\n
address_offset : 0x0 Bytes (0x0)
size : 0x184 byte (0x0)
mem_usage : registers
protection :
Clock Transition Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TRMD : Status and control of the clock transition mode
bits : 0 - 0 (1 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read
KEY_CODE : Register Key
bits : 16 - 47 (32 bit)
access : read-write
Clock Monitoring Status Clear Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CKMDETC : Clear CKMSTAT
bits : 0 - 3 (4 bit)
access : write
__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read
KEY_CODE : Register Key
bits : 16 - 47 (32 bit)
access : read-write
Clock Monitoring Frequency Lower Setting Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
MNLSET : Lower frequency limit setting for clock monitoring
bits : 0 - 13 (14 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read
KEY_CODE : Register Key
bits : 16 - 47 (32 bit)
access : read-write
Clock Monitoring Frequency Upper Setting Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
MNUSET : Upper frequency limit setting for clock monitoring
bits : 0 - 13 (14 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read
KEY_CODE : Register Key
bits : 16 - 47 (32 bit)
access : read-write
Clock Monitoring Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
MONEN : Clock monitoring function enable
bits : 0 - 0 (1 bit)
access : read-write
DETIRQ : Action at clock error detection
bits : 1 - 2 (2 bit)
access : read-write
MVCLK : Selection of condition to enter clock transition mode
bits : 2 - 4 (3 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 3 - 18 (16 bit)
access : read
KEY_CODE : Register Key
bits : 16 - 47 (32 bit)
access : read-write
Clock Monitoring Status Register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
ZERODET : Clock error factor (target clock stop)
bits : 0 - 0 (1 bit)
access : read
LOWDET : Clock error factor (lower frequency error)
bits : 1 - 2 (2 bit)
access : read
UPDET : Clock error factor (upper frequency error)
bits : 2 - 4 (3 bit)
access : read
REFSTOP : Clock error factor (reference clock stop)
bits : 3 - 6 (4 bit)
access : read
__reserve0 : 0 is always read out.
bits : 4 - 10 (7 bit)
access : read
MONRUN : Clock monitoring function running status
bits : 7 - 14 (8 bit)
access : read
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