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WDT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :

Registers

WDTCTR1

WDTERR

WDTERRCLR

WDTCTR2

WDTCLR

WDTBC


WDTCTR1

Watchdog Timer Control Register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

WDTCTR1 WDTCTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDCK __reserve0 WDCEN __reserve1 KEY_CODE

WDCK : Selection of binary counter clock source
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 10 (7 bit)
access : read

WDCEN : WDT count enable
bits : 7 - 14 (8 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read

KEY_CODE : Register Key
bits : 16 - 47 (32 bit)
access : write


WDTERR

Watchdog Timer Error Flag Register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

WDTERR WDTERR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WDOVF __reserve0 WINERR CLRERR __reserve1

WDOVF : Occurrence of WDT overflow error
bits : 0 - 0 (1 bit)
access : read

__reserve0 : 0 is always read out.
bits : 1 - 2 (2 bit)
access : read

WINERR : Occurrence of WDT window error
bits : 2 - 4 (3 bit)
access : read

CLRERR : Occurrence of WDT clear data error
bits : 3 - 6 (4 bit)
access : read

__reserve1 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read


WDTERRCLR

Watchdog Timer Error Flag Clear Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

WDTERRCLR WDTERRCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDERRC __reserve0 KEY_CODE

WDERRC : Setting bit of WDERRC to 1 clears the corresponding bit of WDTERR.
bits : 0 - 7 (8 bit)
access : write

__reserve0 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read

KEY_CODE : Register Key
bits : 16 - 47 (32 bit)
access : write


WDTCTR2

Watchdog Timer Control Register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

WDTCTR2 WDTCTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDWIN __reserve0 WDSTB __reserve1 KEY_CODE

WDWIN : Settings of the time WDT counter can be cleared (window open period)
bits : 0 - 2 (3 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 3 - 6 (4 bit)
access : read

WDSTB : WDT count control in standby mode (SLEEP mode, DEEPSLEEP mode)
bits : 4 - 9 (6 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 6 - 21 (16 bit)
access : read

KEY_CODE : Register Key
bits : 16 - 47 (32 bit)
access : write


WDTCLR

Watchdog Timer Clear Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

WDTCLR WDTCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WDCL

WDCL : Writing 0xA5 clears WDT counter.
bits : 0 - 7 (8 bit)
access : write


WDTBC

Watchdog Timer Binary Counter
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

WDTBC WDTBC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WDBC

WDBC : Value of WDT binary counter is read out.
bits : 0 - 7 (8 bit)
access : read



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