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PPWM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xF08 byte (0x0)
mem_usage : registers
protection :

Registers

GPWM0MD

GPWM0HRSET

GPWM1MD

GPWM1OUTMD

GPWM1SEL

GPWM1BC

GPWM1BCSTR

GPWM1HRSET

GPWM1SET

GPWM1TCMPHR

GPWM1TCMP

GPWM1DHRDAT

GPWM1DDAT

GPWM0SET

GPWM1DTMCNT

GPWM1DTMSETA

GPWM1DTMSETB

GPWM1ADST

GPWM1ADSTSEL

GPWM1ADBC

GPWM1IRQCNT

GPWM1ADIRQCNT

GPWM1OFF

GPWM1OFFIRQA

GPWM1OFFIRQB

GPWM0TCMPHR

GPWM1PULSECNT

GPWM1PULSEST

GPWM1DUTYTRGA

GPWM1DUTYTRGB

GPWM1PERITRGA

GPWM1PERITRGB

GPWM1DBUPDATE

GPWM0TCMP

GPWM0DHRDAT

GPWM0DDAT

GPWM0DTMCNT

GPWM2MD

GPWM2OUTMD

GPWM2SEL

GPWM2BC

GPWM2BCSTR

GPWM2HRSET

GPWM2SET

GPWM2TCMPHR

GPWM2TCMP

GPWM2DHRDAT

GPWM2DDAT

GPWM2DTMCNT

GPWM2DTMSETA

GPWM2DTMSETB

GPWM2ADST

GPWM2ADSTSEL

GPWM2ADBC

GPWM2IRQCNT

GPWM2ADIRQCNT

GPWM2OFF

GPWM2OFFIRQA

GPWM2OFFIRQB

GPWM0DTMSETA

GPWM2PULSECNT

GPWM2PULSEST

GPWM2DUTYTRGA

GPWM2DUTYTRGB

GPWM2PERITRGA

GPWM2PERITRGB

GPWM2DBUPDATE

GPWM0DTMSETB

GPWM0ADST

GPWM0ADSTSEL

GPWM0ADBC

GPWM0IRQCNT

GPWM3MD

GPWM3OUTMD

GPWM3SEL

GPWM3BC

GPWM3BCSTR

GPWM3HRSET

GPWM3SET

GPWM3TCMPHR

GPWM3TCMP

GPWM3DHRDAT

GPWM3DDAT

GPWM3DTMCNT

GPWM3DTMSETA

GPWM3DTMSETB

GPWM3ADST

GPWM3ADSTSEL

GPWM3ADBC

GPWM3IRQCNT

GPWM3ADIRQCNT

GPWM3OFF

GPWM3OFFIRQA

GPWM3OFFIRQB

GPWM0ADIRQCNT

GPWM3PULSECNT

GPWM3PULSEST

GPWM3DUTYTRGA

GPWM3DUTYTRGB

GPWM3PERITRGA

GPWM3PERITRGB

GPWM3DBUPDATE

GPWM0OFF

GPWM0OFFIRQA

GPWM0OFFIRQB

GPWM0OUTMD

GPWM0PULSECNT

GPWM4MD

GPWM4OUTMD

GPWM4SEL

GPWM4BC

GPWM4BCSTR

GPWM4HRSET

GPWM4SET

GPWM4TCMPHR

GPWM4TCMP

GPWM4DHRDAT

GPWM4DDAT

GPWM4DTMCNT

GPWM4DTMSETA

GPWM4DTMSETB

GPWM4ADST

GPWM4ADSTSEL

GPWM4ADBC

GPWM4IRQCNT

GPWM4ADIRQCNT

GPWM4OFF

GPWM4OFFIRQA

GPWM4OFFIRQB

GPWM0PULSEST

GPWM4PULSECNT

GPWM4PULSEST

GPWM4DUTYTRGA

GPWM4DUTYTRGB

GPWM4PERITRGA

GPWM4PERITRGB

GPWM4DBUPDATE

GPWM0DUTYTRGA

GPWM0DUTYTRGB

GPWM0PERITRGA

GPWM0PERITRGB

GPWM0DBUPDATE

GPWM5MD

GPWM5OUTMD

GPWM5SEL

GPWM5BC

GPWM5BCSTR

GPWM5HRSET

GPWM5SET

GPWM5TCMPHR

GPWM5TCMP

GPWM5DHRDAT

GPWM5DDAT

GPWM5DTMCNT

GPWM5DTMSETA

GPWM5DTMSETB

GPWM5ADST

GPWM5ADSTSEL

GPWM5ADBC

GPWM5IRQCNT

GPWM5ADIRQCNT

GPWM5OFF

GPWM5OFFIRQA

GPWM5OFFIRQB

GPWM5PULSECNT

GPWM5PULSEST

GPWM5DUTYTRGA

GPWM5DUTYTRGB

GPWM5PERITRGA

GPWM5PERITRGB

GPWM5DBUPDATE

GPWM6MD

GPWM6OUTMD

GPWM6SEL

GPWM6BC

GPWM6BCSTR

GPWM6HRSET

GPWM6SET

GPWM6TCMPHR

GPWM6TCMP

GPWM6DHRDAT

GPWM6DDAT

GPWM6DTMCNT

GPWM6DTMSETA

GPWM6DTMSETB

GPWM6ADST

GPWM6ADSTSEL

GPWM6ADBC

GPWM6IRQCNT

GPWM6ADIRQCNT

GPWM6OFF

GPWM6OFFIRQA

GPWM6OFFIRQB

GPWM6PULSECNT

GPWM6PULSEST

GPWM6DUTYTRGA

GPWM6DUTYTRGB

GPWM6PERITRGA

GPWM6PERITRGB

GPWM6DBUPDATE

GPWM7MD

GPWM7OUTMD

GPWM7SEL

GPWM7BC

GPWM7BCSTR

GPWM7HRSET

GPWM7SET

GPWM7TCMPHR

GPWM7TCMP

GPWM7DHRDAT

GPWM7DDAT

GPWM7DTMCNT

GPWM7DTMSETA

GPWM7DTMSETB

GPWM7ADST

GPWM7ADSTSEL

GPWM7ADBC

GPWM7IRQCNT

GPWM7ADIRQCNT

GPWM7OFF

GPWM7OFFIRQA

GPWM7OFFIRQB

GPWM7PULSECNT

GPWM7PULSEST

GPWM7DUTYTRGA

GPWM7DUTYTRGB

GPWM7PERITRGA

GPWM7PERITRGB

GPWM7DBUPDATE

GPWM0SEL

GPWM8MD

GPWM8OUTMD

GPWM8SEL

GPWM8BC

GPWM8BCSTR

GPWM8HRSET

GPWM8SET

GPWM8TCMPHR

GPWM8TCMP

GPWM8DHRDAT

GPWM8DDAT

GPWM8DTMCNT

GPWM8DTMSETA

GPWM8DTMSETB

GPWM8ADST

GPWM8ADSTSEL

GPWM8ADBC

GPWM8IRQCNT

GPWM8ADIRQCNT

GPWM8OFF

GPWM8OFFIRQA

GPWM8OFFIRQB

GPWM8PULSECNT

GPWM8PULSEST

GPWM8DUTYTRGA

GPWM8DUTYTRGB

GPWM8PERITRGA

GPWM8PERITRGB

GPWM8DBUPDATE

GPWM9MD

GPWM9OUTMD

GPWM9SEL

GPWM9BC

GPWM9BCSTR

GPWM9SET

GPWM9TCMP

GPWM9DDAT

GPWM9DTMCNT

GPWM9DTMSETA

GPWM9DTMSETB

GPWM9ADST

GPWM9ADSTSEL

GPWM9ADBC

GPWM9IRQCNT

GPWM9ADIRQCNT

GPWM9OFF

GPWM9OFFIRQA

GPWM9OFFIRQB

GPWM9PULSECNT

GPWM9PULSEST

GPWM9DUTYTRGA

GPWM9DUTYTRGB

GPWM9PERITRGA

GPWM9PERITRGB

GPWM9DBUPDATE

GPWM0BC

GPWM0BCSTR

GPWMC_DBUPALL

GPWMC_PINSEL


GPWM0MD

GPWM0 Mode Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0MD GPWM0MD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAVEMDn TCENn HRSELn HRPRENn SYNCENn DUPENn PCRBENn PCRAENn SDSELBn SDSELAn __reserve0 CLKSELn __reserve1 SFTENn SDIRn __reserve2

WAVEMDn : PWM waveform mode select
bits : 0 - 0 (1 bit)
access : read-write

TCENn : PWM Operation control
bits : 1 - 2 (2 bit)
access : read-write

HRSELn : High resolution output function enable
bits : 2 - 4 (3 bit)
access : read-write

HRPRENn : High resolution cycle function enable
bits : 3 - 6 (4 bit)
access : read-write

SYNCENn : Synchronous start function (MFA) enable
bits : 4 - 8 (5 bit)
access : read-write

DUPENn : Double buffer updating enable register selection
bits : 5 - 10 (6 bit)
access : read-write

PCRBENn : Double buffer load timing enable (GPWMnBC overflow)
bits : 6 - 12 (7 bit)
access : read-write

PCRAENn : Double buffer load timing enable (GPWMnBC underflow)
bits : 7 - 14 (8 bit)
access : read-write

SDSELBn : GPWMnSEL buffer mode
bits : 8 - 16 (9 bit)
access : read-write

SDSELAn : GPWMnOUTMD buffer mode
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 20 (11 bit)
access : read

CLKSELn : Count clock selection
bits : 11 - 22 (12 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 12 - 24 (13 bit)
access : read

SFTENn : PWM output shift function enable
bits : 13 - 26 (14 bit)
access : read-write

SDIRn : Shift direction control
bits : 14 - 28 (15 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 15 - 30 (16 bit)
access : read


GPWM0HRSET

GPWM0 High Resolutio0 Cycle Setti0g Register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0HRSET GPWM0HRSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRSETn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRSETn : Set high resolution cycle
bits : 11 - 26 (16 bit)
access : read-write


GPWM1MD

GPWM1 Mode Register
address_offset : 0x100 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1MD GPWM1MD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAVEMDn TCENn HRSELn HRPRENn SYNCENn DUPENn PCRBENn PCRAENn SDSELBn SDSELAn __reserve0 CLKSELn __reserve1 SFTENn SDIRn __reserve2

WAVEMDn : PWM waveform mode select
bits : 0 - 0 (1 bit)
access : read-write

TCENn : PWM Operation control
bits : 1 - 2 (2 bit)
access : read-write

HRSELn : High resolution output function enable
bits : 2 - 4 (3 bit)
access : read-write

HRPRENn : High resolution cycle function enable
bits : 3 - 6 (4 bit)
access : read-write

SYNCENn : Synchronous start function (MFA) enable
bits : 4 - 8 (5 bit)
access : read-write

DUPENn : Double buffer updating enable register selection
bits : 5 - 10 (6 bit)
access : read-write

PCRBENn : Double buffer load timing enable (GPWMnBC overflow)
bits : 6 - 12 (7 bit)
access : read-write

PCRAENn : Double buffer load timing enable (GPWMnBC underflow)
bits : 7 - 14 (8 bit)
access : read-write

SDSELBn : GPWMnSEL buffer mode
bits : 8 - 16 (9 bit)
access : read-write

SDSELAn : GPWMnOUTMD buffer mode
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 20 (11 bit)
access : read

CLKSELn : Count clock selection
bits : 11 - 22 (12 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 12 - 24 (13 bit)
access : read

SFTENn : PWM output shift function enable
bits : 13 - 26 (14 bit)
access : read-write

SDIRn : Shift direction control
bits : 14 - 28 (15 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 15 - 30 (16 bit)
access : read


GPWM1OUTMD

GPWM1 Output Polarity Co1trol Register
address_offset : 0x104 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1OUTMD GPWM1OUTMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PXDTn PXDTNn __reserve0

PXDTn : GPWMn output polarity
bits : 0 - 0 (1 bit)
access : read-write

PXDTNn : NGPWMn output polarity
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM1SEL

GPWM1 Output Co1trol Register
address_offset : 0x108 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1SEL GPWM1SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTLVn OTLVNn PSELn PSELNn __reserve0

OTLVn : GPWMn High/Low-level output
bits : 0 - 0 (1 bit)
access : read-write

OTLVNn : NGPWMn High/Low-level output
bits : 1 - 2 (2 bit)
access : read-write

PSELn : GPWMn output sources
bits : 2 - 4 (3 bit)
access : read-write

PSELNn : NGPWMn output sources
bits : 3 - 6 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read


GPWM1BC

GPWM1BC Value Read Register
address_offset : 0x10C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1BC GPWM1BC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCn

BCn : Read the binary counter value of GPWMn
bits : 0 - 15 (16 bit)
access : read


GPWM1BCSTR

GPWM1BC Status Read Register
address_offset : 0x10E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1BCSTR GPWM1BCSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRn __reserve0

STRn : GPWMn binary counter's counting status read
bits : 0 - 0 (1 bit)
access : read

__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read


GPWM1HRSET

GPWM1 High Resolutio1 Cycle Setti1g Register
address_offset : 0x110 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1HRSET GPWM1HRSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRSETn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRSETn : Set high resolution cycle
bits : 11 - 26 (16 bit)
access : read-write


GPWM1SET

GPWM1 Cycle Setti1g Register
address_offset : 0x112 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1SET GPWM1SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETn

SETn : Set the cycle to the GPWMn 16-bit counter.
bits : 0 - 15 (16 bit)
access : read-write


GPWM1TCMPHR

GPWM1 High Resolutio1 Phase Compariso1 Setti1g Register
address_offset : 0x114 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1TCMPHR GPWM1TCMPHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRTCPn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRTCPn : Set phase comparison high resolution
bits : 11 - 26 (16 bit)
access : read-write


GPWM1TCMP

GPWM1 Phase Compariso1 Setti1g Register
address_offset : 0x116 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1TCMP GPWM1TCMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCPn

TCPn : Set the timing to change output of GPWMn.
bits : 0 - 15 (16 bit)
access : read-write


GPWM1DHRDAT

GPWM1 High Resolutio1 Output Shift Amou1t Setti1g Register
address_offset : 0x118 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1DHRDAT GPWM1DHRDAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRSTIMn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRSTIMn : Set high resolution output shift amount
bits : 11 - 26 (16 bit)
access : read-write


GPWM1DDAT

GPWM1 Output Shift Amou1t Setti1g Register
address_offset : 0x11A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1DDAT GPWM1DDAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STIMn

STIMn : Set GPWMn output shift amount
bits : 0 - 15 (16 bit)
access : read-write


GPWM0SET

GPWM0 Cycle Setti0g Register
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0SET GPWM0SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETn

SETn : Set the cycle to the GPWMn 16-bit counter.
bits : 0 - 15 (16 bit)
access : read-write


GPWM1DTMCNT

GPWM1 Dead Time Co1trol Register
address_offset : 0x120 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1DTMCNT GPWM1DTMCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTENn ORMDn NORMDn SLFCNTn __reserve0

DTENn : Dead time insertion
bits : 0 - 0 (1 bit)
access : read-write

ORMDn : GPWMn dead time insertion logic
bits : 1 - 2 (2 bit)
access : read-write

NORMDn : NGPWMn dead time insertion logic
bits : 2 - 4 (3 bit)
access : read-write

SLFCNTn : Dead time width automatic control enable
bits : 3 - 6 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read


GPWM1DTMSETA

GPWM1 Dead Time Setti1g Register A
address_offset : 0x124 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1DTMSETA GPWM1DTMSETA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTSTAn __reserve0

DTSTAn : Set dead time for GPWMn.
bits : 0 - 9 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM1DTMSETB

GPWM1 Dead Time Setti1g Register B
address_offset : 0x126 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1DTMSETB GPWM1DTMSETB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTSTBn __reserve0

DTSTBn : Set dead time for NGPWMn.
bits : 0 - 9 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM1ADST

GPWM1 Sy1chro1ous Trigger Setti1g Register
address_offset : 0x128 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1ADST GPWM1ADST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PASTn

PASTn : Set the value of starting GPWMn synchronous A/D.
bits : 0 - 15 (16 bit)
access : read-write


GPWM1ADSTSEL

GPWM1 Sy1chro1ous Trigger Polarity Selectio1 Register
address_offset : 0x12A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1ADSTSEL GPWM1ADSTSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PASTUPn PASTDNn __reserve0

PASTUPn : Set the timing of synchronous trigger generation.
bits : 0 - 0 (1 bit)
access : read-write

PASTDNn : Set the timing of synchronous trigger generation.
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM1ADBC

GPWM1 Sy1chro1ous Bi1ary Cou1ter Read Register
address_offset : 0x12C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1ADBC GPWM1ADBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADBCn

ADBCn : Read the binary count for starting GPWMn synchronous A/D.
bits : 0 - 15 (16 bit)
access : read


GPWM1IRQCNT

GPWM1 UDF/OVF I1terrupt Output Co1trol Register
address_offset : 0x130 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1IRQCNT GPWM1IRQCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDFCNTn UDFSCNTn OVFCNTn OVFSCNTn

UDFCNTn : Number of times setting for GPWMn underflow interrupt (Second time or later)
bits : 0 - 3 (4 bit)
access : read-write

UDFSCNTn : Number of times setting for GPWMn underflow interrupt (First time)
bits : 4 - 11 (8 bit)
access : read-write

OVFCNTn : Number of times setting for GPWMn overflow interrupt (Second time or later)
bits : 8 - 19 (12 bit)
access : read-write

OVFSCNTn : Number of times setting for GPWMn overflow interrupt (First time)
bits : 12 - 27 (16 bit)
access : read-write


GPWM1ADIRQCNT

GPWM1 A/D Start I1terrupt Output Co1trol Register
address_offset : 0x134 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1ADIRQCNT GPWM1ADIRQCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASTCNTn ASTSCNTn __reserve0

ASTCNTn : Number of times setting for GPWMn synchronous A/D start interrupt (Second time or later)
bits : 0 - 3 (4 bit)
access : read-write

ASTSCNTn : Number of times setting for GPWMn synchronous A/D start interrupt (First time)
bits : 4 - 11 (8 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read


GPWM1OFF

GPWM1 Pi1 Protectio1 Co1trol Register
address_offset : 0x138 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1OFF GPWM1OFF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTENn __reserve0 PRT PRTN __reserve1

OUTENn : GPWMn pin output enable
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 4 (4 bit)
access : read

PRT : GPWMOUTn output pin protection function
bits : 4 - 9 (6 bit)
access : read-write

PRTN : NGPWMOUTn output pin protection function
bits : 6 - 13 (8 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read


GPWM1OFFIRQA

GPWM1 Pi1 Protectio1 Factor Selectio1 Register A
address_offset : 0x13C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1OFFIRQA GPWM1OFFIRQA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ08ENn IRQ09ENn IRQ14ENn IRQ15ENn IRQ18ENn IRQ19ENn NMIENn AD0ERRAENn AD0ERRBENn AD1ERRAENn AD1ERRBENn AD2ERRAENn AD2ERRBENn __reserve0

IRQ00ENn : Protection factor control by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Protection factor control by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ08ENn : Protection factor control by External Interrupt 8
bits : 2 - 4 (3 bit)
access : read-write

IRQ09ENn : Protection factor control by External Interrupt 9
bits : 3 - 6 (4 bit)
access : read-write

IRQ14ENn : Protection factor control by External Interrupt 14
bits : 4 - 8 (5 bit)
access : read-write

IRQ15ENn : Protection factor control by External Interrupt 15
bits : 5 - 10 (6 bit)
access : read-write

IRQ18ENn : Protection factor control by External Interrupt 18
bits : 6 - 12 (7 bit)
access : read-write

IRQ19ENn : Protection factor control by External Interrupt 19
bits : 7 - 14 (8 bit)
access : read-write

NMIENn : Protection factor control by NMI
bits : 8 - 16 (9 bit)
access : read-write

AD0ERRAENn : Protection factor control by A/D0 Conversion Error Detection
bits : 9 - 18 (10 bit)
access : read-write

AD0ERRBENn : Protection factor control by A/D0 Conversion Error Detection B
bits : 10 - 20 (11 bit)
access : read-write

AD1ERRAENn : Protection factor control by A/D1 Conversion Error Detection
bits : 11 - 22 (12 bit)
access : read-write

AD1ERRBENn : Protection factor control by A/D1 Conversion Error Detection B
bits : 12 - 24 (13 bit)
access : read-write

AD2ERRAENn : Protection factor control by A/D2 Conversion Error Detection
bits : 13 - 26 (14 bit)
access : read-write

AD2ERRBENn : Protection factor control by A/D2 Conversion Error Detection B
bits : 14 - 28 (15 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 15 - 30 (16 bit)
access : read


GPWM1OFFIRQB

GPWM1 Pi1 Protectio1 Factor Selectio1 Register B
address_offset : 0x13E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1OFFIRQB GPWM1OFFIRQB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Protection factor control by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Protection factor control by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Protection factor control by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Protection factor control by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Protection factor control by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Protection factor control by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Protection factor control by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Protection factor control by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Protection factor control by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Protection factor control by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM0TCMPHR

GPWM0 High Resolutio0 Phase Compariso0 Setti0g Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0TCMPHR GPWM0TCMPHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRTCPn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRTCPn : Set phase comparison high resolution
bits : 11 - 26 (16 bit)
access : read-write


GPWM1PULSECNT

GPWM1 Pulse Co1trol Register
address_offset : 0x140 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1PULSECNT GPWM1PULSECNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTCTENn DTACTSELn DTCTASELn DTCTBSELn DTOVFRETn DTUDFRETn PRCTENn PRACTSELn PRRETSELn __reserve0

DTCTENn : Duty Cut enable
bits : 0 - 0 (1 bit)
access : read-write

DTACTSELn : Duty cut start factor polarity selection
bits : 1 - 2 (2 bit)
access : read-write

DTCTASELn : GPWMn operation selection when the duty cut
bits : 2 - 5 (4 bit)
access : read-write

DTCTBSELn : NGPWMn operation selection when the duty cut
bits : 4 - 9 (6 bit)
access : read-write

DTOVFRETn : Control of the return of duty cut by the overflow
bits : 6 - 12 (7 bit)
access : read-write

DTUDFRETn : Control of the return of duty cut by the underflow
bits : 7 - 14 (8 bit)
access : read-write

PRCTENn : Period Cut enable
bits : 8 - 16 (9 bit)
access : read-write

PRACTSELn : Period cut start factor polarity selection
bits : 9 - 18 (10 bit)
access : read-write

PRRETSELn : Period cut operation selection
bits : 10 - 20 (11 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 11 - 26 (16 bit)
access : read


GPWM1PULSEST

GPWM1 Pulse Co1trol Status Register
address_offset : 0x144 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1PULSEST GPWM1PULSEST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTCTSTn PRCTSTn __reserve0

DTCTSTn : Duty cut state
bits : 0 - 0 (1 bit)
access : read-write

PRCTSTn : Period cut state
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM1DUTYTRGA

GPWM1 Duty Cut Factor Selectio1 Register A
address_offset : 0x148 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1DUTYTRGA GPWM1DUTYTRGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ02ENn IRQ03ENn IRQ04ENn IRQ05ENn IRQ06ENn IRQ07ENn IRQ08ENn IRQ09ENn IRQ10ENn IRQ11ENn IRQ12ENn IRQ13ENn IRQ14ENn IRQ15ENn

IRQ00ENn : Duty cut start factor selection by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Duty cut start factor selection by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ02ENn : Duty cut start factor selection by External Interrupt 2
bits : 2 - 4 (3 bit)
access : read-write

IRQ03ENn : Duty cut start factor selection by External Interrupt 3
bits : 3 - 6 (4 bit)
access : read-write

IRQ04ENn : Duty cut start factor selection by External Interrupt 4
bits : 4 - 8 (5 bit)
access : read-write

IRQ05ENn : Duty cut start factor selection by External Interrupt 5
bits : 5 - 10 (6 bit)
access : read-write

IRQ06ENn : Duty cut start factor selection by External Interrupt 6
bits : 6 - 12 (7 bit)
access : read-write

IRQ07ENn : Duty cut start factor selection by External Interrupt 7
bits : 7 - 14 (8 bit)
access : read-write

IRQ08ENn : Duty cut start factor selection by External Interrupt 8
bits : 8 - 16 (9 bit)
access : read-write

IRQ09ENn : Duty cut start factor selection by External Interrupt 9
bits : 9 - 18 (10 bit)
access : read-write

IRQ10ENn : Duty cut start factor selection by External Interrupt 10
bits : 10 - 20 (11 bit)
access : read-write

IRQ11ENn : Duty cut start factor selection by External Interrupt 11
bits : 11 - 22 (12 bit)
access : read-write

IRQ12ENn : Duty cut start factor selection by External Interrupt 12
bits : 12 - 24 (13 bit)
access : read-write

IRQ13ENn : Duty cut start factor selection by External Interrupt 13
bits : 13 - 26 (14 bit)
access : read-write

IRQ14ENn : Duty cut start factor selection by External Interrupt 14
bits : 14 - 28 (15 bit)
access : read-write

IRQ15ENn : Duty cut start factor selection by External Interrupt 15
bits : 15 - 30 (16 bit)
access : read-write


GPWM1DUTYTRGB

GPWM1 Duty Cut Factor Selectio1 Register B
address_offset : 0x14A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1DUTYTRGB GPWM1DUTYTRGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Duty cut start factor selection by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Duty cut start factor selection by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Duty cut start factor selection by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Duty cut start factor selection by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Duty cut start factor selection by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Duty cut start factor selection by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Duty cut start factor selection by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Duty cut start factor selection by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Duty cut start factor selection by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Duty cut start factor selection by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM1PERITRGA

GPWM1 Period Cut Factor Selectio1 Register A
address_offset : 0x14C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1PERITRGA GPWM1PERITRGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ02ENn IRQ03ENn IRQ04ENn IRQ05ENn IRQ06ENn IRQ07ENn IRQ08ENn IRQ09ENn IRQ10ENn IRQ11ENn IRQ12ENn IRQ13ENn IRQ14ENn IRQ15ENn

IRQ00ENn : Period cut start factor selection by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Period cut start factor selection by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ02ENn : Period cut start factor selection by External Interrupt 2
bits : 2 - 4 (3 bit)
access : read-write

IRQ03ENn : Period cut start factor selection by External Interrupt 3
bits : 3 - 6 (4 bit)
access : read-write

IRQ04ENn : Period cut start factor selection by External Interrupt 4
bits : 4 - 8 (5 bit)
access : read-write

IRQ05ENn : Period cut start factor selection by External Interrupt 5
bits : 5 - 10 (6 bit)
access : read-write

IRQ06ENn : Period cut start factor selection by External Interrupt 6
bits : 6 - 12 (7 bit)
access : read-write

IRQ07ENn : Period cut start factor selection by External Interrupt 7
bits : 7 - 14 (8 bit)
access : read-write

IRQ08ENn : Period cut start factor selection by External Interrupt 8
bits : 8 - 16 (9 bit)
access : read-write

IRQ09ENn : Period cut start factor selection by External Interrupt 9
bits : 9 - 18 (10 bit)
access : read-write

IRQ10ENn : Period cut start factor selection by External Interrupt 10
bits : 10 - 20 (11 bit)
access : read-write

IRQ11ENn : Period cut start factor selection by External Interrupt 11
bits : 11 - 22 (12 bit)
access : read-write

IRQ12ENn : Period cut start factor selection by External Interrupt 12
bits : 12 - 24 (13 bit)
access : read-write

IRQ13ENn : Period cut start factor selection by External Interrupt 13
bits : 13 - 26 (14 bit)
access : read-write

IRQ14ENn : Period cut start factor selection by External Interrupt 14
bits : 14 - 28 (15 bit)
access : read-write

IRQ15ENn : Period cut start factor selection by External Interrupt 15
bits : 15 - 30 (16 bit)
access : read-write


GPWM1PERITRGB

GPWM1 Period Cut Factor Selectio1 Register B
address_offset : 0x14E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1PERITRGB GPWM1PERITRGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Period cut start factor selection by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Period cut start factor selection by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Period cut start factor selection by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Period cut start factor selection by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Period cut start factor selection by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Period cut start factor selection by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Period cut start factor selection by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Period cut start factor selection by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Period cut start factor selection by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Period cut start factor selection by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM1DBUPDATE

GPWM1 Double Buffer Updati1g E1able Register
address_offset : 0x150 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM1DBUPDATE GPWM1DBUPDATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUPn __reserve0

DUPn : Double buffer updating enable
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read


GPWM0TCMP

GPWM0 Phase Compariso0 Setti0g Register
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0TCMP GPWM0TCMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCPn

TCPn : Set the timing to change output of GPWMn.
bits : 0 - 15 (16 bit)
access : read-write


GPWM0DHRDAT

GPWM0 High Resolutio0 Output Shift Amou0t Setti0g Register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0DHRDAT GPWM0DHRDAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRSTIMn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRSTIMn : Set high resolution output shift amount
bits : 11 - 26 (16 bit)
access : read-write


GPWM0DDAT

GPWM0 Output Shift Amou0t Setti0g Register
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0DDAT GPWM0DDAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STIMn

STIMn : Set GPWMn output shift amount
bits : 0 - 15 (16 bit)
access : read-write


GPWM0DTMCNT

GPWM0 Dead Time Co0trol Register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0DTMCNT GPWM0DTMCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTENn ORMDn NORMDn SLFCNTn __reserve0

DTENn : Dead time insertion
bits : 0 - 0 (1 bit)
access : read-write

ORMDn : GPWMn dead time insertion logic
bits : 1 - 2 (2 bit)
access : read-write

NORMDn : NGPWMn dead time insertion logic
bits : 2 - 4 (3 bit)
access : read-write

SLFCNTn : Dead time width automatic control enable
bits : 3 - 6 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read


GPWM2MD

GPWM2 Mode Register
address_offset : 0x200 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2MD GPWM2MD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAVEMDn TCENn HRSELn HRPRENn SYNCENn DUPENn PCRBENn PCRAENn SDSELBn SDSELAn __reserve0 CLKSELn __reserve1 SFTENn SDIRn __reserve2

WAVEMDn : PWM waveform mode select
bits : 0 - 0 (1 bit)
access : read-write

TCENn : PWM Operation control
bits : 1 - 2 (2 bit)
access : read-write

HRSELn : High resolution output function enable
bits : 2 - 4 (3 bit)
access : read-write

HRPRENn : High resolution cycle function enable
bits : 3 - 6 (4 bit)
access : read-write

SYNCENn : Synchronous start function (MFA) enable
bits : 4 - 8 (5 bit)
access : read-write

DUPENn : Double buffer updating enable register selection
bits : 5 - 10 (6 bit)
access : read-write

PCRBENn : Double buffer load timing enable (GPWMnBC overflow)
bits : 6 - 12 (7 bit)
access : read-write

PCRAENn : Double buffer load timing enable (GPWMnBC underflow)
bits : 7 - 14 (8 bit)
access : read-write

SDSELBn : GPWMnSEL buffer mode
bits : 8 - 16 (9 bit)
access : read-write

SDSELAn : GPWMnOUTMD buffer mode
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 20 (11 bit)
access : read

CLKSELn : Count clock selection
bits : 11 - 22 (12 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 12 - 24 (13 bit)
access : read

SFTENn : PWM output shift function enable
bits : 13 - 26 (14 bit)
access : read-write

SDIRn : Shift direction control
bits : 14 - 28 (15 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 15 - 30 (16 bit)
access : read


GPWM2OUTMD

GPWM2 Output Polarity Co2trol Register
address_offset : 0x204 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2OUTMD GPWM2OUTMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PXDTn PXDTNn __reserve0

PXDTn : GPWMn output polarity
bits : 0 - 0 (1 bit)
access : read-write

PXDTNn : NGPWMn output polarity
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM2SEL

GPWM2 Output Co2trol Register
address_offset : 0x208 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2SEL GPWM2SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTLVn OTLVNn PSELn PSELNn __reserve0

OTLVn : GPWMn High/Low-level output
bits : 0 - 0 (1 bit)
access : read-write

OTLVNn : NGPWMn High/Low-level output
bits : 1 - 2 (2 bit)
access : read-write

PSELn : GPWMn output sources
bits : 2 - 4 (3 bit)
access : read-write

PSELNn : NGPWMn output sources
bits : 3 - 6 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read


GPWM2BC

GPWM2BC Value Read Register
address_offset : 0x20C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2BC GPWM2BC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCn

BCn : Read the binary counter value of GPWMn
bits : 0 - 15 (16 bit)
access : read


GPWM2BCSTR

GPWM2BC Status Read Register
address_offset : 0x20E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2BCSTR GPWM2BCSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRn __reserve0

STRn : GPWMn binary counter's counting status read
bits : 0 - 0 (1 bit)
access : read

__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read


GPWM2HRSET

GPWM2 High Resolutio2 Cycle Setti2g Register
address_offset : 0x210 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2HRSET GPWM2HRSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRSETn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRSETn : Set high resolution cycle
bits : 11 - 26 (16 bit)
access : read-write


GPWM2SET

GPWM2 Cycle Setti2g Register
address_offset : 0x212 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2SET GPWM2SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETn

SETn : Set the cycle to the GPWMn 16-bit counter.
bits : 0 - 15 (16 bit)
access : read-write


GPWM2TCMPHR

GPWM2 High Resolutio2 Phase Compariso2 Setti2g Register
address_offset : 0x214 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2TCMPHR GPWM2TCMPHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRTCPn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRTCPn : Set phase comparison high resolution
bits : 11 - 26 (16 bit)
access : read-write


GPWM2TCMP

GPWM2 Phase Compariso2 Setti2g Register
address_offset : 0x216 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2TCMP GPWM2TCMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCPn

TCPn : Set the timing to change output of GPWMn.
bits : 0 - 15 (16 bit)
access : read-write


GPWM2DHRDAT

GPWM2 High Resolutio2 Output Shift Amou2t Setti2g Register
address_offset : 0x218 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2DHRDAT GPWM2DHRDAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRSTIMn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRSTIMn : Set high resolution output shift amount
bits : 11 - 26 (16 bit)
access : read-write


GPWM2DDAT

GPWM2 Output Shift Amou2t Setti2g Register
address_offset : 0x21A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2DDAT GPWM2DDAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STIMn

STIMn : Set GPWMn output shift amount
bits : 0 - 15 (16 bit)
access : read-write


GPWM2DTMCNT

GPWM2 Dead Time Co2trol Register
address_offset : 0x220 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2DTMCNT GPWM2DTMCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTENn ORMDn NORMDn SLFCNTn __reserve0

DTENn : Dead time insertion
bits : 0 - 0 (1 bit)
access : read-write

ORMDn : GPWMn dead time insertion logic
bits : 1 - 2 (2 bit)
access : read-write

NORMDn : NGPWMn dead time insertion logic
bits : 2 - 4 (3 bit)
access : read-write

SLFCNTn : Dead time width automatic control enable
bits : 3 - 6 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read


GPWM2DTMSETA

GPWM2 Dead Time Setti2g Register A
address_offset : 0x224 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2DTMSETA GPWM2DTMSETA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTSTAn __reserve0

DTSTAn : Set dead time for GPWMn.
bits : 0 - 9 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM2DTMSETB

GPWM2 Dead Time Setti2g Register B
address_offset : 0x226 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2DTMSETB GPWM2DTMSETB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTSTBn __reserve0

DTSTBn : Set dead time for NGPWMn.
bits : 0 - 9 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM2ADST

GPWM2 Sy2chro2ous Trigger Setti2g Register
address_offset : 0x228 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2ADST GPWM2ADST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PASTn

PASTn : Set the value of starting GPWMn synchronous A/D.
bits : 0 - 15 (16 bit)
access : read-write


GPWM2ADSTSEL

GPWM2 Sy2chro2ous Trigger Polarity Selectio2 Register
address_offset : 0x22A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2ADSTSEL GPWM2ADSTSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PASTUPn PASTDNn __reserve0

PASTUPn : Set the timing of synchronous trigger generation.
bits : 0 - 0 (1 bit)
access : read-write

PASTDNn : Set the timing of synchronous trigger generation.
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM2ADBC

GPWM2 Sy2chro2ous Bi2ary Cou2ter Read Register
address_offset : 0x22C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2ADBC GPWM2ADBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADBCn

ADBCn : Read the binary count for starting GPWMn synchronous A/D.
bits : 0 - 15 (16 bit)
access : read


GPWM2IRQCNT

GPWM2 UDF/OVF I2terrupt Output Co2trol Register
address_offset : 0x230 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2IRQCNT GPWM2IRQCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDFCNTn UDFSCNTn OVFCNTn OVFSCNTn

UDFCNTn : Number of times setting for GPWMn underflow interrupt (Second time or later)
bits : 0 - 3 (4 bit)
access : read-write

UDFSCNTn : Number of times setting for GPWMn underflow interrupt (First time)
bits : 4 - 11 (8 bit)
access : read-write

OVFCNTn : Number of times setting for GPWMn overflow interrupt (Second time or later)
bits : 8 - 19 (12 bit)
access : read-write

OVFSCNTn : Number of times setting for GPWMn overflow interrupt (First time)
bits : 12 - 27 (16 bit)
access : read-write


GPWM2ADIRQCNT

GPWM2 A/D Start I2terrupt Output Co2trol Register
address_offset : 0x234 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2ADIRQCNT GPWM2ADIRQCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASTCNTn ASTSCNTn __reserve0

ASTCNTn : Number of times setting for GPWMn synchronous A/D start interrupt (Second time or later)
bits : 0 - 3 (4 bit)
access : read-write

ASTSCNTn : Number of times setting for GPWMn synchronous A/D start interrupt (First time)
bits : 4 - 11 (8 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read


GPWM2OFF

GPWM2 Pi2 Protectio2 Co2trol Register
address_offset : 0x238 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2OFF GPWM2OFF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTENn __reserve0 PRT PRTN __reserve1

OUTENn : GPWMn pin output enable
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 4 (4 bit)
access : read

PRT : GPWMOUTn output pin protection function
bits : 4 - 9 (6 bit)
access : read-write

PRTN : NGPWMOUTn output pin protection function
bits : 6 - 13 (8 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read


GPWM2OFFIRQA

GPWM2 Pi2 Protectio2 Factor Selectio2 Register A
address_offset : 0x23C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2OFFIRQA GPWM2OFFIRQA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ08ENn IRQ09ENn IRQ14ENn IRQ15ENn IRQ18ENn IRQ19ENn NMIENn AD0ERRAENn AD0ERRBENn AD1ERRAENn AD1ERRBENn AD2ERRAENn AD2ERRBENn __reserve0

IRQ00ENn : Protection factor control by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Protection factor control by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ08ENn : Protection factor control by External Interrupt 8
bits : 2 - 4 (3 bit)
access : read-write

IRQ09ENn : Protection factor control by External Interrupt 9
bits : 3 - 6 (4 bit)
access : read-write

IRQ14ENn : Protection factor control by External Interrupt 14
bits : 4 - 8 (5 bit)
access : read-write

IRQ15ENn : Protection factor control by External Interrupt 15
bits : 5 - 10 (6 bit)
access : read-write

IRQ18ENn : Protection factor control by External Interrupt 18
bits : 6 - 12 (7 bit)
access : read-write

IRQ19ENn : Protection factor control by External Interrupt 19
bits : 7 - 14 (8 bit)
access : read-write

NMIENn : Protection factor control by NMI
bits : 8 - 16 (9 bit)
access : read-write

AD0ERRAENn : Protection factor control by A/D0 Conversion Error Detection
bits : 9 - 18 (10 bit)
access : read-write

AD0ERRBENn : Protection factor control by A/D0 Conversion Error Detection B
bits : 10 - 20 (11 bit)
access : read-write

AD1ERRAENn : Protection factor control by A/D1 Conversion Error Detection
bits : 11 - 22 (12 bit)
access : read-write

AD1ERRBENn : Protection factor control by A/D1 Conversion Error Detection B
bits : 12 - 24 (13 bit)
access : read-write

AD2ERRAENn : Protection factor control by A/D2 Conversion Error Detection
bits : 13 - 26 (14 bit)
access : read-write

AD2ERRBENn : Protection factor control by A/D2 Conversion Error Detection B
bits : 14 - 28 (15 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 15 - 30 (16 bit)
access : read


GPWM2OFFIRQB

GPWM2 Pi2 Protectio2 Factor Selectio2 Register B
address_offset : 0x23E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2OFFIRQB GPWM2OFFIRQB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Protection factor control by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Protection factor control by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Protection factor control by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Protection factor control by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Protection factor control by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Protection factor control by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Protection factor control by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Protection factor control by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Protection factor control by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Protection factor control by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM0DTMSETA

GPWM0 Dead Time Setti0g Register A
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0DTMSETA GPWM0DTMSETA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTSTAn __reserve0

DTSTAn : Set dead time for GPWMn.
bits : 0 - 9 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM2PULSECNT

GPWM2 Pulse Co2trol Register
address_offset : 0x240 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2PULSECNT GPWM2PULSECNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTCTENn DTACTSELn DTCTASELn DTCTBSELn DTOVFRETn DTUDFRETn PRCTENn PRACTSELn PRRETSELn __reserve0

DTCTENn : Duty Cut enable
bits : 0 - 0 (1 bit)
access : read-write

DTACTSELn : Duty cut start factor polarity selection
bits : 1 - 2 (2 bit)
access : read-write

DTCTASELn : GPWMn operation selection when the duty cut
bits : 2 - 5 (4 bit)
access : read-write

DTCTBSELn : NGPWMn operation selection when the duty cut
bits : 4 - 9 (6 bit)
access : read-write

DTOVFRETn : Control of the return of duty cut by the overflow
bits : 6 - 12 (7 bit)
access : read-write

DTUDFRETn : Control of the return of duty cut by the underflow
bits : 7 - 14 (8 bit)
access : read-write

PRCTENn : Period Cut enable
bits : 8 - 16 (9 bit)
access : read-write

PRACTSELn : Period cut start factor polarity selection
bits : 9 - 18 (10 bit)
access : read-write

PRRETSELn : Period cut operation selection
bits : 10 - 20 (11 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 11 - 26 (16 bit)
access : read


GPWM2PULSEST

GPWM2 Pulse Co2trol Status Register
address_offset : 0x244 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2PULSEST GPWM2PULSEST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTCTSTn PRCTSTn __reserve0

DTCTSTn : Duty cut state
bits : 0 - 0 (1 bit)
access : read-write

PRCTSTn : Period cut state
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM2DUTYTRGA

GPWM2 Duty Cut Factor Selectio2 Register A
address_offset : 0x248 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2DUTYTRGA GPWM2DUTYTRGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ02ENn IRQ03ENn IRQ04ENn IRQ05ENn IRQ06ENn IRQ07ENn IRQ08ENn IRQ09ENn IRQ10ENn IRQ11ENn IRQ12ENn IRQ13ENn IRQ14ENn IRQ15ENn

IRQ00ENn : Duty cut start factor selection by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Duty cut start factor selection by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ02ENn : Duty cut start factor selection by External Interrupt 2
bits : 2 - 4 (3 bit)
access : read-write

IRQ03ENn : Duty cut start factor selection by External Interrupt 3
bits : 3 - 6 (4 bit)
access : read-write

IRQ04ENn : Duty cut start factor selection by External Interrupt 4
bits : 4 - 8 (5 bit)
access : read-write

IRQ05ENn : Duty cut start factor selection by External Interrupt 5
bits : 5 - 10 (6 bit)
access : read-write

IRQ06ENn : Duty cut start factor selection by External Interrupt 6
bits : 6 - 12 (7 bit)
access : read-write

IRQ07ENn : Duty cut start factor selection by External Interrupt 7
bits : 7 - 14 (8 bit)
access : read-write

IRQ08ENn : Duty cut start factor selection by External Interrupt 8
bits : 8 - 16 (9 bit)
access : read-write

IRQ09ENn : Duty cut start factor selection by External Interrupt 9
bits : 9 - 18 (10 bit)
access : read-write

IRQ10ENn : Duty cut start factor selection by External Interrupt 10
bits : 10 - 20 (11 bit)
access : read-write

IRQ11ENn : Duty cut start factor selection by External Interrupt 11
bits : 11 - 22 (12 bit)
access : read-write

IRQ12ENn : Duty cut start factor selection by External Interrupt 12
bits : 12 - 24 (13 bit)
access : read-write

IRQ13ENn : Duty cut start factor selection by External Interrupt 13
bits : 13 - 26 (14 bit)
access : read-write

IRQ14ENn : Duty cut start factor selection by External Interrupt 14
bits : 14 - 28 (15 bit)
access : read-write

IRQ15ENn : Duty cut start factor selection by External Interrupt 15
bits : 15 - 30 (16 bit)
access : read-write


GPWM2DUTYTRGB

GPWM2 Duty Cut Factor Selectio2 Register B
address_offset : 0x24A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2DUTYTRGB GPWM2DUTYTRGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Duty cut start factor selection by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Duty cut start factor selection by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Duty cut start factor selection by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Duty cut start factor selection by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Duty cut start factor selection by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Duty cut start factor selection by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Duty cut start factor selection by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Duty cut start factor selection by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Duty cut start factor selection by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Duty cut start factor selection by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM2PERITRGA

GPWM2 Period Cut Factor Selectio2 Register A
address_offset : 0x24C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2PERITRGA GPWM2PERITRGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ02ENn IRQ03ENn IRQ04ENn IRQ05ENn IRQ06ENn IRQ07ENn IRQ08ENn IRQ09ENn IRQ10ENn IRQ11ENn IRQ12ENn IRQ13ENn IRQ14ENn IRQ15ENn

IRQ00ENn : Period cut start factor selection by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Period cut start factor selection by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ02ENn : Period cut start factor selection by External Interrupt 2
bits : 2 - 4 (3 bit)
access : read-write

IRQ03ENn : Period cut start factor selection by External Interrupt 3
bits : 3 - 6 (4 bit)
access : read-write

IRQ04ENn : Period cut start factor selection by External Interrupt 4
bits : 4 - 8 (5 bit)
access : read-write

IRQ05ENn : Period cut start factor selection by External Interrupt 5
bits : 5 - 10 (6 bit)
access : read-write

IRQ06ENn : Period cut start factor selection by External Interrupt 6
bits : 6 - 12 (7 bit)
access : read-write

IRQ07ENn : Period cut start factor selection by External Interrupt 7
bits : 7 - 14 (8 bit)
access : read-write

IRQ08ENn : Period cut start factor selection by External Interrupt 8
bits : 8 - 16 (9 bit)
access : read-write

IRQ09ENn : Period cut start factor selection by External Interrupt 9
bits : 9 - 18 (10 bit)
access : read-write

IRQ10ENn : Period cut start factor selection by External Interrupt 10
bits : 10 - 20 (11 bit)
access : read-write

IRQ11ENn : Period cut start factor selection by External Interrupt 11
bits : 11 - 22 (12 bit)
access : read-write

IRQ12ENn : Period cut start factor selection by External Interrupt 12
bits : 12 - 24 (13 bit)
access : read-write

IRQ13ENn : Period cut start factor selection by External Interrupt 13
bits : 13 - 26 (14 bit)
access : read-write

IRQ14ENn : Period cut start factor selection by External Interrupt 14
bits : 14 - 28 (15 bit)
access : read-write

IRQ15ENn : Period cut start factor selection by External Interrupt 15
bits : 15 - 30 (16 bit)
access : read-write


GPWM2PERITRGB

GPWM2 Period Cut Factor Selectio2 Register B
address_offset : 0x24E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2PERITRGB GPWM2PERITRGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Period cut start factor selection by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Period cut start factor selection by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Period cut start factor selection by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Period cut start factor selection by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Period cut start factor selection by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Period cut start factor selection by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Period cut start factor selection by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Period cut start factor selection by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Period cut start factor selection by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Period cut start factor selection by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM2DBUPDATE

GPWM2 Double Buffer Updati2g E2able Register
address_offset : 0x250 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM2DBUPDATE GPWM2DBUPDATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUPn __reserve0

DUPn : Double buffer updating enable
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read


GPWM0DTMSETB

GPWM0 Dead Time Setti0g Register B
address_offset : 0x26 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0DTMSETB GPWM0DTMSETB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTSTBn __reserve0

DTSTBn : Set dead time for NGPWMn.
bits : 0 - 9 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM0ADST

GPWM0 Sy0chro0ous Trigger Setti0g Register
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0ADST GPWM0ADST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PASTn

PASTn : Set the value of starting GPWMn synchronous A/D.
bits : 0 - 15 (16 bit)
access : read-write


GPWM0ADSTSEL

GPWM0 Sy0chro0ous Trigger Polarity Selectio0 Register
address_offset : 0x2A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0ADSTSEL GPWM0ADSTSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PASTUPn PASTDNn __reserve0

PASTUPn : Set the timing of synchronous trigger generation.
bits : 0 - 0 (1 bit)
access : read-write

PASTDNn : Set the timing of synchronous trigger generation.
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM0ADBC

GPWM0 Sy0chro0ous Bi0ary Cou0ter Read Register
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0ADBC GPWM0ADBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADBCn

ADBCn : Read the binary count for starting GPWMn synchronous A/D.
bits : 0 - 15 (16 bit)
access : read


GPWM0IRQCNT

GPWM0 UDF/OVF I0terrupt Output Co0trol Register
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0IRQCNT GPWM0IRQCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDFCNTn UDFSCNTn OVFCNTn OVFSCNTn

UDFCNTn : Number of times setting for GPWMn underflow interrupt (Second time or later)
bits : 0 - 3 (4 bit)
access : read-write

UDFSCNTn : Number of times setting for GPWMn underflow interrupt (First time)
bits : 4 - 11 (8 bit)
access : read-write

OVFCNTn : Number of times setting for GPWMn overflow interrupt (Second time or later)
bits : 8 - 19 (12 bit)
access : read-write

OVFSCNTn : Number of times setting for GPWMn overflow interrupt (First time)
bits : 12 - 27 (16 bit)
access : read-write


GPWM3MD

GPWM3 Mode Register
address_offset : 0x300 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3MD GPWM3MD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAVEMDn TCENn HRSELn HRPRENn SYNCENn DUPENn PCRBENn PCRAENn SDSELBn SDSELAn __reserve0 CLKSELn __reserve1 SFTENn SDIRn __reserve2

WAVEMDn : PWM waveform mode select
bits : 0 - 0 (1 bit)
access : read-write

TCENn : PWM Operation control
bits : 1 - 2 (2 bit)
access : read-write

HRSELn : High resolution output function enable
bits : 2 - 4 (3 bit)
access : read-write

HRPRENn : High resolution cycle function enable
bits : 3 - 6 (4 bit)
access : read-write

SYNCENn : Synchronous start function (MFA) enable
bits : 4 - 8 (5 bit)
access : read-write

DUPENn : Double buffer updating enable register selection
bits : 5 - 10 (6 bit)
access : read-write

PCRBENn : Double buffer load timing enable (GPWMnBC overflow)
bits : 6 - 12 (7 bit)
access : read-write

PCRAENn : Double buffer load timing enable (GPWMnBC underflow)
bits : 7 - 14 (8 bit)
access : read-write

SDSELBn : GPWMnSEL buffer mode
bits : 8 - 16 (9 bit)
access : read-write

SDSELAn : GPWMnOUTMD buffer mode
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 20 (11 bit)
access : read

CLKSELn : Count clock selection
bits : 11 - 22 (12 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 12 - 24 (13 bit)
access : read

SFTENn : PWM output shift function enable
bits : 13 - 26 (14 bit)
access : read-write

SDIRn : Shift direction control
bits : 14 - 28 (15 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 15 - 30 (16 bit)
access : read


GPWM3OUTMD

GPWM3 Output Polarity Co3trol Register
address_offset : 0x304 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3OUTMD GPWM3OUTMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PXDTn PXDTNn __reserve0

PXDTn : GPWMn output polarity
bits : 0 - 0 (1 bit)
access : read-write

PXDTNn : NGPWMn output polarity
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM3SEL

GPWM3 Output Co3trol Register
address_offset : 0x308 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3SEL GPWM3SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTLVn OTLVNn PSELn PSELNn __reserve0

OTLVn : GPWMn High/Low-level output
bits : 0 - 0 (1 bit)
access : read-write

OTLVNn : NGPWMn High/Low-level output
bits : 1 - 2 (2 bit)
access : read-write

PSELn : GPWMn output sources
bits : 2 - 4 (3 bit)
access : read-write

PSELNn : NGPWMn output sources
bits : 3 - 6 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read


GPWM3BC

GPWM3BC Value Read Register
address_offset : 0x30C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3BC GPWM3BC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCn

BCn : Read the binary counter value of GPWMn
bits : 0 - 15 (16 bit)
access : read


GPWM3BCSTR

GPWM3BC Status Read Register
address_offset : 0x30E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3BCSTR GPWM3BCSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRn __reserve0

STRn : GPWMn binary counter's counting status read
bits : 0 - 0 (1 bit)
access : read

__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read


GPWM3HRSET

GPWM3 High Resolutio3 Cycle Setti3g Register
address_offset : 0x310 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3HRSET GPWM3HRSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRSETn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRSETn : Set high resolution cycle
bits : 11 - 26 (16 bit)
access : read-write


GPWM3SET

GPWM3 Cycle Setti3g Register
address_offset : 0x312 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3SET GPWM3SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETn

SETn : Set the cycle to the GPWMn 16-bit counter.
bits : 0 - 15 (16 bit)
access : read-write


GPWM3TCMPHR

GPWM3 High Resolutio3 Phase Compariso3 Setti3g Register
address_offset : 0x314 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3TCMPHR GPWM3TCMPHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRTCPn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRTCPn : Set phase comparison high resolution
bits : 11 - 26 (16 bit)
access : read-write


GPWM3TCMP

GPWM3 Phase Compariso3 Setti3g Register
address_offset : 0x316 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3TCMP GPWM3TCMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCPn

TCPn : Set the timing to change output of GPWMn.
bits : 0 - 15 (16 bit)
access : read-write


GPWM3DHRDAT

GPWM3 High Resolutio3 Output Shift Amou3t Setti3g Register
address_offset : 0x318 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3DHRDAT GPWM3DHRDAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRSTIMn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRSTIMn : Set high resolution output shift amount
bits : 11 - 26 (16 bit)
access : read-write


GPWM3DDAT

GPWM3 Output Shift Amou3t Setti3g Register
address_offset : 0x31A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3DDAT GPWM3DDAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STIMn

STIMn : Set GPWMn output shift amount
bits : 0 - 15 (16 bit)
access : read-write


GPWM3DTMCNT

GPWM3 Dead Time Co3trol Register
address_offset : 0x320 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3DTMCNT GPWM3DTMCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTENn ORMDn NORMDn SLFCNTn __reserve0

DTENn : Dead time insertion
bits : 0 - 0 (1 bit)
access : read-write

ORMDn : GPWMn dead time insertion logic
bits : 1 - 2 (2 bit)
access : read-write

NORMDn : NGPWMn dead time insertion logic
bits : 2 - 4 (3 bit)
access : read-write

SLFCNTn : Dead time width automatic control enable
bits : 3 - 6 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read


GPWM3DTMSETA

GPWM3 Dead Time Setti3g Register A
address_offset : 0x324 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3DTMSETA GPWM3DTMSETA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTSTAn __reserve0

DTSTAn : Set dead time for GPWMn.
bits : 0 - 9 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM3DTMSETB

GPWM3 Dead Time Setti3g Register B
address_offset : 0x326 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3DTMSETB GPWM3DTMSETB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTSTBn __reserve0

DTSTBn : Set dead time for NGPWMn.
bits : 0 - 9 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM3ADST

GPWM3 Sy3chro3ous Trigger Setti3g Register
address_offset : 0x328 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3ADST GPWM3ADST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PASTn

PASTn : Set the value of starting GPWMn synchronous A/D.
bits : 0 - 15 (16 bit)
access : read-write


GPWM3ADSTSEL

GPWM3 Sy3chro3ous Trigger Polarity Selectio3 Register
address_offset : 0x32A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3ADSTSEL GPWM3ADSTSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PASTUPn PASTDNn __reserve0

PASTUPn : Set the timing of synchronous trigger generation.
bits : 0 - 0 (1 bit)
access : read-write

PASTDNn : Set the timing of synchronous trigger generation.
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM3ADBC

GPWM3 Sy3chro3ous Bi3ary Cou3ter Read Register
address_offset : 0x32C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3ADBC GPWM3ADBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADBCn

ADBCn : Read the binary count for starting GPWMn synchronous A/D.
bits : 0 - 15 (16 bit)
access : read


GPWM3IRQCNT

GPWM3 UDF/OVF I3terrupt Output Co3trol Register
address_offset : 0x330 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3IRQCNT GPWM3IRQCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDFCNTn UDFSCNTn OVFCNTn OVFSCNTn

UDFCNTn : Number of times setting for GPWMn underflow interrupt (Second time or later)
bits : 0 - 3 (4 bit)
access : read-write

UDFSCNTn : Number of times setting for GPWMn underflow interrupt (First time)
bits : 4 - 11 (8 bit)
access : read-write

OVFCNTn : Number of times setting for GPWMn overflow interrupt (Second time or later)
bits : 8 - 19 (12 bit)
access : read-write

OVFSCNTn : Number of times setting for GPWMn overflow interrupt (First time)
bits : 12 - 27 (16 bit)
access : read-write


GPWM3ADIRQCNT

GPWM3 A/D Start I3terrupt Output Co3trol Register
address_offset : 0x334 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3ADIRQCNT GPWM3ADIRQCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASTCNTn ASTSCNTn __reserve0

ASTCNTn : Number of times setting for GPWMn synchronous A/D start interrupt (Second time or later)
bits : 0 - 3 (4 bit)
access : read-write

ASTSCNTn : Number of times setting for GPWMn synchronous A/D start interrupt (First time)
bits : 4 - 11 (8 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read


GPWM3OFF

GPWM3 Pi3 Protectio3 Co3trol Register
address_offset : 0x338 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3OFF GPWM3OFF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTENn __reserve0 PRT PRTN __reserve1

OUTENn : GPWMn pin output enable
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 4 (4 bit)
access : read

PRT : GPWMOUTn output pin protection function
bits : 4 - 9 (6 bit)
access : read-write

PRTN : NGPWMOUTn output pin protection function
bits : 6 - 13 (8 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read


GPWM3OFFIRQA

GPWM3 Pi3 Protectio3 Factor Selectio3 Register A
address_offset : 0x33C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3OFFIRQA GPWM3OFFIRQA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ08ENn IRQ09ENn IRQ14ENn IRQ15ENn IRQ18ENn IRQ19ENn NMIENn AD0ERRAENn AD0ERRBENn AD1ERRAENn AD1ERRBENn AD2ERRAENn AD2ERRBENn __reserve0

IRQ00ENn : Protection factor control by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Protection factor control by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ08ENn : Protection factor control by External Interrupt 8
bits : 2 - 4 (3 bit)
access : read-write

IRQ09ENn : Protection factor control by External Interrupt 9
bits : 3 - 6 (4 bit)
access : read-write

IRQ14ENn : Protection factor control by External Interrupt 14
bits : 4 - 8 (5 bit)
access : read-write

IRQ15ENn : Protection factor control by External Interrupt 15
bits : 5 - 10 (6 bit)
access : read-write

IRQ18ENn : Protection factor control by External Interrupt 18
bits : 6 - 12 (7 bit)
access : read-write

IRQ19ENn : Protection factor control by External Interrupt 19
bits : 7 - 14 (8 bit)
access : read-write

NMIENn : Protection factor control by NMI
bits : 8 - 16 (9 bit)
access : read-write

AD0ERRAENn : Protection factor control by A/D0 Conversion Error Detection
bits : 9 - 18 (10 bit)
access : read-write

AD0ERRBENn : Protection factor control by A/D0 Conversion Error Detection B
bits : 10 - 20 (11 bit)
access : read-write

AD1ERRAENn : Protection factor control by A/D1 Conversion Error Detection
bits : 11 - 22 (12 bit)
access : read-write

AD1ERRBENn : Protection factor control by A/D1 Conversion Error Detection B
bits : 12 - 24 (13 bit)
access : read-write

AD2ERRAENn : Protection factor control by A/D2 Conversion Error Detection
bits : 13 - 26 (14 bit)
access : read-write

AD2ERRBENn : Protection factor control by A/D2 Conversion Error Detection B
bits : 14 - 28 (15 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 15 - 30 (16 bit)
access : read


GPWM3OFFIRQB

GPWM3 Pi3 Protectio3 Factor Selectio3 Register B
address_offset : 0x33E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3OFFIRQB GPWM3OFFIRQB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Protection factor control by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Protection factor control by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Protection factor control by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Protection factor control by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Protection factor control by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Protection factor control by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Protection factor control by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Protection factor control by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Protection factor control by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Protection factor control by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM0ADIRQCNT

GPWM0 A/D Start I0terrupt Output Co0trol Register
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0ADIRQCNT GPWM0ADIRQCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASTCNTn ASTSCNTn __reserve0

ASTCNTn : Number of times setting for GPWMn synchronous A/D start interrupt (Second time or later)
bits : 0 - 3 (4 bit)
access : read-write

ASTSCNTn : Number of times setting for GPWMn synchronous A/D start interrupt (First time)
bits : 4 - 11 (8 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read


GPWM3PULSECNT

GPWM3 Pulse Co3trol Register
address_offset : 0x340 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3PULSECNT GPWM3PULSECNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTCTENn DTACTSELn DTCTASELn DTCTBSELn DTOVFRETn DTUDFRETn PRCTENn PRACTSELn PRRETSELn __reserve0

DTCTENn : Duty Cut enable
bits : 0 - 0 (1 bit)
access : read-write

DTACTSELn : Duty cut start factor polarity selection
bits : 1 - 2 (2 bit)
access : read-write

DTCTASELn : GPWMn operation selection when the duty cut
bits : 2 - 5 (4 bit)
access : read-write

DTCTBSELn : NGPWMn operation selection when the duty cut
bits : 4 - 9 (6 bit)
access : read-write

DTOVFRETn : Control of the return of duty cut by the overflow
bits : 6 - 12 (7 bit)
access : read-write

DTUDFRETn : Control of the return of duty cut by the underflow
bits : 7 - 14 (8 bit)
access : read-write

PRCTENn : Period Cut enable
bits : 8 - 16 (9 bit)
access : read-write

PRACTSELn : Period cut start factor polarity selection
bits : 9 - 18 (10 bit)
access : read-write

PRRETSELn : Period cut operation selection
bits : 10 - 20 (11 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 11 - 26 (16 bit)
access : read


GPWM3PULSEST

GPWM3 Pulse Co3trol Status Register
address_offset : 0x344 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3PULSEST GPWM3PULSEST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTCTSTn PRCTSTn __reserve0

DTCTSTn : Duty cut state
bits : 0 - 0 (1 bit)
access : read-write

PRCTSTn : Period cut state
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM3DUTYTRGA

GPWM3 Duty Cut Factor Selectio3 Register A
address_offset : 0x348 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3DUTYTRGA GPWM3DUTYTRGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ02ENn IRQ03ENn IRQ04ENn IRQ05ENn IRQ06ENn IRQ07ENn IRQ08ENn IRQ09ENn IRQ10ENn IRQ11ENn IRQ12ENn IRQ13ENn IRQ14ENn IRQ15ENn

IRQ00ENn : Duty cut start factor selection by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Duty cut start factor selection by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ02ENn : Duty cut start factor selection by External Interrupt 2
bits : 2 - 4 (3 bit)
access : read-write

IRQ03ENn : Duty cut start factor selection by External Interrupt 3
bits : 3 - 6 (4 bit)
access : read-write

IRQ04ENn : Duty cut start factor selection by External Interrupt 4
bits : 4 - 8 (5 bit)
access : read-write

IRQ05ENn : Duty cut start factor selection by External Interrupt 5
bits : 5 - 10 (6 bit)
access : read-write

IRQ06ENn : Duty cut start factor selection by External Interrupt 6
bits : 6 - 12 (7 bit)
access : read-write

IRQ07ENn : Duty cut start factor selection by External Interrupt 7
bits : 7 - 14 (8 bit)
access : read-write

IRQ08ENn : Duty cut start factor selection by External Interrupt 8
bits : 8 - 16 (9 bit)
access : read-write

IRQ09ENn : Duty cut start factor selection by External Interrupt 9
bits : 9 - 18 (10 bit)
access : read-write

IRQ10ENn : Duty cut start factor selection by External Interrupt 10
bits : 10 - 20 (11 bit)
access : read-write

IRQ11ENn : Duty cut start factor selection by External Interrupt 11
bits : 11 - 22 (12 bit)
access : read-write

IRQ12ENn : Duty cut start factor selection by External Interrupt 12
bits : 12 - 24 (13 bit)
access : read-write

IRQ13ENn : Duty cut start factor selection by External Interrupt 13
bits : 13 - 26 (14 bit)
access : read-write

IRQ14ENn : Duty cut start factor selection by External Interrupt 14
bits : 14 - 28 (15 bit)
access : read-write

IRQ15ENn : Duty cut start factor selection by External Interrupt 15
bits : 15 - 30 (16 bit)
access : read-write


GPWM3DUTYTRGB

GPWM3 Duty Cut Factor Selectio3 Register B
address_offset : 0x34A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3DUTYTRGB GPWM3DUTYTRGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Duty cut start factor selection by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Duty cut start factor selection by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Duty cut start factor selection by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Duty cut start factor selection by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Duty cut start factor selection by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Duty cut start factor selection by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Duty cut start factor selection by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Duty cut start factor selection by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Duty cut start factor selection by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Duty cut start factor selection by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM3PERITRGA

GPWM3 Period Cut Factor Selectio3 Register A
address_offset : 0x34C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3PERITRGA GPWM3PERITRGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ02ENn IRQ03ENn IRQ04ENn IRQ05ENn IRQ06ENn IRQ07ENn IRQ08ENn IRQ09ENn IRQ10ENn IRQ11ENn IRQ12ENn IRQ13ENn IRQ14ENn IRQ15ENn

IRQ00ENn : Period cut start factor selection by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Period cut start factor selection by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ02ENn : Period cut start factor selection by External Interrupt 2
bits : 2 - 4 (3 bit)
access : read-write

IRQ03ENn : Period cut start factor selection by External Interrupt 3
bits : 3 - 6 (4 bit)
access : read-write

IRQ04ENn : Period cut start factor selection by External Interrupt 4
bits : 4 - 8 (5 bit)
access : read-write

IRQ05ENn : Period cut start factor selection by External Interrupt 5
bits : 5 - 10 (6 bit)
access : read-write

IRQ06ENn : Period cut start factor selection by External Interrupt 6
bits : 6 - 12 (7 bit)
access : read-write

IRQ07ENn : Period cut start factor selection by External Interrupt 7
bits : 7 - 14 (8 bit)
access : read-write

IRQ08ENn : Period cut start factor selection by External Interrupt 8
bits : 8 - 16 (9 bit)
access : read-write

IRQ09ENn : Period cut start factor selection by External Interrupt 9
bits : 9 - 18 (10 bit)
access : read-write

IRQ10ENn : Period cut start factor selection by External Interrupt 10
bits : 10 - 20 (11 bit)
access : read-write

IRQ11ENn : Period cut start factor selection by External Interrupt 11
bits : 11 - 22 (12 bit)
access : read-write

IRQ12ENn : Period cut start factor selection by External Interrupt 12
bits : 12 - 24 (13 bit)
access : read-write

IRQ13ENn : Period cut start factor selection by External Interrupt 13
bits : 13 - 26 (14 bit)
access : read-write

IRQ14ENn : Period cut start factor selection by External Interrupt 14
bits : 14 - 28 (15 bit)
access : read-write

IRQ15ENn : Period cut start factor selection by External Interrupt 15
bits : 15 - 30 (16 bit)
access : read-write


GPWM3PERITRGB

GPWM3 Period Cut Factor Selectio3 Register B
address_offset : 0x34E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3PERITRGB GPWM3PERITRGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Period cut start factor selection by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Period cut start factor selection by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Period cut start factor selection by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Period cut start factor selection by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Period cut start factor selection by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Period cut start factor selection by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Period cut start factor selection by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Period cut start factor selection by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Period cut start factor selection by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Period cut start factor selection by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM3DBUPDATE

GPWM3 Double Buffer Updati3g E3able Register
address_offset : 0x350 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM3DBUPDATE GPWM3DBUPDATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUPn __reserve0

DUPn : Double buffer updating enable
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read


GPWM0OFF

GPWM0 Pi0 Protectio0 Co0trol Register
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0OFF GPWM0OFF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTENn __reserve0 PRT PRTN __reserve1

OUTENn : GPWMn pin output enable
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 4 (4 bit)
access : read

PRT : GPWMOUTn output pin protection function
bits : 4 - 9 (6 bit)
access : read-write

PRTN : NGPWMOUTn output pin protection function
bits : 6 - 13 (8 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read


GPWM0OFFIRQA

GPWM0 Pi0 Protectio0 Factor Selectio0 Register A
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0OFFIRQA GPWM0OFFIRQA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ08ENn IRQ09ENn IRQ14ENn IRQ15ENn IRQ18ENn IRQ19ENn NMIENn AD0ERRAENn AD0ERRBENn AD1ERRAENn AD1ERRBENn AD2ERRAENn AD2ERRBENn __reserve0

IRQ00ENn : Protection factor control by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Protection factor control by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ08ENn : Protection factor control by External Interrupt 8
bits : 2 - 4 (3 bit)
access : read-write

IRQ09ENn : Protection factor control by External Interrupt 9
bits : 3 - 6 (4 bit)
access : read-write

IRQ14ENn : Protection factor control by External Interrupt 14
bits : 4 - 8 (5 bit)
access : read-write

IRQ15ENn : Protection factor control by External Interrupt 15
bits : 5 - 10 (6 bit)
access : read-write

IRQ18ENn : Protection factor control by External Interrupt 18
bits : 6 - 12 (7 bit)
access : read-write

IRQ19ENn : Protection factor control by External Interrupt 19
bits : 7 - 14 (8 bit)
access : read-write

NMIENn : Protection factor control by NMI
bits : 8 - 16 (9 bit)
access : read-write

AD0ERRAENn : Protection factor control by A/D0 Conversion Error Detection
bits : 9 - 18 (10 bit)
access : read-write

AD0ERRBENn : Protection factor control by A/D0 Conversion Error Detection B
bits : 10 - 20 (11 bit)
access : read-write

AD1ERRAENn : Protection factor control by A/D1 Conversion Error Detection
bits : 11 - 22 (12 bit)
access : read-write

AD1ERRBENn : Protection factor control by A/D1 Conversion Error Detection B
bits : 12 - 24 (13 bit)
access : read-write

AD2ERRAENn : Protection factor control by A/D2 Conversion Error Detection
bits : 13 - 26 (14 bit)
access : read-write

AD2ERRBENn : Protection factor control by A/D2 Conversion Error Detection B
bits : 14 - 28 (15 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 15 - 30 (16 bit)
access : read


GPWM0OFFIRQB

GPWM0 Pi0 Protectio0 Factor Selectio0 Register B
address_offset : 0x3E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0OFFIRQB GPWM0OFFIRQB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Protection factor control by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Protection factor control by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Protection factor control by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Protection factor control by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Protection factor control by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Protection factor control by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Protection factor control by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Protection factor control by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Protection factor control by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Protection factor control by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM0OUTMD

GPWM0 Output Polarity Co0trol Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0OUTMD GPWM0OUTMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PXDTn PXDTNn __reserve0

PXDTn : GPWMn output polarity
bits : 0 - 0 (1 bit)
access : read-write

PXDTNn : NGPWMn output polarity
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM0PULSECNT

GPWM0 Pulse Co0trol Register
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0PULSECNT GPWM0PULSECNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTCTENn DTACTSELn DTCTASELn DTCTBSELn DTOVFRETn DTUDFRETn PRCTENn PRACTSELn PRRETSELn __reserve0

DTCTENn : Duty Cut enable
bits : 0 - 0 (1 bit)
access : read-write

DTACTSELn : Duty cut start factor polarity selection
bits : 1 - 2 (2 bit)
access : read-write

DTCTASELn : GPWMn operation selection when the duty cut
bits : 2 - 5 (4 bit)
access : read-write

DTCTBSELn : NGPWMn operation selection when the duty cut
bits : 4 - 9 (6 bit)
access : read-write

DTOVFRETn : Control of the return of duty cut by the overflow
bits : 6 - 12 (7 bit)
access : read-write

DTUDFRETn : Control of the return of duty cut by the underflow
bits : 7 - 14 (8 bit)
access : read-write

PRCTENn : Period Cut enable
bits : 8 - 16 (9 bit)
access : read-write

PRACTSELn : Period cut start factor polarity selection
bits : 9 - 18 (10 bit)
access : read-write

PRRETSELn : Period cut operation selection
bits : 10 - 20 (11 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 11 - 26 (16 bit)
access : read


GPWM4MD

GPWM4 Mode Register
address_offset : 0x400 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4MD GPWM4MD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAVEMDn TCENn HRSELn HRPRENn SYNCENn DUPENn PCRBENn PCRAENn SDSELBn SDSELAn __reserve0 CLKSELn __reserve1 SFTENn SDIRn __reserve2

WAVEMDn : PWM waveform mode select
bits : 0 - 0 (1 bit)
access : read-write

TCENn : PWM Operation control
bits : 1 - 2 (2 bit)
access : read-write

HRSELn : High resolution output function enable
bits : 2 - 4 (3 bit)
access : read-write

HRPRENn : High resolution cycle function enable
bits : 3 - 6 (4 bit)
access : read-write

SYNCENn : Synchronous start function (MFA) enable
bits : 4 - 8 (5 bit)
access : read-write

DUPENn : Double buffer updating enable register selection
bits : 5 - 10 (6 bit)
access : read-write

PCRBENn : Double buffer load timing enable (GPWMnBC overflow)
bits : 6 - 12 (7 bit)
access : read-write

PCRAENn : Double buffer load timing enable (GPWMnBC underflow)
bits : 7 - 14 (8 bit)
access : read-write

SDSELBn : GPWMnSEL buffer mode
bits : 8 - 16 (9 bit)
access : read-write

SDSELAn : GPWMnOUTMD buffer mode
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 20 (11 bit)
access : read

CLKSELn : Count clock selection
bits : 11 - 22 (12 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 12 - 24 (13 bit)
access : read

SFTENn : PWM output shift function enable
bits : 13 - 26 (14 bit)
access : read-write

SDIRn : Shift direction control
bits : 14 - 28 (15 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 15 - 30 (16 bit)
access : read


GPWM4OUTMD

GPWM4 Output Polarity Co4trol Register
address_offset : 0x404 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4OUTMD GPWM4OUTMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PXDTn PXDTNn __reserve0

PXDTn : GPWMn output polarity
bits : 0 - 0 (1 bit)
access : read-write

PXDTNn : NGPWMn output polarity
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM4SEL

GPWM4 Output Co4trol Register
address_offset : 0x408 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4SEL GPWM4SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTLVn OTLVNn PSELn PSELNn __reserve0

OTLVn : GPWMn High/Low-level output
bits : 0 - 0 (1 bit)
access : read-write

OTLVNn : NGPWMn High/Low-level output
bits : 1 - 2 (2 bit)
access : read-write

PSELn : GPWMn output sources
bits : 2 - 4 (3 bit)
access : read-write

PSELNn : NGPWMn output sources
bits : 3 - 6 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read


GPWM4BC

GPWM4BC Value Read Register
address_offset : 0x40C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4BC GPWM4BC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCn

BCn : Read the binary counter value of GPWMn
bits : 0 - 15 (16 bit)
access : read


GPWM4BCSTR

GPWM4BC Status Read Register
address_offset : 0x40E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4BCSTR GPWM4BCSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRn __reserve0

STRn : GPWMn binary counter's counting status read
bits : 0 - 0 (1 bit)
access : read

__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read


GPWM4HRSET

GPWM4 High Resolutio4 Cycle Setti4g Register
address_offset : 0x410 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4HRSET GPWM4HRSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRSETn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRSETn : Set high resolution cycle
bits : 11 - 26 (16 bit)
access : read-write


GPWM4SET

GPWM4 Cycle Setti4g Register
address_offset : 0x412 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4SET GPWM4SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETn

SETn : Set the cycle to the GPWMn 16-bit counter.
bits : 0 - 15 (16 bit)
access : read-write


GPWM4TCMPHR

GPWM4 High Resolutio4 Phase Compariso4 Setti4g Register
address_offset : 0x414 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4TCMPHR GPWM4TCMPHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRTCPn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRTCPn : Set phase comparison high resolution
bits : 11 - 26 (16 bit)
access : read-write


GPWM4TCMP

GPWM4 Phase Compariso4 Setti4g Register
address_offset : 0x416 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4TCMP GPWM4TCMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCPn

TCPn : Set the timing to change output of GPWMn.
bits : 0 - 15 (16 bit)
access : read-write


GPWM4DHRDAT

GPWM4 High Resolutio4 Output Shift Amou4t Setti4g Register
address_offset : 0x418 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4DHRDAT GPWM4DHRDAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRSTIMn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRSTIMn : Set high resolution output shift amount
bits : 11 - 26 (16 bit)
access : read-write


GPWM4DDAT

GPWM4 Output Shift Amou4t Setti4g Register
address_offset : 0x41A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4DDAT GPWM4DDAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STIMn

STIMn : Set GPWMn output shift amount
bits : 0 - 15 (16 bit)
access : read-write


GPWM4DTMCNT

GPWM4 Dead Time Co4trol Register
address_offset : 0x420 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4DTMCNT GPWM4DTMCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTENn ORMDn NORMDn SLFCNTn __reserve0

DTENn : Dead time insertion
bits : 0 - 0 (1 bit)
access : read-write

ORMDn : GPWMn dead time insertion logic
bits : 1 - 2 (2 bit)
access : read-write

NORMDn : NGPWMn dead time insertion logic
bits : 2 - 4 (3 bit)
access : read-write

SLFCNTn : Dead time width automatic control enable
bits : 3 - 6 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read


GPWM4DTMSETA

GPWM4 Dead Time Setti4g Register A
address_offset : 0x424 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4DTMSETA GPWM4DTMSETA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTSTAn __reserve0

DTSTAn : Set dead time for GPWMn.
bits : 0 - 9 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM4DTMSETB

GPWM4 Dead Time Setti4g Register B
address_offset : 0x426 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4DTMSETB GPWM4DTMSETB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTSTBn __reserve0

DTSTBn : Set dead time for NGPWMn.
bits : 0 - 9 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM4ADST

GPWM4 Sy4chro4ous Trigger Setti4g Register
address_offset : 0x428 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4ADST GPWM4ADST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PASTn

PASTn : Set the value of starting GPWMn synchronous A/D.
bits : 0 - 15 (16 bit)
access : read-write


GPWM4ADSTSEL

GPWM4 Sy4chro4ous Trigger Polarity Selectio4 Register
address_offset : 0x42A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4ADSTSEL GPWM4ADSTSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PASTUPn PASTDNn __reserve0

PASTUPn : Set the timing of synchronous trigger generation.
bits : 0 - 0 (1 bit)
access : read-write

PASTDNn : Set the timing of synchronous trigger generation.
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM4ADBC

GPWM4 Sy4chro4ous Bi4ary Cou4ter Read Register
address_offset : 0x42C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4ADBC GPWM4ADBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADBCn

ADBCn : Read the binary count for starting GPWMn synchronous A/D.
bits : 0 - 15 (16 bit)
access : read


GPWM4IRQCNT

GPWM4 UDF/OVF I4terrupt Output Co4trol Register
address_offset : 0x430 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4IRQCNT GPWM4IRQCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDFCNTn UDFSCNTn OVFCNTn OVFSCNTn

UDFCNTn : Number of times setting for GPWMn underflow interrupt (Second time or later)
bits : 0 - 3 (4 bit)
access : read-write

UDFSCNTn : Number of times setting for GPWMn underflow interrupt (First time)
bits : 4 - 11 (8 bit)
access : read-write

OVFCNTn : Number of times setting for GPWMn overflow interrupt (Second time or later)
bits : 8 - 19 (12 bit)
access : read-write

OVFSCNTn : Number of times setting for GPWMn overflow interrupt (First time)
bits : 12 - 27 (16 bit)
access : read-write


GPWM4ADIRQCNT

GPWM4 A/D Start I4terrupt Output Co4trol Register
address_offset : 0x434 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4ADIRQCNT GPWM4ADIRQCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASTCNTn ASTSCNTn __reserve0

ASTCNTn : Number of times setting for GPWMn synchronous A/D start interrupt (Second time or later)
bits : 0 - 3 (4 bit)
access : read-write

ASTSCNTn : Number of times setting for GPWMn synchronous A/D start interrupt (First time)
bits : 4 - 11 (8 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read


GPWM4OFF

GPWM4 Pi4 Protectio4 Co4trol Register
address_offset : 0x438 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4OFF GPWM4OFF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTENn __reserve0 PRT PRTN __reserve1

OUTENn : GPWMn pin output enable
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 4 (4 bit)
access : read

PRT : GPWMOUTn output pin protection function
bits : 4 - 9 (6 bit)
access : read-write

PRTN : NGPWMOUTn output pin protection function
bits : 6 - 13 (8 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read


GPWM4OFFIRQA

GPWM4 Pi4 Protectio4 Factor Selectio4 Register A
address_offset : 0x43C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4OFFIRQA GPWM4OFFIRQA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ08ENn IRQ09ENn IRQ14ENn IRQ15ENn IRQ18ENn IRQ19ENn NMIENn AD0ERRAENn AD0ERRBENn AD1ERRAENn AD1ERRBENn AD2ERRAENn AD2ERRBENn __reserve0

IRQ00ENn : Protection factor control by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Protection factor control by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ08ENn : Protection factor control by External Interrupt 8
bits : 2 - 4 (3 bit)
access : read-write

IRQ09ENn : Protection factor control by External Interrupt 9
bits : 3 - 6 (4 bit)
access : read-write

IRQ14ENn : Protection factor control by External Interrupt 14
bits : 4 - 8 (5 bit)
access : read-write

IRQ15ENn : Protection factor control by External Interrupt 15
bits : 5 - 10 (6 bit)
access : read-write

IRQ18ENn : Protection factor control by External Interrupt 18
bits : 6 - 12 (7 bit)
access : read-write

IRQ19ENn : Protection factor control by External Interrupt 19
bits : 7 - 14 (8 bit)
access : read-write

NMIENn : Protection factor control by NMI
bits : 8 - 16 (9 bit)
access : read-write

AD0ERRAENn : Protection factor control by A/D0 Conversion Error Detection
bits : 9 - 18 (10 bit)
access : read-write

AD0ERRBENn : Protection factor control by A/D0 Conversion Error Detection B
bits : 10 - 20 (11 bit)
access : read-write

AD1ERRAENn : Protection factor control by A/D1 Conversion Error Detection
bits : 11 - 22 (12 bit)
access : read-write

AD1ERRBENn : Protection factor control by A/D1 Conversion Error Detection B
bits : 12 - 24 (13 bit)
access : read-write

AD2ERRAENn : Protection factor control by A/D2 Conversion Error Detection
bits : 13 - 26 (14 bit)
access : read-write

AD2ERRBENn : Protection factor control by A/D2 Conversion Error Detection B
bits : 14 - 28 (15 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 15 - 30 (16 bit)
access : read


GPWM4OFFIRQB

GPWM4 Pi4 Protectio4 Factor Selectio4 Register B
address_offset : 0x43E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4OFFIRQB GPWM4OFFIRQB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Protection factor control by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Protection factor control by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Protection factor control by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Protection factor control by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Protection factor control by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Protection factor control by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Protection factor control by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Protection factor control by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Protection factor control by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Protection factor control by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM0PULSEST

GPWM0 Pulse Co0trol Status Register
address_offset : 0x44 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0PULSEST GPWM0PULSEST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTCTSTn PRCTSTn __reserve0

DTCTSTn : Duty cut state
bits : 0 - 0 (1 bit)
access : read-write

PRCTSTn : Period cut state
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM4PULSECNT

GPWM4 Pulse Co4trol Register
address_offset : 0x440 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4PULSECNT GPWM4PULSECNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTCTENn DTACTSELn DTCTASELn DTCTBSELn DTOVFRETn DTUDFRETn PRCTENn PRACTSELn PRRETSELn __reserve0

DTCTENn : Duty Cut enable
bits : 0 - 0 (1 bit)
access : read-write

DTACTSELn : Duty cut start factor polarity selection
bits : 1 - 2 (2 bit)
access : read-write

DTCTASELn : GPWMn operation selection when the duty cut
bits : 2 - 5 (4 bit)
access : read-write

DTCTBSELn : NGPWMn operation selection when the duty cut
bits : 4 - 9 (6 bit)
access : read-write

DTOVFRETn : Control of the return of duty cut by the overflow
bits : 6 - 12 (7 bit)
access : read-write

DTUDFRETn : Control of the return of duty cut by the underflow
bits : 7 - 14 (8 bit)
access : read-write

PRCTENn : Period Cut enable
bits : 8 - 16 (9 bit)
access : read-write

PRACTSELn : Period cut start factor polarity selection
bits : 9 - 18 (10 bit)
access : read-write

PRRETSELn : Period cut operation selection
bits : 10 - 20 (11 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 11 - 26 (16 bit)
access : read


GPWM4PULSEST

GPWM4 Pulse Co4trol Status Register
address_offset : 0x444 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4PULSEST GPWM4PULSEST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTCTSTn PRCTSTn __reserve0

DTCTSTn : Duty cut state
bits : 0 - 0 (1 bit)
access : read-write

PRCTSTn : Period cut state
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM4DUTYTRGA

GPWM4 Duty Cut Factor Selectio4 Register A
address_offset : 0x448 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4DUTYTRGA GPWM4DUTYTRGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ02ENn IRQ03ENn IRQ04ENn IRQ05ENn IRQ06ENn IRQ07ENn IRQ08ENn IRQ09ENn IRQ10ENn IRQ11ENn IRQ12ENn IRQ13ENn IRQ14ENn IRQ15ENn

IRQ00ENn : Duty cut start factor selection by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Duty cut start factor selection by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ02ENn : Duty cut start factor selection by External Interrupt 2
bits : 2 - 4 (3 bit)
access : read-write

IRQ03ENn : Duty cut start factor selection by External Interrupt 3
bits : 3 - 6 (4 bit)
access : read-write

IRQ04ENn : Duty cut start factor selection by External Interrupt 4
bits : 4 - 8 (5 bit)
access : read-write

IRQ05ENn : Duty cut start factor selection by External Interrupt 5
bits : 5 - 10 (6 bit)
access : read-write

IRQ06ENn : Duty cut start factor selection by External Interrupt 6
bits : 6 - 12 (7 bit)
access : read-write

IRQ07ENn : Duty cut start factor selection by External Interrupt 7
bits : 7 - 14 (8 bit)
access : read-write

IRQ08ENn : Duty cut start factor selection by External Interrupt 8
bits : 8 - 16 (9 bit)
access : read-write

IRQ09ENn : Duty cut start factor selection by External Interrupt 9
bits : 9 - 18 (10 bit)
access : read-write

IRQ10ENn : Duty cut start factor selection by External Interrupt 10
bits : 10 - 20 (11 bit)
access : read-write

IRQ11ENn : Duty cut start factor selection by External Interrupt 11
bits : 11 - 22 (12 bit)
access : read-write

IRQ12ENn : Duty cut start factor selection by External Interrupt 12
bits : 12 - 24 (13 bit)
access : read-write

IRQ13ENn : Duty cut start factor selection by External Interrupt 13
bits : 13 - 26 (14 bit)
access : read-write

IRQ14ENn : Duty cut start factor selection by External Interrupt 14
bits : 14 - 28 (15 bit)
access : read-write

IRQ15ENn : Duty cut start factor selection by External Interrupt 15
bits : 15 - 30 (16 bit)
access : read-write


GPWM4DUTYTRGB

GPWM4 Duty Cut Factor Selectio4 Register B
address_offset : 0x44A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4DUTYTRGB GPWM4DUTYTRGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Duty cut start factor selection by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Duty cut start factor selection by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Duty cut start factor selection by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Duty cut start factor selection by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Duty cut start factor selection by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Duty cut start factor selection by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Duty cut start factor selection by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Duty cut start factor selection by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Duty cut start factor selection by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Duty cut start factor selection by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM4PERITRGA

GPWM4 Period Cut Factor Selectio4 Register A
address_offset : 0x44C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4PERITRGA GPWM4PERITRGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ02ENn IRQ03ENn IRQ04ENn IRQ05ENn IRQ06ENn IRQ07ENn IRQ08ENn IRQ09ENn IRQ10ENn IRQ11ENn IRQ12ENn IRQ13ENn IRQ14ENn IRQ15ENn

IRQ00ENn : Period cut start factor selection by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Period cut start factor selection by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ02ENn : Period cut start factor selection by External Interrupt 2
bits : 2 - 4 (3 bit)
access : read-write

IRQ03ENn : Period cut start factor selection by External Interrupt 3
bits : 3 - 6 (4 bit)
access : read-write

IRQ04ENn : Period cut start factor selection by External Interrupt 4
bits : 4 - 8 (5 bit)
access : read-write

IRQ05ENn : Period cut start factor selection by External Interrupt 5
bits : 5 - 10 (6 bit)
access : read-write

IRQ06ENn : Period cut start factor selection by External Interrupt 6
bits : 6 - 12 (7 bit)
access : read-write

IRQ07ENn : Period cut start factor selection by External Interrupt 7
bits : 7 - 14 (8 bit)
access : read-write

IRQ08ENn : Period cut start factor selection by External Interrupt 8
bits : 8 - 16 (9 bit)
access : read-write

IRQ09ENn : Period cut start factor selection by External Interrupt 9
bits : 9 - 18 (10 bit)
access : read-write

IRQ10ENn : Period cut start factor selection by External Interrupt 10
bits : 10 - 20 (11 bit)
access : read-write

IRQ11ENn : Period cut start factor selection by External Interrupt 11
bits : 11 - 22 (12 bit)
access : read-write

IRQ12ENn : Period cut start factor selection by External Interrupt 12
bits : 12 - 24 (13 bit)
access : read-write

IRQ13ENn : Period cut start factor selection by External Interrupt 13
bits : 13 - 26 (14 bit)
access : read-write

IRQ14ENn : Period cut start factor selection by External Interrupt 14
bits : 14 - 28 (15 bit)
access : read-write

IRQ15ENn : Period cut start factor selection by External Interrupt 15
bits : 15 - 30 (16 bit)
access : read-write


GPWM4PERITRGB

GPWM4 Period Cut Factor Selectio4 Register B
address_offset : 0x44E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4PERITRGB GPWM4PERITRGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Period cut start factor selection by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Period cut start factor selection by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Period cut start factor selection by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Period cut start factor selection by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Period cut start factor selection by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Period cut start factor selection by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Period cut start factor selection by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Period cut start factor selection by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Period cut start factor selection by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Period cut start factor selection by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM4DBUPDATE

GPWM4 Double Buffer Updati4g E4able Register
address_offset : 0x450 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM4DBUPDATE GPWM4DBUPDATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUPn __reserve0

DUPn : Double buffer updating enable
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read


GPWM0DUTYTRGA

GPWM0 Duty Cut Factor Selectio0 Register A
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0DUTYTRGA GPWM0DUTYTRGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ02ENn IRQ03ENn IRQ04ENn IRQ05ENn IRQ06ENn IRQ07ENn IRQ08ENn IRQ09ENn IRQ10ENn IRQ11ENn IRQ12ENn IRQ13ENn IRQ14ENn IRQ15ENn

IRQ00ENn : Duty cut start factor selection by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Duty cut start factor selection by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ02ENn : Duty cut start factor selection by External Interrupt 2
bits : 2 - 4 (3 bit)
access : read-write

IRQ03ENn : Duty cut start factor selection by External Interrupt 3
bits : 3 - 6 (4 bit)
access : read-write

IRQ04ENn : Duty cut start factor selection by External Interrupt 4
bits : 4 - 8 (5 bit)
access : read-write

IRQ05ENn : Duty cut start factor selection by External Interrupt 5
bits : 5 - 10 (6 bit)
access : read-write

IRQ06ENn : Duty cut start factor selection by External Interrupt 6
bits : 6 - 12 (7 bit)
access : read-write

IRQ07ENn : Duty cut start factor selection by External Interrupt 7
bits : 7 - 14 (8 bit)
access : read-write

IRQ08ENn : Duty cut start factor selection by External Interrupt 8
bits : 8 - 16 (9 bit)
access : read-write

IRQ09ENn : Duty cut start factor selection by External Interrupt 9
bits : 9 - 18 (10 bit)
access : read-write

IRQ10ENn : Duty cut start factor selection by External Interrupt 10
bits : 10 - 20 (11 bit)
access : read-write

IRQ11ENn : Duty cut start factor selection by External Interrupt 11
bits : 11 - 22 (12 bit)
access : read-write

IRQ12ENn : Duty cut start factor selection by External Interrupt 12
bits : 12 - 24 (13 bit)
access : read-write

IRQ13ENn : Duty cut start factor selection by External Interrupt 13
bits : 13 - 26 (14 bit)
access : read-write

IRQ14ENn : Duty cut start factor selection by External Interrupt 14
bits : 14 - 28 (15 bit)
access : read-write

IRQ15ENn : Duty cut start factor selection by External Interrupt 15
bits : 15 - 30 (16 bit)
access : read-write


GPWM0DUTYTRGB

GPWM0 Duty Cut Factor Selectio0 Register B
address_offset : 0x4A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0DUTYTRGB GPWM0DUTYTRGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Duty cut start factor selection by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Duty cut start factor selection by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Duty cut start factor selection by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Duty cut start factor selection by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Duty cut start factor selection by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Duty cut start factor selection by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Duty cut start factor selection by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Duty cut start factor selection by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Duty cut start factor selection by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Duty cut start factor selection by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM0PERITRGA

GPWM0 Period Cut Factor Selectio0 Register A
address_offset : 0x4C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0PERITRGA GPWM0PERITRGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ02ENn IRQ03ENn IRQ04ENn IRQ05ENn IRQ06ENn IRQ07ENn IRQ08ENn IRQ09ENn IRQ10ENn IRQ11ENn IRQ12ENn IRQ13ENn IRQ14ENn IRQ15ENn

IRQ00ENn : Period cut start factor selection by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Period cut start factor selection by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ02ENn : Period cut start factor selection by External Interrupt 2
bits : 2 - 4 (3 bit)
access : read-write

IRQ03ENn : Period cut start factor selection by External Interrupt 3
bits : 3 - 6 (4 bit)
access : read-write

IRQ04ENn : Period cut start factor selection by External Interrupt 4
bits : 4 - 8 (5 bit)
access : read-write

IRQ05ENn : Period cut start factor selection by External Interrupt 5
bits : 5 - 10 (6 bit)
access : read-write

IRQ06ENn : Period cut start factor selection by External Interrupt 6
bits : 6 - 12 (7 bit)
access : read-write

IRQ07ENn : Period cut start factor selection by External Interrupt 7
bits : 7 - 14 (8 bit)
access : read-write

IRQ08ENn : Period cut start factor selection by External Interrupt 8
bits : 8 - 16 (9 bit)
access : read-write

IRQ09ENn : Period cut start factor selection by External Interrupt 9
bits : 9 - 18 (10 bit)
access : read-write

IRQ10ENn : Period cut start factor selection by External Interrupt 10
bits : 10 - 20 (11 bit)
access : read-write

IRQ11ENn : Period cut start factor selection by External Interrupt 11
bits : 11 - 22 (12 bit)
access : read-write

IRQ12ENn : Period cut start factor selection by External Interrupt 12
bits : 12 - 24 (13 bit)
access : read-write

IRQ13ENn : Period cut start factor selection by External Interrupt 13
bits : 13 - 26 (14 bit)
access : read-write

IRQ14ENn : Period cut start factor selection by External Interrupt 14
bits : 14 - 28 (15 bit)
access : read-write

IRQ15ENn : Period cut start factor selection by External Interrupt 15
bits : 15 - 30 (16 bit)
access : read-write


GPWM0PERITRGB

GPWM0 Period Cut Factor Selectio0 Register B
address_offset : 0x4E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0PERITRGB GPWM0PERITRGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Period cut start factor selection by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Period cut start factor selection by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Period cut start factor selection by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Period cut start factor selection by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Period cut start factor selection by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Period cut start factor selection by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Period cut start factor selection by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Period cut start factor selection by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Period cut start factor selection by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Period cut start factor selection by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM0DBUPDATE

GPWM0 Double Buffer Updati0g E0able Register
address_offset : 0x50 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0DBUPDATE GPWM0DBUPDATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUPn __reserve0

DUPn : Double buffer updating enable
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read


GPWM5MD

GPWM5 Mode Register
address_offset : 0x500 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5MD GPWM5MD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAVEMDn TCENn HRSELn HRPRENn SYNCENn DUPENn PCRBENn PCRAENn SDSELBn SDSELAn __reserve0 CLKSELn __reserve1 SFTENn SDIRn __reserve2

WAVEMDn : PWM waveform mode select
bits : 0 - 0 (1 bit)
access : read-write

TCENn : PWM Operation control
bits : 1 - 2 (2 bit)
access : read-write

HRSELn : High resolution output function enable
bits : 2 - 4 (3 bit)
access : read-write

HRPRENn : High resolution cycle function enable
bits : 3 - 6 (4 bit)
access : read-write

SYNCENn : Synchronous start function (MFA) enable
bits : 4 - 8 (5 bit)
access : read-write

DUPENn : Double buffer updating enable register selection
bits : 5 - 10 (6 bit)
access : read-write

PCRBENn : Double buffer load timing enable (GPWMnBC overflow)
bits : 6 - 12 (7 bit)
access : read-write

PCRAENn : Double buffer load timing enable (GPWMnBC underflow)
bits : 7 - 14 (8 bit)
access : read-write

SDSELBn : GPWMnSEL buffer mode
bits : 8 - 16 (9 bit)
access : read-write

SDSELAn : GPWMnOUTMD buffer mode
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 20 (11 bit)
access : read

CLKSELn : Count clock selection
bits : 11 - 22 (12 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 12 - 24 (13 bit)
access : read

SFTENn : PWM output shift function enable
bits : 13 - 26 (14 bit)
access : read-write

SDIRn : Shift direction control
bits : 14 - 28 (15 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 15 - 30 (16 bit)
access : read


GPWM5OUTMD

GPWM5 Output Polarity Co5trol Register
address_offset : 0x504 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5OUTMD GPWM5OUTMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PXDTn PXDTNn __reserve0

PXDTn : GPWMn output polarity
bits : 0 - 0 (1 bit)
access : read-write

PXDTNn : NGPWMn output polarity
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM5SEL

GPWM5 Output Co5trol Register
address_offset : 0x508 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5SEL GPWM5SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTLVn OTLVNn PSELn PSELNn __reserve0

OTLVn : GPWMn High/Low-level output
bits : 0 - 0 (1 bit)
access : read-write

OTLVNn : NGPWMn High/Low-level output
bits : 1 - 2 (2 bit)
access : read-write

PSELn : GPWMn output sources
bits : 2 - 4 (3 bit)
access : read-write

PSELNn : NGPWMn output sources
bits : 3 - 6 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read


GPWM5BC

GPWM5BC Value Read Register
address_offset : 0x50C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5BC GPWM5BC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCn

BCn : Read the binary counter value of GPWMn
bits : 0 - 15 (16 bit)
access : read


GPWM5BCSTR

GPWM5BC Status Read Register
address_offset : 0x50E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5BCSTR GPWM5BCSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRn __reserve0

STRn : GPWMn binary counter's counting status read
bits : 0 - 0 (1 bit)
access : read

__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read


GPWM5HRSET

GPWM5 High Resolutio5 Cycle Setti5g Register
address_offset : 0x510 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5HRSET GPWM5HRSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRSETn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRSETn : Set high resolution cycle
bits : 11 - 26 (16 bit)
access : read-write


GPWM5SET

GPWM5 Cycle Setti5g Register
address_offset : 0x512 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5SET GPWM5SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETn

SETn : Set the cycle to the GPWMn 16-bit counter.
bits : 0 - 15 (16 bit)
access : read-write


GPWM5TCMPHR

GPWM5 High Resolutio5 Phase Compariso5 Setti5g Register
address_offset : 0x514 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5TCMPHR GPWM5TCMPHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRTCPn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRTCPn : Set phase comparison high resolution
bits : 11 - 26 (16 bit)
access : read-write


GPWM5TCMP

GPWM5 Phase Compariso5 Setti5g Register
address_offset : 0x516 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5TCMP GPWM5TCMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCPn

TCPn : Set the timing to change output of GPWMn.
bits : 0 - 15 (16 bit)
access : read-write


GPWM5DHRDAT

GPWM5 High Resolutio5 Output Shift Amou5t Setti5g Register
address_offset : 0x518 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5DHRDAT GPWM5DHRDAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRSTIMn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRSTIMn : Set high resolution output shift amount
bits : 11 - 26 (16 bit)
access : read-write


GPWM5DDAT

GPWM5 Output Shift Amou5t Setti5g Register
address_offset : 0x51A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5DDAT GPWM5DDAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STIMn

STIMn : Set GPWMn output shift amount
bits : 0 - 15 (16 bit)
access : read-write


GPWM5DTMCNT

GPWM5 Dead Time Co5trol Register
address_offset : 0x520 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5DTMCNT GPWM5DTMCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTENn ORMDn NORMDn SLFCNTn __reserve0

DTENn : Dead time insertion
bits : 0 - 0 (1 bit)
access : read-write

ORMDn : GPWMn dead time insertion logic
bits : 1 - 2 (2 bit)
access : read-write

NORMDn : NGPWMn dead time insertion logic
bits : 2 - 4 (3 bit)
access : read-write

SLFCNTn : Dead time width automatic control enable
bits : 3 - 6 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read


GPWM5DTMSETA

GPWM5 Dead Time Setti5g Register A
address_offset : 0x524 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5DTMSETA GPWM5DTMSETA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTSTAn __reserve0

DTSTAn : Set dead time for GPWMn.
bits : 0 - 9 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM5DTMSETB

GPWM5 Dead Time Setti5g Register B
address_offset : 0x526 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5DTMSETB GPWM5DTMSETB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTSTBn __reserve0

DTSTBn : Set dead time for NGPWMn.
bits : 0 - 9 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM5ADST

GPWM5 Sy5chro5ous Trigger Setti5g Register
address_offset : 0x528 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5ADST GPWM5ADST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PASTn

PASTn : Set the value of starting GPWMn synchronous A/D.
bits : 0 - 15 (16 bit)
access : read-write


GPWM5ADSTSEL

GPWM5 Sy5chro5ous Trigger Polarity Selectio5 Register
address_offset : 0x52A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5ADSTSEL GPWM5ADSTSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PASTUPn PASTDNn __reserve0

PASTUPn : Set the timing of synchronous trigger generation.
bits : 0 - 0 (1 bit)
access : read-write

PASTDNn : Set the timing of synchronous trigger generation.
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM5ADBC

GPWM5 Sy5chro5ous Bi5ary Cou5ter Read Register
address_offset : 0x52C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5ADBC GPWM5ADBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADBCn

ADBCn : Read the binary count for starting GPWMn synchronous A/D.
bits : 0 - 15 (16 bit)
access : read


GPWM5IRQCNT

GPWM5 UDF/OVF I5terrupt Output Co5trol Register
address_offset : 0x530 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5IRQCNT GPWM5IRQCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDFCNTn UDFSCNTn OVFCNTn OVFSCNTn

UDFCNTn : Number of times setting for GPWMn underflow interrupt (Second time or later)
bits : 0 - 3 (4 bit)
access : read-write

UDFSCNTn : Number of times setting for GPWMn underflow interrupt (First time)
bits : 4 - 11 (8 bit)
access : read-write

OVFCNTn : Number of times setting for GPWMn overflow interrupt (Second time or later)
bits : 8 - 19 (12 bit)
access : read-write

OVFSCNTn : Number of times setting for GPWMn overflow interrupt (First time)
bits : 12 - 27 (16 bit)
access : read-write


GPWM5ADIRQCNT

GPWM5 A/D Start I5terrupt Output Co5trol Register
address_offset : 0x534 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5ADIRQCNT GPWM5ADIRQCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASTCNTn ASTSCNTn __reserve0

ASTCNTn : Number of times setting for GPWMn synchronous A/D start interrupt (Second time or later)
bits : 0 - 3 (4 bit)
access : read-write

ASTSCNTn : Number of times setting for GPWMn synchronous A/D start interrupt (First time)
bits : 4 - 11 (8 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read


GPWM5OFF

GPWM5 Pi5 Protectio5 Co5trol Register
address_offset : 0x538 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5OFF GPWM5OFF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTENn __reserve0 PRT PRTN __reserve1

OUTENn : GPWMn pin output enable
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 4 (4 bit)
access : read

PRT : GPWMOUTn output pin protection function
bits : 4 - 9 (6 bit)
access : read-write

PRTN : NGPWMOUTn output pin protection function
bits : 6 - 13 (8 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read


GPWM5OFFIRQA

GPWM5 Pi5 Protectio5 Factor Selectio5 Register A
address_offset : 0x53C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5OFFIRQA GPWM5OFFIRQA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ08ENn IRQ09ENn IRQ14ENn IRQ15ENn IRQ18ENn IRQ19ENn NMIENn AD0ERRAENn AD0ERRBENn AD1ERRAENn AD1ERRBENn AD2ERRAENn AD2ERRBENn __reserve0

IRQ00ENn : Protection factor control by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Protection factor control by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ08ENn : Protection factor control by External Interrupt 8
bits : 2 - 4 (3 bit)
access : read-write

IRQ09ENn : Protection factor control by External Interrupt 9
bits : 3 - 6 (4 bit)
access : read-write

IRQ14ENn : Protection factor control by External Interrupt 14
bits : 4 - 8 (5 bit)
access : read-write

IRQ15ENn : Protection factor control by External Interrupt 15
bits : 5 - 10 (6 bit)
access : read-write

IRQ18ENn : Protection factor control by External Interrupt 18
bits : 6 - 12 (7 bit)
access : read-write

IRQ19ENn : Protection factor control by External Interrupt 19
bits : 7 - 14 (8 bit)
access : read-write

NMIENn : Protection factor control by NMI
bits : 8 - 16 (9 bit)
access : read-write

AD0ERRAENn : Protection factor control by A/D0 Conversion Error Detection
bits : 9 - 18 (10 bit)
access : read-write

AD0ERRBENn : Protection factor control by A/D0 Conversion Error Detection B
bits : 10 - 20 (11 bit)
access : read-write

AD1ERRAENn : Protection factor control by A/D1 Conversion Error Detection
bits : 11 - 22 (12 bit)
access : read-write

AD1ERRBENn : Protection factor control by A/D1 Conversion Error Detection B
bits : 12 - 24 (13 bit)
access : read-write

AD2ERRAENn : Protection factor control by A/D2 Conversion Error Detection
bits : 13 - 26 (14 bit)
access : read-write

AD2ERRBENn : Protection factor control by A/D2 Conversion Error Detection B
bits : 14 - 28 (15 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 15 - 30 (16 bit)
access : read


GPWM5OFFIRQB

GPWM5 Pi5 Protectio5 Factor Selectio5 Register B
address_offset : 0x53E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5OFFIRQB GPWM5OFFIRQB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Protection factor control by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Protection factor control by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Protection factor control by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Protection factor control by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Protection factor control by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Protection factor control by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Protection factor control by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Protection factor control by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Protection factor control by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Protection factor control by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM5PULSECNT

GPWM5 Pulse Co5trol Register
address_offset : 0x540 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5PULSECNT GPWM5PULSECNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTCTENn DTACTSELn DTCTASELn DTCTBSELn DTOVFRETn DTUDFRETn PRCTENn PRACTSELn PRRETSELn __reserve0

DTCTENn : Duty Cut enable
bits : 0 - 0 (1 bit)
access : read-write

DTACTSELn : Duty cut start factor polarity selection
bits : 1 - 2 (2 bit)
access : read-write

DTCTASELn : GPWMn operation selection when the duty cut
bits : 2 - 5 (4 bit)
access : read-write

DTCTBSELn : NGPWMn operation selection when the duty cut
bits : 4 - 9 (6 bit)
access : read-write

DTOVFRETn : Control of the return of duty cut by the overflow
bits : 6 - 12 (7 bit)
access : read-write

DTUDFRETn : Control of the return of duty cut by the underflow
bits : 7 - 14 (8 bit)
access : read-write

PRCTENn : Period Cut enable
bits : 8 - 16 (9 bit)
access : read-write

PRACTSELn : Period cut start factor polarity selection
bits : 9 - 18 (10 bit)
access : read-write

PRRETSELn : Period cut operation selection
bits : 10 - 20 (11 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 11 - 26 (16 bit)
access : read


GPWM5PULSEST

GPWM5 Pulse Co5trol Status Register
address_offset : 0x544 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5PULSEST GPWM5PULSEST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTCTSTn PRCTSTn __reserve0

DTCTSTn : Duty cut state
bits : 0 - 0 (1 bit)
access : read-write

PRCTSTn : Period cut state
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM5DUTYTRGA

GPWM5 Duty Cut Factor Selectio5 Register A
address_offset : 0x548 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5DUTYTRGA GPWM5DUTYTRGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ02ENn IRQ03ENn IRQ04ENn IRQ05ENn IRQ06ENn IRQ07ENn IRQ08ENn IRQ09ENn IRQ10ENn IRQ11ENn IRQ12ENn IRQ13ENn IRQ14ENn IRQ15ENn

IRQ00ENn : Duty cut start factor selection by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Duty cut start factor selection by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ02ENn : Duty cut start factor selection by External Interrupt 2
bits : 2 - 4 (3 bit)
access : read-write

IRQ03ENn : Duty cut start factor selection by External Interrupt 3
bits : 3 - 6 (4 bit)
access : read-write

IRQ04ENn : Duty cut start factor selection by External Interrupt 4
bits : 4 - 8 (5 bit)
access : read-write

IRQ05ENn : Duty cut start factor selection by External Interrupt 5
bits : 5 - 10 (6 bit)
access : read-write

IRQ06ENn : Duty cut start factor selection by External Interrupt 6
bits : 6 - 12 (7 bit)
access : read-write

IRQ07ENn : Duty cut start factor selection by External Interrupt 7
bits : 7 - 14 (8 bit)
access : read-write

IRQ08ENn : Duty cut start factor selection by External Interrupt 8
bits : 8 - 16 (9 bit)
access : read-write

IRQ09ENn : Duty cut start factor selection by External Interrupt 9
bits : 9 - 18 (10 bit)
access : read-write

IRQ10ENn : Duty cut start factor selection by External Interrupt 10
bits : 10 - 20 (11 bit)
access : read-write

IRQ11ENn : Duty cut start factor selection by External Interrupt 11
bits : 11 - 22 (12 bit)
access : read-write

IRQ12ENn : Duty cut start factor selection by External Interrupt 12
bits : 12 - 24 (13 bit)
access : read-write

IRQ13ENn : Duty cut start factor selection by External Interrupt 13
bits : 13 - 26 (14 bit)
access : read-write

IRQ14ENn : Duty cut start factor selection by External Interrupt 14
bits : 14 - 28 (15 bit)
access : read-write

IRQ15ENn : Duty cut start factor selection by External Interrupt 15
bits : 15 - 30 (16 bit)
access : read-write


GPWM5DUTYTRGB

GPWM5 Duty Cut Factor Selectio5 Register B
address_offset : 0x54A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5DUTYTRGB GPWM5DUTYTRGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Duty cut start factor selection by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Duty cut start factor selection by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Duty cut start factor selection by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Duty cut start factor selection by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Duty cut start factor selection by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Duty cut start factor selection by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Duty cut start factor selection by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Duty cut start factor selection by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Duty cut start factor selection by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Duty cut start factor selection by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM5PERITRGA

GPWM5 Period Cut Factor Selectio5 Register A
address_offset : 0x54C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5PERITRGA GPWM5PERITRGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ02ENn IRQ03ENn IRQ04ENn IRQ05ENn IRQ06ENn IRQ07ENn IRQ08ENn IRQ09ENn IRQ10ENn IRQ11ENn IRQ12ENn IRQ13ENn IRQ14ENn IRQ15ENn

IRQ00ENn : Period cut start factor selection by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Period cut start factor selection by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ02ENn : Period cut start factor selection by External Interrupt 2
bits : 2 - 4 (3 bit)
access : read-write

IRQ03ENn : Period cut start factor selection by External Interrupt 3
bits : 3 - 6 (4 bit)
access : read-write

IRQ04ENn : Period cut start factor selection by External Interrupt 4
bits : 4 - 8 (5 bit)
access : read-write

IRQ05ENn : Period cut start factor selection by External Interrupt 5
bits : 5 - 10 (6 bit)
access : read-write

IRQ06ENn : Period cut start factor selection by External Interrupt 6
bits : 6 - 12 (7 bit)
access : read-write

IRQ07ENn : Period cut start factor selection by External Interrupt 7
bits : 7 - 14 (8 bit)
access : read-write

IRQ08ENn : Period cut start factor selection by External Interrupt 8
bits : 8 - 16 (9 bit)
access : read-write

IRQ09ENn : Period cut start factor selection by External Interrupt 9
bits : 9 - 18 (10 bit)
access : read-write

IRQ10ENn : Period cut start factor selection by External Interrupt 10
bits : 10 - 20 (11 bit)
access : read-write

IRQ11ENn : Period cut start factor selection by External Interrupt 11
bits : 11 - 22 (12 bit)
access : read-write

IRQ12ENn : Period cut start factor selection by External Interrupt 12
bits : 12 - 24 (13 bit)
access : read-write

IRQ13ENn : Period cut start factor selection by External Interrupt 13
bits : 13 - 26 (14 bit)
access : read-write

IRQ14ENn : Period cut start factor selection by External Interrupt 14
bits : 14 - 28 (15 bit)
access : read-write

IRQ15ENn : Period cut start factor selection by External Interrupt 15
bits : 15 - 30 (16 bit)
access : read-write


GPWM5PERITRGB

GPWM5 Period Cut Factor Selectio5 Register B
address_offset : 0x54E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5PERITRGB GPWM5PERITRGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Period cut start factor selection by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Period cut start factor selection by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Period cut start factor selection by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Period cut start factor selection by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Period cut start factor selection by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Period cut start factor selection by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Period cut start factor selection by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Period cut start factor selection by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Period cut start factor selection by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Period cut start factor selection by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM5DBUPDATE

GPWM5 Double Buffer Updati5g E5able Register
address_offset : 0x550 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM5DBUPDATE GPWM5DBUPDATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUPn __reserve0

DUPn : Double buffer updating enable
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read


GPWM6MD

GPWM6 Mode Register
address_offset : 0x600 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6MD GPWM6MD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAVEMDn TCENn HRSELn HRPRENn SYNCENn DUPENn PCRBENn PCRAENn SDSELBn SDSELAn __reserve0 CLKSELn __reserve1 SFTENn SDIRn __reserve2

WAVEMDn : PWM waveform mode select
bits : 0 - 0 (1 bit)
access : read-write

TCENn : PWM Operation control
bits : 1 - 2 (2 bit)
access : read-write

HRSELn : High resolution output function enable
bits : 2 - 4 (3 bit)
access : read-write

HRPRENn : High resolution cycle function enable
bits : 3 - 6 (4 bit)
access : read-write

SYNCENn : Synchronous start function (MFA) enable
bits : 4 - 8 (5 bit)
access : read-write

DUPENn : Double buffer updating enable register selection
bits : 5 - 10 (6 bit)
access : read-write

PCRBENn : Double buffer load timing enable (GPWMnBC overflow)
bits : 6 - 12 (7 bit)
access : read-write

PCRAENn : Double buffer load timing enable (GPWMnBC underflow)
bits : 7 - 14 (8 bit)
access : read-write

SDSELBn : GPWMnSEL buffer mode
bits : 8 - 16 (9 bit)
access : read-write

SDSELAn : GPWMnOUTMD buffer mode
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 20 (11 bit)
access : read

CLKSELn : Count clock selection
bits : 11 - 22 (12 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 12 - 24 (13 bit)
access : read

SFTENn : PWM output shift function enable
bits : 13 - 26 (14 bit)
access : read-write

SDIRn : Shift direction control
bits : 14 - 28 (15 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 15 - 30 (16 bit)
access : read


GPWM6OUTMD

GPWM6 Output Polarity Co6trol Register
address_offset : 0x604 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6OUTMD GPWM6OUTMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PXDTn PXDTNn __reserve0

PXDTn : GPWMn output polarity
bits : 0 - 0 (1 bit)
access : read-write

PXDTNn : NGPWMn output polarity
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM6SEL

GPWM6 Output Co6trol Register
address_offset : 0x608 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6SEL GPWM6SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTLVn OTLVNn PSELn PSELNn __reserve0

OTLVn : GPWMn High/Low-level output
bits : 0 - 0 (1 bit)
access : read-write

OTLVNn : NGPWMn High/Low-level output
bits : 1 - 2 (2 bit)
access : read-write

PSELn : GPWMn output sources
bits : 2 - 4 (3 bit)
access : read-write

PSELNn : NGPWMn output sources
bits : 3 - 6 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read


GPWM6BC

GPWM6BC Value Read Register
address_offset : 0x60C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6BC GPWM6BC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCn

BCn : Read the binary counter value of GPWMn
bits : 0 - 15 (16 bit)
access : read


GPWM6BCSTR

GPWM6BC Status Read Register
address_offset : 0x60E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6BCSTR GPWM6BCSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRn __reserve0

STRn : GPWMn binary counter's counting status read
bits : 0 - 0 (1 bit)
access : read

__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read


GPWM6HRSET

GPWM6 High Resolutio6 Cycle Setti6g Register
address_offset : 0x610 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6HRSET GPWM6HRSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRSETn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRSETn : Set high resolution cycle
bits : 11 - 26 (16 bit)
access : read-write


GPWM6SET

GPWM6 Cycle Setti6g Register
address_offset : 0x612 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6SET GPWM6SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETn

SETn : Set the cycle to the GPWMn 16-bit counter.
bits : 0 - 15 (16 bit)
access : read-write


GPWM6TCMPHR

GPWM6 High Resolutio6 Phase Compariso6 Setti6g Register
address_offset : 0x614 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6TCMPHR GPWM6TCMPHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRTCPn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRTCPn : Set phase comparison high resolution
bits : 11 - 26 (16 bit)
access : read-write


GPWM6TCMP

GPWM6 Phase Compariso6 Setti6g Register
address_offset : 0x616 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6TCMP GPWM6TCMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCPn

TCPn : Set the timing to change output of GPWMn.
bits : 0 - 15 (16 bit)
access : read-write


GPWM6DHRDAT

GPWM6 High Resolutio6 Output Shift Amou6t Setti6g Register
address_offset : 0x618 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6DHRDAT GPWM6DHRDAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRSTIMn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRSTIMn : Set high resolution output shift amount
bits : 11 - 26 (16 bit)
access : read-write


GPWM6DDAT

GPWM6 Output Shift Amou6t Setti6g Register
address_offset : 0x61A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6DDAT GPWM6DDAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STIMn

STIMn : Set GPWMn output shift amount
bits : 0 - 15 (16 bit)
access : read-write


GPWM6DTMCNT

GPWM6 Dead Time Co6trol Register
address_offset : 0x620 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6DTMCNT GPWM6DTMCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTENn ORMDn NORMDn SLFCNTn __reserve0

DTENn : Dead time insertion
bits : 0 - 0 (1 bit)
access : read-write

ORMDn : GPWMn dead time insertion logic
bits : 1 - 2 (2 bit)
access : read-write

NORMDn : NGPWMn dead time insertion logic
bits : 2 - 4 (3 bit)
access : read-write

SLFCNTn : Dead time width automatic control enable
bits : 3 - 6 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read


GPWM6DTMSETA

GPWM6 Dead Time Setti6g Register A
address_offset : 0x624 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6DTMSETA GPWM6DTMSETA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTSTAn __reserve0

DTSTAn : Set dead time for GPWMn.
bits : 0 - 9 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM6DTMSETB

GPWM6 Dead Time Setti6g Register B
address_offset : 0x626 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6DTMSETB GPWM6DTMSETB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTSTBn __reserve0

DTSTBn : Set dead time for NGPWMn.
bits : 0 - 9 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM6ADST

GPWM6 Sy6chro6ous Trigger Setti6g Register
address_offset : 0x628 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6ADST GPWM6ADST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PASTn

PASTn : Set the value of starting GPWMn synchronous A/D.
bits : 0 - 15 (16 bit)
access : read-write


GPWM6ADSTSEL

GPWM6 Sy6chro6ous Trigger Polarity Selectio6 Register
address_offset : 0x62A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6ADSTSEL GPWM6ADSTSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PASTUPn PASTDNn __reserve0

PASTUPn : Set the timing of synchronous trigger generation.
bits : 0 - 0 (1 bit)
access : read-write

PASTDNn : Set the timing of synchronous trigger generation.
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM6ADBC

GPWM6 Sy6chro6ous Bi6ary Cou6ter Read Register
address_offset : 0x62C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6ADBC GPWM6ADBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADBCn

ADBCn : Read the binary count for starting GPWMn synchronous A/D.
bits : 0 - 15 (16 bit)
access : read


GPWM6IRQCNT

GPWM6 UDF/OVF I6terrupt Output Co6trol Register
address_offset : 0x630 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6IRQCNT GPWM6IRQCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDFCNTn UDFSCNTn OVFCNTn OVFSCNTn

UDFCNTn : Number of times setting for GPWMn underflow interrupt (Second time or later)
bits : 0 - 3 (4 bit)
access : read-write

UDFSCNTn : Number of times setting for GPWMn underflow interrupt (First time)
bits : 4 - 11 (8 bit)
access : read-write

OVFCNTn : Number of times setting for GPWMn overflow interrupt (Second time or later)
bits : 8 - 19 (12 bit)
access : read-write

OVFSCNTn : Number of times setting for GPWMn overflow interrupt (First time)
bits : 12 - 27 (16 bit)
access : read-write


GPWM6ADIRQCNT

GPWM6 A/D Start I6terrupt Output Co6trol Register
address_offset : 0x634 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6ADIRQCNT GPWM6ADIRQCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASTCNTn ASTSCNTn __reserve0

ASTCNTn : Number of times setting for GPWMn synchronous A/D start interrupt (Second time or later)
bits : 0 - 3 (4 bit)
access : read-write

ASTSCNTn : Number of times setting for GPWMn synchronous A/D start interrupt (First time)
bits : 4 - 11 (8 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read


GPWM6OFF

GPWM6 Pi6 Protectio6 Co6trol Register
address_offset : 0x638 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6OFF GPWM6OFF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTENn __reserve0 PRT PRTN __reserve1

OUTENn : GPWMn pin output enable
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 4 (4 bit)
access : read

PRT : GPWMOUTn output pin protection function
bits : 4 - 9 (6 bit)
access : read-write

PRTN : NGPWMOUTn output pin protection function
bits : 6 - 13 (8 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read


GPWM6OFFIRQA

GPWM6 Pi6 Protectio6 Factor Selectio6 Register A
address_offset : 0x63C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6OFFIRQA GPWM6OFFIRQA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ08ENn IRQ09ENn IRQ14ENn IRQ15ENn IRQ18ENn IRQ19ENn NMIENn AD0ERRAENn AD0ERRBENn AD1ERRAENn AD1ERRBENn AD2ERRAENn AD2ERRBENn __reserve0

IRQ00ENn : Protection factor control by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Protection factor control by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ08ENn : Protection factor control by External Interrupt 8
bits : 2 - 4 (3 bit)
access : read-write

IRQ09ENn : Protection factor control by External Interrupt 9
bits : 3 - 6 (4 bit)
access : read-write

IRQ14ENn : Protection factor control by External Interrupt 14
bits : 4 - 8 (5 bit)
access : read-write

IRQ15ENn : Protection factor control by External Interrupt 15
bits : 5 - 10 (6 bit)
access : read-write

IRQ18ENn : Protection factor control by External Interrupt 18
bits : 6 - 12 (7 bit)
access : read-write

IRQ19ENn : Protection factor control by External Interrupt 19
bits : 7 - 14 (8 bit)
access : read-write

NMIENn : Protection factor control by NMI
bits : 8 - 16 (9 bit)
access : read-write

AD0ERRAENn : Protection factor control by A/D0 Conversion Error Detection
bits : 9 - 18 (10 bit)
access : read-write

AD0ERRBENn : Protection factor control by A/D0 Conversion Error Detection B
bits : 10 - 20 (11 bit)
access : read-write

AD1ERRAENn : Protection factor control by A/D1 Conversion Error Detection
bits : 11 - 22 (12 bit)
access : read-write

AD1ERRBENn : Protection factor control by A/D1 Conversion Error Detection B
bits : 12 - 24 (13 bit)
access : read-write

AD2ERRAENn : Protection factor control by A/D2 Conversion Error Detection
bits : 13 - 26 (14 bit)
access : read-write

AD2ERRBENn : Protection factor control by A/D2 Conversion Error Detection B
bits : 14 - 28 (15 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 15 - 30 (16 bit)
access : read


GPWM6OFFIRQB

GPWM6 Pi6 Protectio6 Factor Selectio6 Register B
address_offset : 0x63E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6OFFIRQB GPWM6OFFIRQB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Protection factor control by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Protection factor control by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Protection factor control by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Protection factor control by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Protection factor control by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Protection factor control by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Protection factor control by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Protection factor control by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Protection factor control by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Protection factor control by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM6PULSECNT

GPWM6 Pulse Co6trol Register
address_offset : 0x640 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6PULSECNT GPWM6PULSECNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTCTENn DTACTSELn DTCTASELn DTCTBSELn DTOVFRETn DTUDFRETn PRCTENn PRACTSELn PRRETSELn __reserve0

DTCTENn : Duty Cut enable
bits : 0 - 0 (1 bit)
access : read-write

DTACTSELn : Duty cut start factor polarity selection
bits : 1 - 2 (2 bit)
access : read-write

DTCTASELn : GPWMn operation selection when the duty cut
bits : 2 - 5 (4 bit)
access : read-write

DTCTBSELn : NGPWMn operation selection when the duty cut
bits : 4 - 9 (6 bit)
access : read-write

DTOVFRETn : Control of the return of duty cut by the overflow
bits : 6 - 12 (7 bit)
access : read-write

DTUDFRETn : Control of the return of duty cut by the underflow
bits : 7 - 14 (8 bit)
access : read-write

PRCTENn : Period Cut enable
bits : 8 - 16 (9 bit)
access : read-write

PRACTSELn : Period cut start factor polarity selection
bits : 9 - 18 (10 bit)
access : read-write

PRRETSELn : Period cut operation selection
bits : 10 - 20 (11 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 11 - 26 (16 bit)
access : read


GPWM6PULSEST

GPWM6 Pulse Co6trol Status Register
address_offset : 0x644 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6PULSEST GPWM6PULSEST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTCTSTn PRCTSTn __reserve0

DTCTSTn : Duty cut state
bits : 0 - 0 (1 bit)
access : read-write

PRCTSTn : Period cut state
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM6DUTYTRGA

GPWM6 Duty Cut Factor Selectio6 Register A
address_offset : 0x648 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6DUTYTRGA GPWM6DUTYTRGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ02ENn IRQ03ENn IRQ04ENn IRQ05ENn IRQ06ENn IRQ07ENn IRQ08ENn IRQ09ENn IRQ10ENn IRQ11ENn IRQ12ENn IRQ13ENn IRQ14ENn IRQ15ENn

IRQ00ENn : Duty cut start factor selection by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Duty cut start factor selection by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ02ENn : Duty cut start factor selection by External Interrupt 2
bits : 2 - 4 (3 bit)
access : read-write

IRQ03ENn : Duty cut start factor selection by External Interrupt 3
bits : 3 - 6 (4 bit)
access : read-write

IRQ04ENn : Duty cut start factor selection by External Interrupt 4
bits : 4 - 8 (5 bit)
access : read-write

IRQ05ENn : Duty cut start factor selection by External Interrupt 5
bits : 5 - 10 (6 bit)
access : read-write

IRQ06ENn : Duty cut start factor selection by External Interrupt 6
bits : 6 - 12 (7 bit)
access : read-write

IRQ07ENn : Duty cut start factor selection by External Interrupt 7
bits : 7 - 14 (8 bit)
access : read-write

IRQ08ENn : Duty cut start factor selection by External Interrupt 8
bits : 8 - 16 (9 bit)
access : read-write

IRQ09ENn : Duty cut start factor selection by External Interrupt 9
bits : 9 - 18 (10 bit)
access : read-write

IRQ10ENn : Duty cut start factor selection by External Interrupt 10
bits : 10 - 20 (11 bit)
access : read-write

IRQ11ENn : Duty cut start factor selection by External Interrupt 11
bits : 11 - 22 (12 bit)
access : read-write

IRQ12ENn : Duty cut start factor selection by External Interrupt 12
bits : 12 - 24 (13 bit)
access : read-write

IRQ13ENn : Duty cut start factor selection by External Interrupt 13
bits : 13 - 26 (14 bit)
access : read-write

IRQ14ENn : Duty cut start factor selection by External Interrupt 14
bits : 14 - 28 (15 bit)
access : read-write

IRQ15ENn : Duty cut start factor selection by External Interrupt 15
bits : 15 - 30 (16 bit)
access : read-write


GPWM6DUTYTRGB

GPWM6 Duty Cut Factor Selectio6 Register B
address_offset : 0x64A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6DUTYTRGB GPWM6DUTYTRGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Duty cut start factor selection by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Duty cut start factor selection by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Duty cut start factor selection by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Duty cut start factor selection by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Duty cut start factor selection by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Duty cut start factor selection by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Duty cut start factor selection by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Duty cut start factor selection by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Duty cut start factor selection by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Duty cut start factor selection by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM6PERITRGA

GPWM6 Period Cut Factor Selectio6 Register A
address_offset : 0x64C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6PERITRGA GPWM6PERITRGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ02ENn IRQ03ENn IRQ04ENn IRQ05ENn IRQ06ENn IRQ07ENn IRQ08ENn IRQ09ENn IRQ10ENn IRQ11ENn IRQ12ENn IRQ13ENn IRQ14ENn IRQ15ENn

IRQ00ENn : Period cut start factor selection by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Period cut start factor selection by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ02ENn : Period cut start factor selection by External Interrupt 2
bits : 2 - 4 (3 bit)
access : read-write

IRQ03ENn : Period cut start factor selection by External Interrupt 3
bits : 3 - 6 (4 bit)
access : read-write

IRQ04ENn : Period cut start factor selection by External Interrupt 4
bits : 4 - 8 (5 bit)
access : read-write

IRQ05ENn : Period cut start factor selection by External Interrupt 5
bits : 5 - 10 (6 bit)
access : read-write

IRQ06ENn : Period cut start factor selection by External Interrupt 6
bits : 6 - 12 (7 bit)
access : read-write

IRQ07ENn : Period cut start factor selection by External Interrupt 7
bits : 7 - 14 (8 bit)
access : read-write

IRQ08ENn : Period cut start factor selection by External Interrupt 8
bits : 8 - 16 (9 bit)
access : read-write

IRQ09ENn : Period cut start factor selection by External Interrupt 9
bits : 9 - 18 (10 bit)
access : read-write

IRQ10ENn : Period cut start factor selection by External Interrupt 10
bits : 10 - 20 (11 bit)
access : read-write

IRQ11ENn : Period cut start factor selection by External Interrupt 11
bits : 11 - 22 (12 bit)
access : read-write

IRQ12ENn : Period cut start factor selection by External Interrupt 12
bits : 12 - 24 (13 bit)
access : read-write

IRQ13ENn : Period cut start factor selection by External Interrupt 13
bits : 13 - 26 (14 bit)
access : read-write

IRQ14ENn : Period cut start factor selection by External Interrupt 14
bits : 14 - 28 (15 bit)
access : read-write

IRQ15ENn : Period cut start factor selection by External Interrupt 15
bits : 15 - 30 (16 bit)
access : read-write


GPWM6PERITRGB

GPWM6 Period Cut Factor Selectio6 Register B
address_offset : 0x64E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6PERITRGB GPWM6PERITRGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Period cut start factor selection by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Period cut start factor selection by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Period cut start factor selection by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Period cut start factor selection by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Period cut start factor selection by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Period cut start factor selection by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Period cut start factor selection by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Period cut start factor selection by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Period cut start factor selection by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Period cut start factor selection by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM6DBUPDATE

GPWM6 Double Buffer Updati6g E6able Register
address_offset : 0x650 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM6DBUPDATE GPWM6DBUPDATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUPn __reserve0

DUPn : Double buffer updating enable
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read


GPWM7MD

GPWM7 Mode Register
address_offset : 0x700 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7MD GPWM7MD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAVEMDn TCENn HRSELn HRPRENn SYNCENn DUPENn PCRBENn PCRAENn SDSELBn SDSELAn __reserve0 CLKSELn __reserve1 SFTENn SDIRn __reserve2

WAVEMDn : PWM waveform mode select
bits : 0 - 0 (1 bit)
access : read-write

TCENn : PWM Operation control
bits : 1 - 2 (2 bit)
access : read-write

HRSELn : High resolution output function enable
bits : 2 - 4 (3 bit)
access : read-write

HRPRENn : High resolution cycle function enable
bits : 3 - 6 (4 bit)
access : read-write

SYNCENn : Synchronous start function (MFA) enable
bits : 4 - 8 (5 bit)
access : read-write

DUPENn : Double buffer updating enable register selection
bits : 5 - 10 (6 bit)
access : read-write

PCRBENn : Double buffer load timing enable (GPWMnBC overflow)
bits : 6 - 12 (7 bit)
access : read-write

PCRAENn : Double buffer load timing enable (GPWMnBC underflow)
bits : 7 - 14 (8 bit)
access : read-write

SDSELBn : GPWMnSEL buffer mode
bits : 8 - 16 (9 bit)
access : read-write

SDSELAn : GPWMnOUTMD buffer mode
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 20 (11 bit)
access : read

CLKSELn : Count clock selection
bits : 11 - 22 (12 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 12 - 24 (13 bit)
access : read

SFTENn : PWM output shift function enable
bits : 13 - 26 (14 bit)
access : read-write

SDIRn : Shift direction control
bits : 14 - 28 (15 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 15 - 30 (16 bit)
access : read


GPWM7OUTMD

GPWM7 Output Polarity Co7trol Register
address_offset : 0x704 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7OUTMD GPWM7OUTMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PXDTn PXDTNn __reserve0

PXDTn : GPWMn output polarity
bits : 0 - 0 (1 bit)
access : read-write

PXDTNn : NGPWMn output polarity
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM7SEL

GPWM7 Output Co7trol Register
address_offset : 0x708 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7SEL GPWM7SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTLVn OTLVNn PSELn PSELNn __reserve0

OTLVn : GPWMn High/Low-level output
bits : 0 - 0 (1 bit)
access : read-write

OTLVNn : NGPWMn High/Low-level output
bits : 1 - 2 (2 bit)
access : read-write

PSELn : GPWMn output sources
bits : 2 - 4 (3 bit)
access : read-write

PSELNn : NGPWMn output sources
bits : 3 - 6 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read


GPWM7BC

GPWM7BC Value Read Register
address_offset : 0x70C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7BC GPWM7BC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCn

BCn : Read the binary counter value of GPWMn
bits : 0 - 15 (16 bit)
access : read


GPWM7BCSTR

GPWM7BC Status Read Register
address_offset : 0x70E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7BCSTR GPWM7BCSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRn __reserve0

STRn : GPWMn binary counter's counting status read
bits : 0 - 0 (1 bit)
access : read

__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read


GPWM7HRSET

GPWM7 High Resolutio7 Cycle Setti7g Register
address_offset : 0x710 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7HRSET GPWM7HRSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRSETn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRSETn : Set high resolution cycle
bits : 11 - 26 (16 bit)
access : read-write


GPWM7SET

GPWM7 Cycle Setti7g Register
address_offset : 0x712 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7SET GPWM7SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETn

SETn : Set the cycle to the GPWMn 16-bit counter.
bits : 0 - 15 (16 bit)
access : read-write


GPWM7TCMPHR

GPWM7 High Resolutio7 Phase Compariso7 Setti7g Register
address_offset : 0x714 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7TCMPHR GPWM7TCMPHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRTCPn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRTCPn : Set phase comparison high resolution
bits : 11 - 26 (16 bit)
access : read-write


GPWM7TCMP

GPWM7 Phase Compariso7 Setti7g Register
address_offset : 0x716 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7TCMP GPWM7TCMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCPn

TCPn : Set the timing to change output of GPWMn.
bits : 0 - 15 (16 bit)
access : read-write


GPWM7DHRDAT

GPWM7 High Resolutio7 Output Shift Amou7t Setti7g Register
address_offset : 0x718 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7DHRDAT GPWM7DHRDAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRSTIMn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRSTIMn : Set high resolution output shift amount
bits : 11 - 26 (16 bit)
access : read-write


GPWM7DDAT

GPWM7 Output Shift Amou7t Setti7g Register
address_offset : 0x71A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7DDAT GPWM7DDAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STIMn

STIMn : Set GPWMn output shift amount
bits : 0 - 15 (16 bit)
access : read-write


GPWM7DTMCNT

GPWM7 Dead Time Co7trol Register
address_offset : 0x720 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7DTMCNT GPWM7DTMCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTENn ORMDn NORMDn SLFCNTn __reserve0

DTENn : Dead time insertion
bits : 0 - 0 (1 bit)
access : read-write

ORMDn : GPWMn dead time insertion logic
bits : 1 - 2 (2 bit)
access : read-write

NORMDn : NGPWMn dead time insertion logic
bits : 2 - 4 (3 bit)
access : read-write

SLFCNTn : Dead time width automatic control enable
bits : 3 - 6 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read


GPWM7DTMSETA

GPWM7 Dead Time Setti7g Register A
address_offset : 0x724 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7DTMSETA GPWM7DTMSETA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTSTAn __reserve0

DTSTAn : Set dead time for GPWMn.
bits : 0 - 9 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM7DTMSETB

GPWM7 Dead Time Setti7g Register B
address_offset : 0x726 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7DTMSETB GPWM7DTMSETB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTSTBn __reserve0

DTSTBn : Set dead time for NGPWMn.
bits : 0 - 9 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM7ADST

GPWM7 Sy7chro7ous Trigger Setti7g Register
address_offset : 0x728 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7ADST GPWM7ADST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PASTn

PASTn : Set the value of starting GPWMn synchronous A/D.
bits : 0 - 15 (16 bit)
access : read-write


GPWM7ADSTSEL

GPWM7 Sy7chro7ous Trigger Polarity Selectio7 Register
address_offset : 0x72A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7ADSTSEL GPWM7ADSTSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PASTUPn PASTDNn __reserve0

PASTUPn : Set the timing of synchronous trigger generation.
bits : 0 - 0 (1 bit)
access : read-write

PASTDNn : Set the timing of synchronous trigger generation.
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM7ADBC

GPWM7 Sy7chro7ous Bi7ary Cou7ter Read Register
address_offset : 0x72C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7ADBC GPWM7ADBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADBCn

ADBCn : Read the binary count for starting GPWMn synchronous A/D.
bits : 0 - 15 (16 bit)
access : read


GPWM7IRQCNT

GPWM7 UDF/OVF I7terrupt Output Co7trol Register
address_offset : 0x730 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7IRQCNT GPWM7IRQCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDFCNTn UDFSCNTn OVFCNTn OVFSCNTn

UDFCNTn : Number of times setting for GPWMn underflow interrupt (Second time or later)
bits : 0 - 3 (4 bit)
access : read-write

UDFSCNTn : Number of times setting for GPWMn underflow interrupt (First time)
bits : 4 - 11 (8 bit)
access : read-write

OVFCNTn : Number of times setting for GPWMn overflow interrupt (Second time or later)
bits : 8 - 19 (12 bit)
access : read-write

OVFSCNTn : Number of times setting for GPWMn overflow interrupt (First time)
bits : 12 - 27 (16 bit)
access : read-write


GPWM7ADIRQCNT

GPWM7 A/D Start I7terrupt Output Co7trol Register
address_offset : 0x734 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7ADIRQCNT GPWM7ADIRQCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASTCNTn ASTSCNTn __reserve0

ASTCNTn : Number of times setting for GPWMn synchronous A/D start interrupt (Second time or later)
bits : 0 - 3 (4 bit)
access : read-write

ASTSCNTn : Number of times setting for GPWMn synchronous A/D start interrupt (First time)
bits : 4 - 11 (8 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read


GPWM7OFF

GPWM7 Pi7 Protectio7 Co7trol Register
address_offset : 0x738 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7OFF GPWM7OFF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTENn __reserve0 PRT PRTN __reserve1

OUTENn : GPWMn pin output enable
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 4 (4 bit)
access : read

PRT : GPWMOUTn output pin protection function
bits : 4 - 9 (6 bit)
access : read-write

PRTN : NGPWMOUTn output pin protection function
bits : 6 - 13 (8 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read


GPWM7OFFIRQA

GPWM7 Pi7 Protectio7 Factor Selectio7 Register A
address_offset : 0x73C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7OFFIRQA GPWM7OFFIRQA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ08ENn IRQ09ENn IRQ14ENn IRQ15ENn IRQ18ENn IRQ19ENn NMIENn AD0ERRAENn AD0ERRBENn AD1ERRAENn AD1ERRBENn AD2ERRAENn AD2ERRBENn __reserve0

IRQ00ENn : Protection factor control by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Protection factor control by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ08ENn : Protection factor control by External Interrupt 8
bits : 2 - 4 (3 bit)
access : read-write

IRQ09ENn : Protection factor control by External Interrupt 9
bits : 3 - 6 (4 bit)
access : read-write

IRQ14ENn : Protection factor control by External Interrupt 14
bits : 4 - 8 (5 bit)
access : read-write

IRQ15ENn : Protection factor control by External Interrupt 15
bits : 5 - 10 (6 bit)
access : read-write

IRQ18ENn : Protection factor control by External Interrupt 18
bits : 6 - 12 (7 bit)
access : read-write

IRQ19ENn : Protection factor control by External Interrupt 19
bits : 7 - 14 (8 bit)
access : read-write

NMIENn : Protection factor control by NMI
bits : 8 - 16 (9 bit)
access : read-write

AD0ERRAENn : Protection factor control by A/D0 Conversion Error Detection
bits : 9 - 18 (10 bit)
access : read-write

AD0ERRBENn : Protection factor control by A/D0 Conversion Error Detection B
bits : 10 - 20 (11 bit)
access : read-write

AD1ERRAENn : Protection factor control by A/D1 Conversion Error Detection
bits : 11 - 22 (12 bit)
access : read-write

AD1ERRBENn : Protection factor control by A/D1 Conversion Error Detection B
bits : 12 - 24 (13 bit)
access : read-write

AD2ERRAENn : Protection factor control by A/D2 Conversion Error Detection
bits : 13 - 26 (14 bit)
access : read-write

AD2ERRBENn : Protection factor control by A/D2 Conversion Error Detection B
bits : 14 - 28 (15 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 15 - 30 (16 bit)
access : read


GPWM7OFFIRQB

GPWM7 Pi7 Protectio7 Factor Selectio7 Register B
address_offset : 0x73E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7OFFIRQB GPWM7OFFIRQB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Protection factor control by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Protection factor control by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Protection factor control by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Protection factor control by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Protection factor control by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Protection factor control by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Protection factor control by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Protection factor control by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Protection factor control by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Protection factor control by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM7PULSECNT

GPWM7 Pulse Co7trol Register
address_offset : 0x740 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7PULSECNT GPWM7PULSECNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTCTENn DTACTSELn DTCTASELn DTCTBSELn DTOVFRETn DTUDFRETn PRCTENn PRACTSELn PRRETSELn __reserve0

DTCTENn : Duty Cut enable
bits : 0 - 0 (1 bit)
access : read-write

DTACTSELn : Duty cut start factor polarity selection
bits : 1 - 2 (2 bit)
access : read-write

DTCTASELn : GPWMn operation selection when the duty cut
bits : 2 - 5 (4 bit)
access : read-write

DTCTBSELn : NGPWMn operation selection when the duty cut
bits : 4 - 9 (6 bit)
access : read-write

DTOVFRETn : Control of the return of duty cut by the overflow
bits : 6 - 12 (7 bit)
access : read-write

DTUDFRETn : Control of the return of duty cut by the underflow
bits : 7 - 14 (8 bit)
access : read-write

PRCTENn : Period Cut enable
bits : 8 - 16 (9 bit)
access : read-write

PRACTSELn : Period cut start factor polarity selection
bits : 9 - 18 (10 bit)
access : read-write

PRRETSELn : Period cut operation selection
bits : 10 - 20 (11 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 11 - 26 (16 bit)
access : read


GPWM7PULSEST

GPWM7 Pulse Co7trol Status Register
address_offset : 0x744 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7PULSEST GPWM7PULSEST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTCTSTn PRCTSTn __reserve0

DTCTSTn : Duty cut state
bits : 0 - 0 (1 bit)
access : read-write

PRCTSTn : Period cut state
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM7DUTYTRGA

GPWM7 Duty Cut Factor Selectio7 Register A
address_offset : 0x748 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7DUTYTRGA GPWM7DUTYTRGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ02ENn IRQ03ENn IRQ04ENn IRQ05ENn IRQ06ENn IRQ07ENn IRQ08ENn IRQ09ENn IRQ10ENn IRQ11ENn IRQ12ENn IRQ13ENn IRQ14ENn IRQ15ENn

IRQ00ENn : Duty cut start factor selection by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Duty cut start factor selection by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ02ENn : Duty cut start factor selection by External Interrupt 2
bits : 2 - 4 (3 bit)
access : read-write

IRQ03ENn : Duty cut start factor selection by External Interrupt 3
bits : 3 - 6 (4 bit)
access : read-write

IRQ04ENn : Duty cut start factor selection by External Interrupt 4
bits : 4 - 8 (5 bit)
access : read-write

IRQ05ENn : Duty cut start factor selection by External Interrupt 5
bits : 5 - 10 (6 bit)
access : read-write

IRQ06ENn : Duty cut start factor selection by External Interrupt 6
bits : 6 - 12 (7 bit)
access : read-write

IRQ07ENn : Duty cut start factor selection by External Interrupt 7
bits : 7 - 14 (8 bit)
access : read-write

IRQ08ENn : Duty cut start factor selection by External Interrupt 8
bits : 8 - 16 (9 bit)
access : read-write

IRQ09ENn : Duty cut start factor selection by External Interrupt 9
bits : 9 - 18 (10 bit)
access : read-write

IRQ10ENn : Duty cut start factor selection by External Interrupt 10
bits : 10 - 20 (11 bit)
access : read-write

IRQ11ENn : Duty cut start factor selection by External Interrupt 11
bits : 11 - 22 (12 bit)
access : read-write

IRQ12ENn : Duty cut start factor selection by External Interrupt 12
bits : 12 - 24 (13 bit)
access : read-write

IRQ13ENn : Duty cut start factor selection by External Interrupt 13
bits : 13 - 26 (14 bit)
access : read-write

IRQ14ENn : Duty cut start factor selection by External Interrupt 14
bits : 14 - 28 (15 bit)
access : read-write

IRQ15ENn : Duty cut start factor selection by External Interrupt 15
bits : 15 - 30 (16 bit)
access : read-write


GPWM7DUTYTRGB

GPWM7 Duty Cut Factor Selectio7 Register B
address_offset : 0x74A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7DUTYTRGB GPWM7DUTYTRGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Duty cut start factor selection by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Duty cut start factor selection by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Duty cut start factor selection by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Duty cut start factor selection by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Duty cut start factor selection by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Duty cut start factor selection by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Duty cut start factor selection by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Duty cut start factor selection by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Duty cut start factor selection by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Duty cut start factor selection by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM7PERITRGA

GPWM7 Period Cut Factor Selectio7 Register A
address_offset : 0x74C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7PERITRGA GPWM7PERITRGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ02ENn IRQ03ENn IRQ04ENn IRQ05ENn IRQ06ENn IRQ07ENn IRQ08ENn IRQ09ENn IRQ10ENn IRQ11ENn IRQ12ENn IRQ13ENn IRQ14ENn IRQ15ENn

IRQ00ENn : Period cut start factor selection by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Period cut start factor selection by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ02ENn : Period cut start factor selection by External Interrupt 2
bits : 2 - 4 (3 bit)
access : read-write

IRQ03ENn : Period cut start factor selection by External Interrupt 3
bits : 3 - 6 (4 bit)
access : read-write

IRQ04ENn : Period cut start factor selection by External Interrupt 4
bits : 4 - 8 (5 bit)
access : read-write

IRQ05ENn : Period cut start factor selection by External Interrupt 5
bits : 5 - 10 (6 bit)
access : read-write

IRQ06ENn : Period cut start factor selection by External Interrupt 6
bits : 6 - 12 (7 bit)
access : read-write

IRQ07ENn : Period cut start factor selection by External Interrupt 7
bits : 7 - 14 (8 bit)
access : read-write

IRQ08ENn : Period cut start factor selection by External Interrupt 8
bits : 8 - 16 (9 bit)
access : read-write

IRQ09ENn : Period cut start factor selection by External Interrupt 9
bits : 9 - 18 (10 bit)
access : read-write

IRQ10ENn : Period cut start factor selection by External Interrupt 10
bits : 10 - 20 (11 bit)
access : read-write

IRQ11ENn : Period cut start factor selection by External Interrupt 11
bits : 11 - 22 (12 bit)
access : read-write

IRQ12ENn : Period cut start factor selection by External Interrupt 12
bits : 12 - 24 (13 bit)
access : read-write

IRQ13ENn : Period cut start factor selection by External Interrupt 13
bits : 13 - 26 (14 bit)
access : read-write

IRQ14ENn : Period cut start factor selection by External Interrupt 14
bits : 14 - 28 (15 bit)
access : read-write

IRQ15ENn : Period cut start factor selection by External Interrupt 15
bits : 15 - 30 (16 bit)
access : read-write


GPWM7PERITRGB

GPWM7 Period Cut Factor Selectio7 Register B
address_offset : 0x74E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7PERITRGB GPWM7PERITRGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Period cut start factor selection by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Period cut start factor selection by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Period cut start factor selection by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Period cut start factor selection by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Period cut start factor selection by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Period cut start factor selection by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Period cut start factor selection by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Period cut start factor selection by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Period cut start factor selection by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Period cut start factor selection by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM7DBUPDATE

GPWM7 Double Buffer Updati7g E7able Register
address_offset : 0x750 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM7DBUPDATE GPWM7DBUPDATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUPn __reserve0

DUPn : Double buffer updating enable
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read


GPWM0SEL

GPWM0 Output Co0trol Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0SEL GPWM0SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTLVn OTLVNn PSELn PSELNn __reserve0

OTLVn : GPWMn High/Low-level output
bits : 0 - 0 (1 bit)
access : read-write

OTLVNn : NGPWMn High/Low-level output
bits : 1 - 2 (2 bit)
access : read-write

PSELn : GPWMn output sources
bits : 2 - 4 (3 bit)
access : read-write

PSELNn : NGPWMn output sources
bits : 3 - 6 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read


GPWM8MD

GPWM8 Mode Register
address_offset : 0x800 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8MD GPWM8MD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAVEMDn TCENn HRSELn HRPRENn SYNCENn DUPENn PCRBENn PCRAENn SDSELBn SDSELAn __reserve0 CLKSELn __reserve1 SFTENn SDIRn __reserve2

WAVEMDn : PWM waveform mode select
bits : 0 - 0 (1 bit)
access : read-write

TCENn : PWM Operation control
bits : 1 - 2 (2 bit)
access : read-write

HRSELn : High resolution output function enable
bits : 2 - 4 (3 bit)
access : read-write

HRPRENn : High resolution cycle function enable
bits : 3 - 6 (4 bit)
access : read-write

SYNCENn : Synchronous start function (MFA) enable
bits : 4 - 8 (5 bit)
access : read-write

DUPENn : Double buffer updating enable register selection
bits : 5 - 10 (6 bit)
access : read-write

PCRBENn : Double buffer load timing enable (GPWMnBC overflow)
bits : 6 - 12 (7 bit)
access : read-write

PCRAENn : Double buffer load timing enable (GPWMnBC underflow)
bits : 7 - 14 (8 bit)
access : read-write

SDSELBn : GPWMnSEL buffer mode
bits : 8 - 16 (9 bit)
access : read-write

SDSELAn : GPWMnOUTMD buffer mode
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 20 (11 bit)
access : read

CLKSELn : Count clock selection
bits : 11 - 22 (12 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 12 - 24 (13 bit)
access : read

SFTENn : PWM output shift function enable
bits : 13 - 26 (14 bit)
access : read-write

SDIRn : Shift direction control
bits : 14 - 28 (15 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 15 - 30 (16 bit)
access : read


GPWM8OUTMD

GPWM8 Output Polarity Co8trol Register
address_offset : 0x804 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8OUTMD GPWM8OUTMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PXDTn PXDTNn __reserve0

PXDTn : GPWMn output polarity
bits : 0 - 0 (1 bit)
access : read-write

PXDTNn : NGPWMn output polarity
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM8SEL

GPWM8 Output Co8trol Register
address_offset : 0x808 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8SEL GPWM8SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTLVn OTLVNn PSELn PSELNn __reserve0

OTLVn : GPWMn High/Low-level output
bits : 0 - 0 (1 bit)
access : read-write

OTLVNn : NGPWMn High/Low-level output
bits : 1 - 2 (2 bit)
access : read-write

PSELn : GPWMn output sources
bits : 2 - 4 (3 bit)
access : read-write

PSELNn : NGPWMn output sources
bits : 3 - 6 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read


GPWM8BC

GPWM8BC Value Read Register
address_offset : 0x80C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8BC GPWM8BC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCn

BCn : Read the binary counter value of GPWMn
bits : 0 - 15 (16 bit)
access : read


GPWM8BCSTR

GPWM8BC Status Read Register
address_offset : 0x80E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8BCSTR GPWM8BCSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRn __reserve0

STRn : GPWMn binary counter's counting status read
bits : 0 - 0 (1 bit)
access : read

__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read


GPWM8HRSET

GPWM8 High Resolutio8 Cycle Setti8g Register
address_offset : 0x810 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8HRSET GPWM8HRSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRSETn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRSETn : Set high resolution cycle
bits : 11 - 26 (16 bit)
access : read-write


GPWM8SET

GPWM8 Cycle Setti8g Register
address_offset : 0x812 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8SET GPWM8SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETn

SETn : Set the cycle to the GPWMn 16-bit counter.
bits : 0 - 15 (16 bit)
access : read-write


GPWM8TCMPHR

GPWM8 High Resolutio8 Phase Compariso8 Setti8g Register
address_offset : 0x814 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8TCMPHR GPWM8TCMPHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRTCPn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRTCPn : Set phase comparison high resolution
bits : 11 - 26 (16 bit)
access : read-write


GPWM8TCMP

GPWM8 Phase Compariso8 Setti8g Register
address_offset : 0x816 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8TCMP GPWM8TCMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCPn

TCPn : Set the timing to change output of GPWMn.
bits : 0 - 15 (16 bit)
access : read-write


GPWM8DHRDAT

GPWM8 High Resolutio8 Output Shift Amou8t Setti8g Register
address_offset : 0x818 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8DHRDAT GPWM8DHRDAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HRSTIMn

__reserve0 : 0 is always read out.
bits : 0 - 10 (11 bit)
access : read

HRSTIMn : Set high resolution output shift amount
bits : 11 - 26 (16 bit)
access : read-write


GPWM8DDAT

GPWM8 Output Shift Amou8t Setti8g Register
address_offset : 0x81A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8DDAT GPWM8DDAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STIMn

STIMn : Set GPWMn output shift amount
bits : 0 - 15 (16 bit)
access : read-write


GPWM8DTMCNT

GPWM8 Dead Time Co8trol Register
address_offset : 0x820 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8DTMCNT GPWM8DTMCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTENn ORMDn NORMDn SLFCNTn __reserve0

DTENn : Dead time insertion
bits : 0 - 0 (1 bit)
access : read-write

ORMDn : GPWMn dead time insertion logic
bits : 1 - 2 (2 bit)
access : read-write

NORMDn : NGPWMn dead time insertion logic
bits : 2 - 4 (3 bit)
access : read-write

SLFCNTn : Dead time width automatic control enable
bits : 3 - 6 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read


GPWM8DTMSETA

GPWM8 Dead Time Setti8g Register A
address_offset : 0x824 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8DTMSETA GPWM8DTMSETA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTSTAn __reserve0

DTSTAn : Set dead time for GPWMn.
bits : 0 - 9 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM8DTMSETB

GPWM8 Dead Time Setti8g Register B
address_offset : 0x826 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8DTMSETB GPWM8DTMSETB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTSTBn __reserve0

DTSTBn : Set dead time for NGPWMn.
bits : 0 - 9 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM8ADST

GPWM8 Sy8chro8ous Trigger Setti8g Register
address_offset : 0x828 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8ADST GPWM8ADST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PASTn

PASTn : Set the value of starting GPWMn synchronous A/D.
bits : 0 - 15 (16 bit)
access : read-write


GPWM8ADSTSEL

GPWM8 Sy8chro8ous Trigger Polarity Selectio8 Register
address_offset : 0x82A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8ADSTSEL GPWM8ADSTSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PASTUPn PASTDNn __reserve0

PASTUPn : Set the timing of synchronous trigger generation.
bits : 0 - 0 (1 bit)
access : read-write

PASTDNn : Set the timing of synchronous trigger generation.
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM8ADBC

GPWM8 Sy8chro8ous Bi8ary Cou8ter Read Register
address_offset : 0x82C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8ADBC GPWM8ADBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADBCn

ADBCn : Read the binary count for starting GPWMn synchronous A/D.
bits : 0 - 15 (16 bit)
access : read


GPWM8IRQCNT

GPWM8 UDF/OVF I8terrupt Output Co8trol Register
address_offset : 0x830 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8IRQCNT GPWM8IRQCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDFCNTn UDFSCNTn OVFCNTn OVFSCNTn

UDFCNTn : Number of times setting for GPWMn underflow interrupt (Second time or later)
bits : 0 - 3 (4 bit)
access : read-write

UDFSCNTn : Number of times setting for GPWMn underflow interrupt (First time)
bits : 4 - 11 (8 bit)
access : read-write

OVFCNTn : Number of times setting for GPWMn overflow interrupt (Second time or later)
bits : 8 - 19 (12 bit)
access : read-write

OVFSCNTn : Number of times setting for GPWMn overflow interrupt (First time)
bits : 12 - 27 (16 bit)
access : read-write


GPWM8ADIRQCNT

GPWM8 A/D Start I8terrupt Output Co8trol Register
address_offset : 0x834 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8ADIRQCNT GPWM8ADIRQCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASTCNTn ASTSCNTn __reserve0

ASTCNTn : Number of times setting for GPWMn synchronous A/D start interrupt (Second time or later)
bits : 0 - 3 (4 bit)
access : read-write

ASTSCNTn : Number of times setting for GPWMn synchronous A/D start interrupt (First time)
bits : 4 - 11 (8 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read


GPWM8OFF

GPWM8 Pi8 Protectio8 Co8trol Register
address_offset : 0x838 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8OFF GPWM8OFF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTENn __reserve0 PRT PRTN __reserve1

OUTENn : GPWMn pin output enable
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 4 (4 bit)
access : read

PRT : GPWMOUTn output pin protection function
bits : 4 - 9 (6 bit)
access : read-write

PRTN : NGPWMOUTn output pin protection function
bits : 6 - 13 (8 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read


GPWM8OFFIRQA

GPWM8 Pi8 Protectio8 Factor Selectio8 Register A
address_offset : 0x83C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8OFFIRQA GPWM8OFFIRQA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ08ENn IRQ09ENn IRQ14ENn IRQ15ENn IRQ18ENn IRQ19ENn NMIENn AD0ERRAENn AD0ERRBENn AD1ERRAENn AD1ERRBENn AD2ERRAENn AD2ERRBENn __reserve0

IRQ00ENn : Protection factor control by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Protection factor control by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ08ENn : Protection factor control by External Interrupt 8
bits : 2 - 4 (3 bit)
access : read-write

IRQ09ENn : Protection factor control by External Interrupt 9
bits : 3 - 6 (4 bit)
access : read-write

IRQ14ENn : Protection factor control by External Interrupt 14
bits : 4 - 8 (5 bit)
access : read-write

IRQ15ENn : Protection factor control by External Interrupt 15
bits : 5 - 10 (6 bit)
access : read-write

IRQ18ENn : Protection factor control by External Interrupt 18
bits : 6 - 12 (7 bit)
access : read-write

IRQ19ENn : Protection factor control by External Interrupt 19
bits : 7 - 14 (8 bit)
access : read-write

NMIENn : Protection factor control by NMI
bits : 8 - 16 (9 bit)
access : read-write

AD0ERRAENn : Protection factor control by A/D0 Conversion Error Detection
bits : 9 - 18 (10 bit)
access : read-write

AD0ERRBENn : Protection factor control by A/D0 Conversion Error Detection B
bits : 10 - 20 (11 bit)
access : read-write

AD1ERRAENn : Protection factor control by A/D1 Conversion Error Detection
bits : 11 - 22 (12 bit)
access : read-write

AD1ERRBENn : Protection factor control by A/D1 Conversion Error Detection B
bits : 12 - 24 (13 bit)
access : read-write

AD2ERRAENn : Protection factor control by A/D2 Conversion Error Detection
bits : 13 - 26 (14 bit)
access : read-write

AD2ERRBENn : Protection factor control by A/D2 Conversion Error Detection B
bits : 14 - 28 (15 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 15 - 30 (16 bit)
access : read


GPWM8OFFIRQB

GPWM8 Pi8 Protectio8 Factor Selectio8 Register B
address_offset : 0x83E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8OFFIRQB GPWM8OFFIRQB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Protection factor control by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Protection factor control by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Protection factor control by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Protection factor control by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Protection factor control by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Protection factor control by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Protection factor control by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Protection factor control by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Protection factor control by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Protection factor control by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM8PULSECNT

GPWM8 Pulse Co8trol Register
address_offset : 0x840 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8PULSECNT GPWM8PULSECNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTCTENn DTACTSELn DTCTASELn DTCTBSELn DTOVFRETn DTUDFRETn PRCTENn PRACTSELn PRRETSELn __reserve0

DTCTENn : Duty Cut enable
bits : 0 - 0 (1 bit)
access : read-write

DTACTSELn : Duty cut start factor polarity selection
bits : 1 - 2 (2 bit)
access : read-write

DTCTASELn : GPWMn operation selection when the duty cut
bits : 2 - 5 (4 bit)
access : read-write

DTCTBSELn : NGPWMn operation selection when the duty cut
bits : 4 - 9 (6 bit)
access : read-write

DTOVFRETn : Control of the return of duty cut by the overflow
bits : 6 - 12 (7 bit)
access : read-write

DTUDFRETn : Control of the return of duty cut by the underflow
bits : 7 - 14 (8 bit)
access : read-write

PRCTENn : Period Cut enable
bits : 8 - 16 (9 bit)
access : read-write

PRACTSELn : Period cut start factor polarity selection
bits : 9 - 18 (10 bit)
access : read-write

PRRETSELn : Period cut operation selection
bits : 10 - 20 (11 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 11 - 26 (16 bit)
access : read


GPWM8PULSEST

GPWM8 Pulse Co8trol Status Register
address_offset : 0x844 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8PULSEST GPWM8PULSEST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTCTSTn PRCTSTn __reserve0

DTCTSTn : Duty cut state
bits : 0 - 0 (1 bit)
access : read-write

PRCTSTn : Period cut state
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM8DUTYTRGA

GPWM8 Duty Cut Factor Selectio8 Register A
address_offset : 0x848 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8DUTYTRGA GPWM8DUTYTRGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ02ENn IRQ03ENn IRQ04ENn IRQ05ENn IRQ06ENn IRQ07ENn IRQ08ENn IRQ09ENn IRQ10ENn IRQ11ENn IRQ12ENn IRQ13ENn IRQ14ENn IRQ15ENn

IRQ00ENn : Duty cut start factor selection by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Duty cut start factor selection by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ02ENn : Duty cut start factor selection by External Interrupt 2
bits : 2 - 4 (3 bit)
access : read-write

IRQ03ENn : Duty cut start factor selection by External Interrupt 3
bits : 3 - 6 (4 bit)
access : read-write

IRQ04ENn : Duty cut start factor selection by External Interrupt 4
bits : 4 - 8 (5 bit)
access : read-write

IRQ05ENn : Duty cut start factor selection by External Interrupt 5
bits : 5 - 10 (6 bit)
access : read-write

IRQ06ENn : Duty cut start factor selection by External Interrupt 6
bits : 6 - 12 (7 bit)
access : read-write

IRQ07ENn : Duty cut start factor selection by External Interrupt 7
bits : 7 - 14 (8 bit)
access : read-write

IRQ08ENn : Duty cut start factor selection by External Interrupt 8
bits : 8 - 16 (9 bit)
access : read-write

IRQ09ENn : Duty cut start factor selection by External Interrupt 9
bits : 9 - 18 (10 bit)
access : read-write

IRQ10ENn : Duty cut start factor selection by External Interrupt 10
bits : 10 - 20 (11 bit)
access : read-write

IRQ11ENn : Duty cut start factor selection by External Interrupt 11
bits : 11 - 22 (12 bit)
access : read-write

IRQ12ENn : Duty cut start factor selection by External Interrupt 12
bits : 12 - 24 (13 bit)
access : read-write

IRQ13ENn : Duty cut start factor selection by External Interrupt 13
bits : 13 - 26 (14 bit)
access : read-write

IRQ14ENn : Duty cut start factor selection by External Interrupt 14
bits : 14 - 28 (15 bit)
access : read-write

IRQ15ENn : Duty cut start factor selection by External Interrupt 15
bits : 15 - 30 (16 bit)
access : read-write


GPWM8DUTYTRGB

GPWM8 Duty Cut Factor Selectio8 Register B
address_offset : 0x84A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8DUTYTRGB GPWM8DUTYTRGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Duty cut start factor selection by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Duty cut start factor selection by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Duty cut start factor selection by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Duty cut start factor selection by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Duty cut start factor selection by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Duty cut start factor selection by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Duty cut start factor selection by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Duty cut start factor selection by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Duty cut start factor selection by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Duty cut start factor selection by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM8PERITRGA

GPWM8 Period Cut Factor Selectio8 Register A
address_offset : 0x84C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8PERITRGA GPWM8PERITRGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ02ENn IRQ03ENn IRQ04ENn IRQ05ENn IRQ06ENn IRQ07ENn IRQ08ENn IRQ09ENn IRQ10ENn IRQ11ENn IRQ12ENn IRQ13ENn IRQ14ENn IRQ15ENn

IRQ00ENn : Period cut start factor selection by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Period cut start factor selection by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ02ENn : Period cut start factor selection by External Interrupt 2
bits : 2 - 4 (3 bit)
access : read-write

IRQ03ENn : Period cut start factor selection by External Interrupt 3
bits : 3 - 6 (4 bit)
access : read-write

IRQ04ENn : Period cut start factor selection by External Interrupt 4
bits : 4 - 8 (5 bit)
access : read-write

IRQ05ENn : Period cut start factor selection by External Interrupt 5
bits : 5 - 10 (6 bit)
access : read-write

IRQ06ENn : Period cut start factor selection by External Interrupt 6
bits : 6 - 12 (7 bit)
access : read-write

IRQ07ENn : Period cut start factor selection by External Interrupt 7
bits : 7 - 14 (8 bit)
access : read-write

IRQ08ENn : Period cut start factor selection by External Interrupt 8
bits : 8 - 16 (9 bit)
access : read-write

IRQ09ENn : Period cut start factor selection by External Interrupt 9
bits : 9 - 18 (10 bit)
access : read-write

IRQ10ENn : Period cut start factor selection by External Interrupt 10
bits : 10 - 20 (11 bit)
access : read-write

IRQ11ENn : Period cut start factor selection by External Interrupt 11
bits : 11 - 22 (12 bit)
access : read-write

IRQ12ENn : Period cut start factor selection by External Interrupt 12
bits : 12 - 24 (13 bit)
access : read-write

IRQ13ENn : Period cut start factor selection by External Interrupt 13
bits : 13 - 26 (14 bit)
access : read-write

IRQ14ENn : Period cut start factor selection by External Interrupt 14
bits : 14 - 28 (15 bit)
access : read-write

IRQ15ENn : Period cut start factor selection by External Interrupt 15
bits : 15 - 30 (16 bit)
access : read-write


GPWM8PERITRGB

GPWM8 Period Cut Factor Selectio8 Register B
address_offset : 0x84E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8PERITRGB GPWM8PERITRGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Period cut start factor selection by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Period cut start factor selection by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Period cut start factor selection by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Period cut start factor selection by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Period cut start factor selection by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Period cut start factor selection by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Period cut start factor selection by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Period cut start factor selection by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Period cut start factor selection by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Period cut start factor selection by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM8DBUPDATE

GPWM8 Double Buffer Updati8g E8able Register
address_offset : 0x850 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM8DBUPDATE GPWM8DBUPDATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUPn __reserve0

DUPn : Double buffer updating enable
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read


GPWM9MD

GPWM9 Mode Register
address_offset : 0x900 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM9MD GPWM9MD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAVEMDn TCENn HRSELn HRPRENn SYNCENn DUPENn PCRBENn PCRAENn SDSELBn SDSELAn __reserve0 CLKSELn __reserve1 SFTENn SDIRn __reserve2

WAVEMDn : PWM waveform mode select
bits : 0 - 0 (1 bit)
access : read-write

TCENn : PWM Operation control
bits : 1 - 2 (2 bit)
access : read-write

HRSELn : High resolution output function enable
bits : 2 - 4 (3 bit)
access : read-write

HRPRENn : High resolution cycle function enable
bits : 3 - 6 (4 bit)
access : read-write

SYNCENn : Synchronous start function (MFA) enable
bits : 4 - 8 (5 bit)
access : read-write

DUPENn : Double buffer updating enable register selection
bits : 5 - 10 (6 bit)
access : read-write

PCRBENn : Double buffer load timing enable (GPWMnBC overflow)
bits : 6 - 12 (7 bit)
access : read-write

PCRAENn : Double buffer load timing enable (GPWMnBC underflow)
bits : 7 - 14 (8 bit)
access : read-write

SDSELBn : GPWMnSEL buffer mode
bits : 8 - 16 (9 bit)
access : read-write

SDSELAn : GPWMnOUTMD buffer mode
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 20 (11 bit)
access : read

CLKSELn : Count clock selection
bits : 11 - 22 (12 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 12 - 24 (13 bit)
access : read

SFTENn : PWM output shift function enable
bits : 13 - 26 (14 bit)
access : read-write

SDIRn : Shift direction control
bits : 14 - 28 (15 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 15 - 30 (16 bit)
access : read


GPWM9OUTMD

GPWM9 Output Polarity Co9trol Register
address_offset : 0x904 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM9OUTMD GPWM9OUTMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PXDTn PXDTNn __reserve0

PXDTn : GPWMn output polarity
bits : 0 - 0 (1 bit)
access : read-write

PXDTNn : NGPWMn output polarity
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM9SEL

GPWM9 Output Co9trol Register
address_offset : 0x908 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM9SEL GPWM9SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTLVn OTLVNn PSELn PSELNn __reserve0

OTLVn : GPWMn High/Low-level output
bits : 0 - 0 (1 bit)
access : read-write

OTLVNn : NGPWMn High/Low-level output
bits : 1 - 2 (2 bit)
access : read-write

PSELn : GPWMn output sources
bits : 2 - 4 (3 bit)
access : read-write

PSELNn : NGPWMn output sources
bits : 3 - 6 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read


GPWM9BC

GPWM9BC Value Read Register
address_offset : 0x90C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM9BC GPWM9BC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCn

BCn : Read the binary counter value of GPWMn
bits : 0 - 15 (16 bit)
access : read


GPWM9BCSTR

GPWM9BC Status Read Register
address_offset : 0x90E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM9BCSTR GPWM9BCSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRn __reserve0

STRn : GPWMn binary counter's counting status read
bits : 0 - 0 (1 bit)
access : read

__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read


GPWM9SET

GPWM9 Cycle Setti9g Register
address_offset : 0x912 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM9SET GPWM9SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETn

SETn : Set the cycle to the GPWMn 16-bit counter.
bits : 0 - 15 (16 bit)
access : read-write


GPWM9TCMP

GPWM9 Phase Compariso9 Setti9g Register
address_offset : 0x916 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM9TCMP GPWM9TCMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCPn

TCPn : Set the timing to change output of GPWMn.
bits : 0 - 15 (16 bit)
access : read-write


GPWM9DDAT

GPWM9 Output Shift Amou9t Setti9g Register
address_offset : 0x91A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM9DDAT GPWM9DDAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STIMn

STIMn : Set GPWMn output shift amount
bits : 0 - 15 (16 bit)
access : read-write


GPWM9DTMCNT

GPWM9 Dead Time Co9trol Register
address_offset : 0x920 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM9DTMCNT GPWM9DTMCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTENn ORMDn NORMDn SLFCNTn __reserve0

DTENn : Dead time insertion
bits : 0 - 0 (1 bit)
access : read-write

ORMDn : GPWMn dead time insertion logic
bits : 1 - 2 (2 bit)
access : read-write

NORMDn : NGPWMn dead time insertion logic
bits : 2 - 4 (3 bit)
access : read-write

SLFCNTn : Dead time width automatic control enable
bits : 3 - 6 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read


GPWM9DTMSETA

GPWM9 Dead Time Setti9g Register A
address_offset : 0x924 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM9DTMSETA GPWM9DTMSETA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTSTAn __reserve0

DTSTAn : Set dead time for GPWMn.
bits : 0 - 9 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM9DTMSETB

GPWM9 Dead Time Setti9g Register B
address_offset : 0x926 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM9DTMSETB GPWM9DTMSETB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTSTBn __reserve0

DTSTBn : Set dead time for NGPWMn.
bits : 0 - 9 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM9ADST

GPWM9 Sy9chro9ous Trigger Setti9g Register
address_offset : 0x928 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM9ADST GPWM9ADST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PASTn

PASTn : Set the value of starting GPWMn synchronous A/D.
bits : 0 - 15 (16 bit)
access : read-write


GPWM9ADSTSEL

GPWM9 Sy9chro9ous Trigger Polarity Selectio9 Register
address_offset : 0x92A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM9ADSTSEL GPWM9ADSTSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PASTUPn PASTDNn __reserve0

PASTUPn : Set the timing of synchronous trigger generation.
bits : 0 - 0 (1 bit)
access : read-write

PASTDNn : Set the timing of synchronous trigger generation.
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM9ADBC

GPWM9 Sy9chro9ous Bi9ary Cou9ter Read Register
address_offset : 0x92C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM9ADBC GPWM9ADBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADBCn

ADBCn : Read the binary count for starting GPWMn synchronous A/D.
bits : 0 - 15 (16 bit)
access : read


GPWM9IRQCNT

GPWM9 UDF/OVF I9terrupt Output Co9trol Register
address_offset : 0x930 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM9IRQCNT GPWM9IRQCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDFCNTn UDFSCNTn OVFCNTn OVFSCNTn

UDFCNTn : Number of times setting for GPWMn underflow interrupt (Second time or later)
bits : 0 - 3 (4 bit)
access : read-write

UDFSCNTn : Number of times setting for GPWMn underflow interrupt (First time)
bits : 4 - 11 (8 bit)
access : read-write

OVFCNTn : Number of times setting for GPWMn overflow interrupt (Second time or later)
bits : 8 - 19 (12 bit)
access : read-write

OVFSCNTn : Number of times setting for GPWMn overflow interrupt (First time)
bits : 12 - 27 (16 bit)
access : read-write


GPWM9ADIRQCNT

GPWM9 A/D Start I9terrupt Output Co9trol Register
address_offset : 0x934 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM9ADIRQCNT GPWM9ADIRQCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASTCNTn ASTSCNTn __reserve0

ASTCNTn : Number of times setting for GPWMn synchronous A/D start interrupt (Second time or later)
bits : 0 - 3 (4 bit)
access : read-write

ASTSCNTn : Number of times setting for GPWMn synchronous A/D start interrupt (First time)
bits : 4 - 11 (8 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read


GPWM9OFF

GPWM9 Pi9 Protectio9 Co9trol Register
address_offset : 0x938 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM9OFF GPWM9OFF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTENn __reserve0 PRT PRTN __reserve1

OUTENn : GPWMn pin output enable
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 4 (4 bit)
access : read

PRT : GPWMOUTn output pin protection function
bits : 4 - 9 (6 bit)
access : read-write

PRTN : NGPWMOUTn output pin protection function
bits : 6 - 13 (8 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read


GPWM9OFFIRQA

GPWM9 Pi9 Protectio9 Factor Selectio9 Register A
address_offset : 0x93C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM9OFFIRQA GPWM9OFFIRQA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ08ENn IRQ09ENn IRQ14ENn IRQ15ENn IRQ18ENn IRQ19ENn NMIENn AD0ERRAENn AD0ERRBENn AD1ERRAENn AD1ERRBENn AD2ERRAENn AD2ERRBENn __reserve0

IRQ00ENn : Protection factor control by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Protection factor control by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ08ENn : Protection factor control by External Interrupt 8
bits : 2 - 4 (3 bit)
access : read-write

IRQ09ENn : Protection factor control by External Interrupt 9
bits : 3 - 6 (4 bit)
access : read-write

IRQ14ENn : Protection factor control by External Interrupt 14
bits : 4 - 8 (5 bit)
access : read-write

IRQ15ENn : Protection factor control by External Interrupt 15
bits : 5 - 10 (6 bit)
access : read-write

IRQ18ENn : Protection factor control by External Interrupt 18
bits : 6 - 12 (7 bit)
access : read-write

IRQ19ENn : Protection factor control by External Interrupt 19
bits : 7 - 14 (8 bit)
access : read-write

NMIENn : Protection factor control by NMI
bits : 8 - 16 (9 bit)
access : read-write

AD0ERRAENn : Protection factor control by A/D0 Conversion Error Detection
bits : 9 - 18 (10 bit)
access : read-write

AD0ERRBENn : Protection factor control by A/D0 Conversion Error Detection B
bits : 10 - 20 (11 bit)
access : read-write

AD1ERRAENn : Protection factor control by A/D1 Conversion Error Detection
bits : 11 - 22 (12 bit)
access : read-write

AD1ERRBENn : Protection factor control by A/D1 Conversion Error Detection B
bits : 12 - 24 (13 bit)
access : read-write

AD2ERRAENn : Protection factor control by A/D2 Conversion Error Detection
bits : 13 - 26 (14 bit)
access : read-write

AD2ERRBENn : Protection factor control by A/D2 Conversion Error Detection B
bits : 14 - 28 (15 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 15 - 30 (16 bit)
access : read


GPWM9OFFIRQB

GPWM9 Pi9 Protectio9 Factor Selectio9 Register B
address_offset : 0x93E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM9OFFIRQB GPWM9OFFIRQB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Protection factor control by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Protection factor control by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Protection factor control by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Protection factor control by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Protection factor control by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Protection factor control by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Protection factor control by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Protection factor control by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Protection factor control by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Protection factor control by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM9PULSECNT

GPWM9 Pulse Co9trol Register
address_offset : 0x940 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM9PULSECNT GPWM9PULSECNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTCTENn DTACTSELn DTCTASELn DTCTBSELn DTOVFRETn DTUDFRETn PRCTENn PRACTSELn PRRETSELn __reserve0

DTCTENn : Duty Cut enable
bits : 0 - 0 (1 bit)
access : read-write

DTACTSELn : Duty cut start factor polarity selection
bits : 1 - 2 (2 bit)
access : read-write

DTCTASELn : GPWMn operation selection when the duty cut
bits : 2 - 5 (4 bit)
access : read-write

DTCTBSELn : NGPWMn operation selection when the duty cut
bits : 4 - 9 (6 bit)
access : read-write

DTOVFRETn : Control of the return of duty cut by the overflow
bits : 6 - 12 (7 bit)
access : read-write

DTUDFRETn : Control of the return of duty cut by the underflow
bits : 7 - 14 (8 bit)
access : read-write

PRCTENn : Period Cut enable
bits : 8 - 16 (9 bit)
access : read-write

PRACTSELn : Period cut start factor polarity selection
bits : 9 - 18 (10 bit)
access : read-write

PRRETSELn : Period cut operation selection
bits : 10 - 20 (11 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 11 - 26 (16 bit)
access : read


GPWM9PULSEST

GPWM9 Pulse Co9trol Status Register
address_offset : 0x944 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM9PULSEST GPWM9PULSEST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTCTSTn PRCTSTn __reserve0

DTCTSTn : Duty cut state
bits : 0 - 0 (1 bit)
access : read-write

PRCTSTn : Period cut state
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read


GPWM9DUTYTRGA

GPWM9 Duty Cut Factor Selectio9 Register A
address_offset : 0x948 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM9DUTYTRGA GPWM9DUTYTRGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ02ENn IRQ03ENn IRQ04ENn IRQ05ENn IRQ06ENn IRQ07ENn IRQ08ENn IRQ09ENn IRQ10ENn IRQ11ENn IRQ12ENn IRQ13ENn IRQ14ENn IRQ15ENn

IRQ00ENn : Duty cut start factor selection by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Duty cut start factor selection by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ02ENn : Duty cut start factor selection by External Interrupt 2
bits : 2 - 4 (3 bit)
access : read-write

IRQ03ENn : Duty cut start factor selection by External Interrupt 3
bits : 3 - 6 (4 bit)
access : read-write

IRQ04ENn : Duty cut start factor selection by External Interrupt 4
bits : 4 - 8 (5 bit)
access : read-write

IRQ05ENn : Duty cut start factor selection by External Interrupt 5
bits : 5 - 10 (6 bit)
access : read-write

IRQ06ENn : Duty cut start factor selection by External Interrupt 6
bits : 6 - 12 (7 bit)
access : read-write

IRQ07ENn : Duty cut start factor selection by External Interrupt 7
bits : 7 - 14 (8 bit)
access : read-write

IRQ08ENn : Duty cut start factor selection by External Interrupt 8
bits : 8 - 16 (9 bit)
access : read-write

IRQ09ENn : Duty cut start factor selection by External Interrupt 9
bits : 9 - 18 (10 bit)
access : read-write

IRQ10ENn : Duty cut start factor selection by External Interrupt 10
bits : 10 - 20 (11 bit)
access : read-write

IRQ11ENn : Duty cut start factor selection by External Interrupt 11
bits : 11 - 22 (12 bit)
access : read-write

IRQ12ENn : Duty cut start factor selection by External Interrupt 12
bits : 12 - 24 (13 bit)
access : read-write

IRQ13ENn : Duty cut start factor selection by External Interrupt 13
bits : 13 - 26 (14 bit)
access : read-write

IRQ14ENn : Duty cut start factor selection by External Interrupt 14
bits : 14 - 28 (15 bit)
access : read-write

IRQ15ENn : Duty cut start factor selection by External Interrupt 15
bits : 15 - 30 (16 bit)
access : read-write


GPWM9DUTYTRGB

GPWM9 Duty Cut Factor Selectio9 Register B
address_offset : 0x94A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM9DUTYTRGB GPWM9DUTYTRGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Duty cut start factor selection by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Duty cut start factor selection by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Duty cut start factor selection by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Duty cut start factor selection by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Duty cut start factor selection by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Duty cut start factor selection by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Duty cut start factor selection by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Duty cut start factor selection by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Duty cut start factor selection by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Duty cut start factor selection by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM9PERITRGA

GPWM9 Period Cut Factor Selectio9 Register A
address_offset : 0x94C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM9PERITRGA GPWM9PERITRGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ00ENn IRQ01ENn IRQ02ENn IRQ03ENn IRQ04ENn IRQ05ENn IRQ06ENn IRQ07ENn IRQ08ENn IRQ09ENn IRQ10ENn IRQ11ENn IRQ12ENn IRQ13ENn IRQ14ENn IRQ15ENn

IRQ00ENn : Period cut start factor selection by External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ01ENn : Period cut start factor selection by External Interrupt 1
bits : 1 - 2 (2 bit)
access : read-write

IRQ02ENn : Period cut start factor selection by External Interrupt 2
bits : 2 - 4 (3 bit)
access : read-write

IRQ03ENn : Period cut start factor selection by External Interrupt 3
bits : 3 - 6 (4 bit)
access : read-write

IRQ04ENn : Period cut start factor selection by External Interrupt 4
bits : 4 - 8 (5 bit)
access : read-write

IRQ05ENn : Period cut start factor selection by External Interrupt 5
bits : 5 - 10 (6 bit)
access : read-write

IRQ06ENn : Period cut start factor selection by External Interrupt 6
bits : 6 - 12 (7 bit)
access : read-write

IRQ07ENn : Period cut start factor selection by External Interrupt 7
bits : 7 - 14 (8 bit)
access : read-write

IRQ08ENn : Period cut start factor selection by External Interrupt 8
bits : 8 - 16 (9 bit)
access : read-write

IRQ09ENn : Period cut start factor selection by External Interrupt 9
bits : 9 - 18 (10 bit)
access : read-write

IRQ10ENn : Period cut start factor selection by External Interrupt 10
bits : 10 - 20 (11 bit)
access : read-write

IRQ11ENn : Period cut start factor selection by External Interrupt 11
bits : 11 - 22 (12 bit)
access : read-write

IRQ12ENn : Period cut start factor selection by External Interrupt 12
bits : 12 - 24 (13 bit)
access : read-write

IRQ13ENn : Period cut start factor selection by External Interrupt 13
bits : 13 - 26 (14 bit)
access : read-write

IRQ14ENn : Period cut start factor selection by External Interrupt 14
bits : 14 - 28 (15 bit)
access : read-write

IRQ15ENn : Period cut start factor selection by External Interrupt 15
bits : 15 - 30 (16 bit)
access : read-write


GPWM9PERITRGB

GPWM9 Period Cut Factor Selectio9 Register B
address_offset : 0x94E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM9PERITRGB GPWM9PERITRGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP00ENn CMP01ENn CMP10ENn CMP11ENn CMP20ENn CMP21ENn CMP30ENn CMP31ENn CMP40ENn CMP41ENn __reserve0

CMP00ENn : Period cut start factor selection by Comparator 00 Detection
bits : 0 - 0 (1 bit)
access : read-write

CMP01ENn : Period cut start factor selection by Comparator 01 Detection
bits : 1 - 2 (2 bit)
access : read-write

CMP10ENn : Period cut start factor selection by Comparator 10 Detection
bits : 2 - 4 (3 bit)
access : read-write

CMP11ENn : Period cut start factor selection by Comparator 11 Detection
bits : 3 - 6 (4 bit)
access : read-write

CMP20ENn : Period cut start factor selection by Comparator 20 Detection
bits : 4 - 8 (5 bit)
access : read-write

CMP21ENn : Period cut start factor selection by Comparator 21 Detection
bits : 5 - 10 (6 bit)
access : read-write

CMP30ENn : Period cut start factor selection by Comparator 30 Detection
bits : 6 - 12 (7 bit)
access : read-write

CMP31ENn : Period cut start factor selection by Comparator 31 Detection
bits : 7 - 14 (8 bit)
access : read-write

CMP40ENn : Period cut start factor selection by Comparator 40 Detection
bits : 8 - 16 (9 bit)
access : read-write

CMP41ENn : Period cut start factor selection by Comparator 41 Detection
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read


GPWM9DBUPDATE

GPWM9 Double Buffer Updati9g E9able Register
address_offset : 0x950 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM9DBUPDATE GPWM9DBUPDATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUPn __reserve0

DUPn : Double buffer updating enable
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read


GPWM0BC

GPWM0BC Value Read Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0BC GPWM0BC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCn

BCn : Read the binary counter value of GPWMn
bits : 0 - 15 (16 bit)
access : read


GPWM0BCSTR

GPWM0BC Status Read Register
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWM0BCSTR GPWM0BCSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRn __reserve0

STRn : GPWMn binary counter's counting status read
bits : 0 - 0 (1 bit)
access : read

__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read


GPWMC_DBUPALL

GPWM Double Buffer Collective Updating Enable Register
address_offset : 0xF00 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWMC_DBUPALL GPWMC_DBUPALL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUP0 DUP1 DUP2 DUP3 DUP4 DUP5 DUP6 DUP7 DUP8 DUP9 __reserve0

DUP0 : GPWM0 double buffer updating enable
bits : 0 - 0 (1 bit)
access : read-write

DUP1 : GPWM1 double buffer updating enable
bits : 1 - 2 (2 bit)
access : read-write

DUP2 : GPWM2 double buffer updating enable
bits : 2 - 4 (3 bit)
access : read-write

DUP3 : GPWM3 double buffer updating enable
bits : 3 - 6 (4 bit)
access : read-write

DUP4 : GPWM4 double buffer updating enable
bits : 4 - 8 (5 bit)
access : read-write

DUP5 : GPWM5 double buffer updating enable
bits : 5 - 10 (6 bit)
access : read-write

DUP6 : GPWM6 double buffer updating enable
bits : 6 - 12 (7 bit)
access : read-write

DUP7 : GPWM7 double buffer updating enable
bits : 7 - 14 (8 bit)
access : read-write

DUP8 : GPWM8 double buffer updating enable
bits : 8 - 16 (9 bit)
access : read-write

DUP9 : GPWM9 double buffer updating enable
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


GPWMC_PINSEL

3-Phase Output Pin Output Order Register
address_offset : 0xF04 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

GPWMC_PINSEL GPWMC_PINSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TPWMPINSELA TPWMPINSELB TPWMPINSELC __reserve0

TPWMPINSELA : Pin output order change
bits : 0 - 0 (1 bit)
access : read-write

TPWMPINSELB : Pin output order change
bits : 1 - 2 (2 bit)
access : read-write

TPWMPINSELC : Pin output order change
bits : 2 - 4 (3 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read



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