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SIF_0__6

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xF1C byte (0x0)
mem_usage : registers
protection :

Registers

SC0MD0

SC0MD1

SC0RB

SC6MD0

SC6MD1

SC6MD2

SC6MD3

SC6STR

SC6RB

SC0TB

SC6TB

SC1MD0

SC1MD1

SC1MD2

SC1MD3

SC1STR

SC1RB

SC1TB

SC0MD2

SC0MD3

SC3MD0

SC3MD1

SC3MD2

SC3MD3

SC3MD4

SC3STR

SC3RB

SC3TB

SC0AD0

SC4MD0

SC4MD1

SC4MD2

SC4MD3

SC4MD4

SC4STR

SC4RB

SC4TB

SC5MD0

SC5MD1

SC5MD2

SC5MD3

SC5MD4

SC5STR

SC5RB

SC5TB

SC0STR0

SCINTSEL

SC0STR1

BRTM_S_MODE

BRTM_S_EN

BRTM_S01_CK

BRTM_S23_CK

BRTM_S45_CK

BRTM_S6_CK

BRTM_S0_OC

BRTM_S1_OC

BRTM_S3_OC

BRTM_S4_OC

BRTM_S5_OC

BRTM_S6_OC


SC0MD0

Serial 0 Mode Register 0
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC0MD0 SC0MD0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LNG STE DIR DEM SSC CE1

LNG : Transfer bit count settings (*2)
bits : 0 - 2 (3 bit)
access : read-write

STE : Start condition selection [Clock-Synchronous/IIC Master communication](*1)
bits : 3 - 6 (4 bit)
access : read-write

DIR : Transfer first bit selection
bits : 4 - 8 (5 bit)
access : read-write

DEM : Operation after communication error detection selection [IIC Slave communication]
bits : 5 - 10 (6 bit)
access : read-write

SSC : Clock source selection of internal circuit operation clock [Clock-Synchronous]
bits : 6 - 12 (7 bit)
access : read-write

CE1 : Clock polarity selection [Clock-Synchronous]
bits : 7 - 14 (8 bit)
access : read-write


SC0MD1

Serial 0 Mode Register 1
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC0MD1 SC0MD1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CTM __reserve0 MST __reserve1 SBOS SBIS SBTS IOM

CTM : Continuous communication mode selection [Clock-Synchronous]
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 2 (2 bit)
access : read

MST : [Clock-Synchronous]
bits : 2 - 4 (3 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 3 - 6 (4 bit)
access : read

SBOS : SBOn(SDAn) pin output control
bits : 4 - 8 (5 bit)
access : read-write

SBIS : SBIn/SBOn(SDAn) pin input control
bits : 5 - 10 (6 bit)
access : read-write

SBTS : SBTn(SCLn) pin control
bits : 6 - 12 (7 bit)
access : read-write

IOM : Data input pin selection
bits : 7 - 14 (8 bit)
access : read-write


SC0RB

Serial 0 Reception Data Buffer Register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC0RB SC0RB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB

RB : Reception data is read out.
bits : 0 - 7 (8 bit)
access : read


SC6MD0

Serial 6 Mode Register 0
address_offset : 0x100 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC6MD0 SC6MD0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LNG STE DIR CTM SSC CE1

LNG : Transfer bit count [Clock-Synchronous] (*2)
bits : 0 - 2 (3 bit)
access : read-write

STE : Start condition selection [Clock-Synchronous] (*1)
bits : 3 - 6 (4 bit)
access : read-write

DIR : Transfer first bit selection
bits : 4 - 8 (5 bit)
access : read-write

CTM : Continuous communication mode selection [Clock-Synchronous]
bits : 5 - 10 (6 bit)
access : read-write

SSC : Clock source selection as operation clock [Clock-Synchronous]
bits : 6 - 12 (7 bit)
access : read-write

CE1 : Clock polarity selection [Clock-Synchronous]
bits : 7 - 14 (8 bit)
access : read-write


SC6MD1

Serial 6 Mode Register 1
address_offset : 0x101 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC6MD1 SC6MD1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD DIV MST CKM SBOS SBIS SBTS IOM

CMD : Communication mode selection
bits : 0 - 0 (1 bit)
access : read-write

DIV : Division value selection of transfer clock
bits : 1 - 2 (2 bit)
access : read-write

MST : Master/salve communication selection [Clock-Synchronous]
bits : 2 - 4 (3 bit)
access : read-write

CKM : Division selection of transfer clock [Clock-Synchronous]
bits : 3 - 6 (4 bit)
access : read-write

SBOS : SBOn(TXDn) pin output control
bits : 4 - 8 (5 bit)
access : read-write

SBIS : SBIn(RXDn)/SBOn(TXDn) pin input control
bits : 5 - 10 (6 bit)
access : read-write

SBTS : SBTn pin control
bits : 6 - 12 (7 bit)
access : read-write

IOM : Data input pin selection
bits : 7 - 14 (8 bit)
access : read-write


SC6MD2

Serial 6 Mode Register 2
address_offset : 0x104 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC6MD2 SC6MD2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BRKE BRKF __reserve0 NPE PM FM

BRKE : Break transmission control [UART]
bits : 0 - 0 (1 bit)
access : read-write

BRKF : Break reception detection [UART]
bits : 1 - 2 (2 bit)
access : read

__reserve0 : 0 is always read out.
bits : 2 - 4 (3 bit)
access : read

NPE : Parity bit selection [UART]
bits : 3 - 6 (4 bit)
access : read-write

PM : Parity bit function selection [UART]
bits : 4 - 9 (6 bit)
access : read-write

FM : The number of character bit and stop bit selection [UART]
bits : 6 - 13 (8 bit)
access : read-write


SC6MD3

Serial 6 Mode Register 3
address_offset : 0x105 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC6MD3 SC6MD3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 __reserve0 RSRN RSTN FDC

__reserve0 : 0 is always read out.
bits : 0 - 3 (4 bit)
access : read

RSRN : [Clock-Synchronous]
bits : 4 - 8 (5 bit)
access : read-write

RSTN : [Clock-Synchronous]
bits : 5 - 10 (6 bit)
access : read-write

FDC : Output level selection after the final bit transmit (SBOn pin) [Clock-Synchronous]
bits : 6 - 13 (8 bit)
access : read-write


SC6STR

Serial 6 Status Register
address_offset : 0x108 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC6STR SC6STR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ERE ORE PEK FEF REMP TEMP RBSY TBSY

ERE : Reception error detection
bits : 0 - 0 (1 bit)
access : read

ORE : Overrun error detection
bits : 1 - 2 (2 bit)
access : read

PEK : Parity error detection [UART]
bits : 2 - 4 (3 bit)
access : read

FEF : Framing error detection [UART]
bits : 3 - 6 (4 bit)
access : read

REMP : Reception buffer empty
bits : 4 - 8 (5 bit)
access : read

TEMP : Transmission buffer empty
bits : 5 - 10 (6 bit)
access : read

RBSY : Reception busy detection
bits : 6 - 12 (7 bit)
access : read

TBSY : Transmission busy detection
bits : 7 - 14 (8 bit)
access : read


SC6RB

Serial 6 Receptio6 Data Buffer Register
address_offset : 0x10C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC6RB SC6RB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB

RB : Reception data is read out.
bits : 0 - 7 (8 bit)
access : read


SC0TB

Serial 0 Transmission Data Buffer Register
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC0TB SC0TB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TB

TB : Set the transmission data or the dummy data.
bits : 0 - 7 (8 bit)
access : read-write


SC6TB

Serial 6 Tra6smissio6 Data Buffer Register
address_offset : 0x110 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC6TB SC6TB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TB

TB : Set the transmission data or the dummy data.
bits : 0 - 7 (8 bit)
access : read-write


SC1MD0

Serial 1 Mode Register 0
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC1MD0 SC1MD0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LNG STE DIR CTM SSC CE1

LNG : Transfer bit count [Clock-Synchronous] (*2)
bits : 0 - 2 (3 bit)
access : read-write

STE : Start condition selection [Clock-Synchronous] (*1)
bits : 3 - 6 (4 bit)
access : read-write

DIR : Transfer first bit selection
bits : 4 - 8 (5 bit)
access : read-write

CTM : Continuous communication mode selection [Clock-Synchronous]
bits : 5 - 10 (6 bit)
access : read-write

SSC : Clock source selection as operation clock [Clock-Synchronous]
bits : 6 - 12 (7 bit)
access : read-write

CE1 : Clock polarity selection [Clock-Synchronous]
bits : 7 - 14 (8 bit)
access : read-write


SC1MD1

Serial 1 Mode Register 1
address_offset : 0x21 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC1MD1 SC1MD1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD DIV MST CKM SBOS SBIS SBTS IOM

CMD : Communication mode selection
bits : 0 - 0 (1 bit)
access : read-write

DIV : Division value selection of transfer clock
bits : 1 - 2 (2 bit)
access : read-write

MST : Master/salve communication selection [Clock-Synchronous]
bits : 2 - 4 (3 bit)
access : read-write

CKM : Division selection of transfer clock [Clock-Synchronous]
bits : 3 - 6 (4 bit)
access : read-write

SBOS : SBOn(TXDn) pin output control
bits : 4 - 8 (5 bit)
access : read-write

SBIS : SBIn(RXDn)/SBOn(TXDn) pin input control
bits : 5 - 10 (6 bit)
access : read-write

SBTS : SBTn pin control
bits : 6 - 12 (7 bit)
access : read-write

IOM : Data input pin selection
bits : 7 - 14 (8 bit)
access : read-write


SC1MD2

Serial 1 Mode Register 2
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC1MD2 SC1MD2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BRKE BRKF __reserve0 NPE PM FM

BRKE : Break transmission control [UART]
bits : 0 - 0 (1 bit)
access : read-write

BRKF : Break reception detection [UART]
bits : 1 - 2 (2 bit)
access : read

__reserve0 : 0 is always read out.
bits : 2 - 4 (3 bit)
access : read

NPE : Parity bit selection [UART]
bits : 3 - 6 (4 bit)
access : read-write

PM : Parity bit function selection [UART]
bits : 4 - 9 (6 bit)
access : read-write

FM : The number of character bit and stop bit selection [UART]
bits : 6 - 13 (8 bit)
access : read-write


SC1MD3

Serial 1 Mode Register 3
address_offset : 0x25 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC1MD3 SC1MD3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 __reserve0 RSRN RSTN FDC

__reserve0 : 0 is always read out.
bits : 0 - 3 (4 bit)
access : read

RSRN : [Clock-Synchronous]
bits : 4 - 8 (5 bit)
access : read-write

RSTN : [Clock-Synchronous]
bits : 5 - 10 (6 bit)
access : read-write

FDC : Output level selection after the final bit transmit (SBOn pin) [Clock-Synchronous]
bits : 6 - 13 (8 bit)
access : read-write


SC1STR

Serial 1 Status Register
address_offset : 0x28 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC1STR SC1STR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ERE ORE PEK FEF REMP TEMP RBSY TBSY

ERE : Reception error detection
bits : 0 - 0 (1 bit)
access : read

ORE : Overrun error detection
bits : 1 - 2 (2 bit)
access : read

PEK : Parity error detection [UART]
bits : 2 - 4 (3 bit)
access : read

FEF : Framing error detection [UART]
bits : 3 - 6 (4 bit)
access : read

REMP : Reception buffer empty
bits : 4 - 8 (5 bit)
access : read

TEMP : Transmission buffer empty
bits : 5 - 10 (6 bit)
access : read

RBSY : Reception busy detection
bits : 6 - 12 (7 bit)
access : read

TBSY : Transmission busy detection
bits : 7 - 14 (8 bit)
access : read


SC1RB

Serial 1 Receptio1 Data Buffer Register
address_offset : 0x2C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC1RB SC1RB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB

RB : Reception data is read out.
bits : 0 - 7 (8 bit)
access : read


SC1TB

Serial 1 Tra1smissio1 Data Buffer Register
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC1TB SC1TB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TB

TB : Set the transmission data or the dummy data.
bits : 0 - 7 (8 bit)
access : read-write


SC0MD2

Serial 0 Mode Register 2
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC0MD2 SC0MD2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 __reserve0 __reserve1 FDC

__reserve0 : This bit must be set to 0 .
bits : 0 - 3 (4 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 4 - 9 (6 bit)
access : read

FDC : Output level selection after the final bit transmit (SBOn pin) [Clock-Synchronous]
bits : 6 - 13 (8 bit)
access : read-write


SC0MD3

Serial 0 Mode Register 3
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC0MD3 SC0MD3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACKO ACKS CMD REX TMD STPC __reserve0 __reserve1

ACKO : [Data transmission in IIC]
bits : 0 - 0 (1 bit)
access : read-write

ACKS : This bit must be set to 1 . [IIC]
bits : 1 - 2 (2 bit)
access : read-write

CMD : Communication mode selection
bits : 2 - 4 (3 bit)
access : read-write

REX : Transmission/Reception mode selection [IIC Master communication]
bits : 3 - 6 (4 bit)
access : read-write

TMD : Communication speed selection [IIC]
bits : 4 - 8 (5 bit)
access : read-write

STPC : Stop condition generation selection [IIC Master communication]
bits : 5 - 10 (6 bit)
access : read-write

__reserve0 : This bit must be set to 0 .
bits : 6 - 12 (7 bit)
access : read-write

__reserve1 : This bit must be set to 0 .
bits : 7 - 14 (8 bit)
access : read-write


SC3MD0

Serial 3 Mode Register 0
address_offset : 0x60 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC3MD0 SC3MD0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LNG STE DIR CTM SSC CE1

LNG : Transfer bit count [Clock-Synchronous] (*2)
bits : 0 - 2 (3 bit)
access : read-write

STE : Start condition selection [Clock-Synchronous] (*1)
bits : 3 - 6 (4 bit)
access : read-write

DIR : Transfer first bit selection
bits : 4 - 8 (5 bit)
access : read-write

CTM : Continuous communication mode selection [Clock-Synchronous]
bits : 5 - 10 (6 bit)
access : read-write

SSC : Clock source selection as operation clock [Clock-Synchronous]
bits : 6 - 12 (7 bit)
access : read-write

CE1 : Clock polarity selection [Clock-Synchronous]
bits : 7 - 14 (8 bit)
access : read-write


SC3MD1

Serial 3 Mode Register 1
address_offset : 0x61 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC3MD1 SC3MD1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD DIV MST CKM SBOS SBIS SBTS IOM

CMD : Communication mode selection
bits : 0 - 0 (1 bit)
access : read-write

DIV : Division value selection of transfer clock
bits : 1 - 2 (2 bit)
access : read-write

MST : Master/salve communication selection [Clock-Synchronous]
bits : 2 - 4 (3 bit)
access : read-write

CKM : Division selection of transfer clock [Clock-Synchronous]
bits : 3 - 6 (4 bit)
access : read-write

SBOS : SBOn(TXDn) pin output control
bits : 4 - 8 (5 bit)
access : read-write

SBIS : SBIn(RXDn)/SBOn(TXDn) pin input control
bits : 5 - 10 (6 bit)
access : read-write

SBTS : SBTn pin control
bits : 6 - 12 (7 bit)
access : read-write

IOM : Data input pin selection
bits : 7 - 14 (8 bit)
access : read-write


SC3MD2

Serial 3 Mode Register 2
address_offset : 0x64 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC3MD2 SC3MD2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BRKE BRKF __reserve0 NPE PM FM

BRKE : Break transmission control [UART]
bits : 0 - 0 (1 bit)
access : read-write

BRKF : Break reception detection [UART]
bits : 1 - 2 (2 bit)
access : read

__reserve0 : 0 is always read out.
bits : 2 - 4 (3 bit)
access : read

NPE : Parity bit selection [UART]
bits : 3 - 6 (4 bit)
access : read-write

PM : Parity bit function selection [UART]
bits : 4 - 9 (6 bit)
access : read-write

FM : The number of character bit and stop bit selection [UART]
bits : 6 - 13 (8 bit)
access : read-write


SC3MD3

Serial 3 Mode Register 3
address_offset : 0x65 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC3MD3 SC3MD3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 __reserve0 RSRN RSTN FDC

__reserve0 : 0 is always read out.
bits : 0 - 3 (4 bit)
access : read

RSRN : [Clock-Synchronous]
bits : 4 - 8 (5 bit)
access : read-write

RSTN : [Clock-Synchronous]
bits : 5 - 10 (6 bit)
access : read-write

FDC : Output level selection after the final bit transmit (SBOn pin) [Clock-Synchronous]
bits : 6 - 13 (8 bit)
access : read-write


SC3MD4

Serial 3 Mode Register 4
address_offset : 0x68 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC3MD4 SC3MD4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 __reserve0 SMD CSLV

__reserve0 : 0 is always read out.
bits : 0 - 5 (6 bit)
access : read

SMD : Clock-synchronous communication type selection
bits : 6 - 12 (7 bit)
access : read-write

CSLV : SBCS3 polarity selection
bits : 7 - 14 (8 bit)
access : read-write


SC3STR

Serial 3 Status Register
address_offset : 0x69 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC3STR SC3STR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ERE ORE PEK FEF REMP TEMP RBSY TBSY

ERE : Reception error detection
bits : 0 - 0 (1 bit)
access : read

ORE : Overrun error detection
bits : 1 - 2 (2 bit)
access : read

PEK : Parity error detection [UART]
bits : 2 - 4 (3 bit)
access : read

FEF : Framing error detection [UART]
bits : 3 - 6 (4 bit)
access : read

REMP : Reception buffer empty
bits : 4 - 8 (5 bit)
access : read

TEMP : Transmission buffer empty
bits : 5 - 10 (6 bit)
access : read

RBSY : Reception busy detection
bits : 6 - 12 (7 bit)
access : read

TBSY : Transmission busy detection
bits : 7 - 14 (8 bit)
access : read


SC3RB

Serial 3 Receptio3 Data Buffer Register
address_offset : 0x6C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC3RB SC3RB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB

RB : Reception data is read out.
bits : 0 - 7 (8 bit)
access : read


SC3TB

Serial 3 Tra3smissio3 Data Buffer Register
address_offset : 0x70 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC3TB SC3TB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TB

TB : Set the transmission data or the dummy data.
bits : 0 - 7 (8 bit)
access : read-write


SC0AD0

Serial 0 Address Setting Register 0
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC0AD0 SC0AD0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AD0

AD0 : Set the slave address.
bits : 0 - 7 (8 bit)
access : read-write


SC4MD0

Serial 4 Mode Register 0
address_offset : 0x80 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC4MD0 SC4MD0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LNG STE DIR CTM SSC CE1

LNG : Transfer bit count [Clock-Synchronous] (*2)
bits : 0 - 2 (3 bit)
access : read-write

STE : Start condition selection [Clock-Synchronous] (*1)
bits : 3 - 6 (4 bit)
access : read-write

DIR : Transfer first bit selection
bits : 4 - 8 (5 bit)
access : read-write

CTM : Continuous communication mode selection [Clock-Synchronous]
bits : 5 - 10 (6 bit)
access : read-write

SSC : Clock source selection as operation clock [Clock-Synchronous]
bits : 6 - 12 (7 bit)
access : read-write

CE1 : Clock polarity selection [Clock-Synchronous]
bits : 7 - 14 (8 bit)
access : read-write


SC4MD1

Serial 4 Mode Register 1
address_offset : 0x81 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC4MD1 SC4MD1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD DIV MST CKM SBOS SBIS SBTS IOM

CMD : Communication mode selection
bits : 0 - 0 (1 bit)
access : read-write

DIV : Division value selection of transfer clock
bits : 1 - 2 (2 bit)
access : read-write

MST : Master/salve communication selection [Clock-Synchronous]
bits : 2 - 4 (3 bit)
access : read-write

CKM : Division selection of transfer clock [Clock-Synchronous]
bits : 3 - 6 (4 bit)
access : read-write

SBOS : SBOn(TXDn) pin output control
bits : 4 - 8 (5 bit)
access : read-write

SBIS : SBIn(RXDn)/SBOn(TXDn) pin input control
bits : 5 - 10 (6 bit)
access : read-write

SBTS : SBTn pin control
bits : 6 - 12 (7 bit)
access : read-write

IOM : Data input pin selection
bits : 7 - 14 (8 bit)
access : read-write


SC4MD2

Serial 4 Mode Register 2
address_offset : 0x84 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC4MD2 SC4MD2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BRKE BRKF __reserve0 NPE PM FM

BRKE : Break transmission control [UART]
bits : 0 - 0 (1 bit)
access : read-write

BRKF : Break reception detection [UART]
bits : 1 - 2 (2 bit)
access : read

__reserve0 : 0 is always read out.
bits : 2 - 4 (3 bit)
access : read

NPE : Parity bit selection [UART]
bits : 3 - 6 (4 bit)
access : read-write

PM : Parity bit function selection [UART]
bits : 4 - 9 (6 bit)
access : read-write

FM : The number of character bit and stop bit selection [UART]
bits : 6 - 13 (8 bit)
access : read-write


SC4MD3

Serial 4 Mode Register 3
address_offset : 0x85 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC4MD3 SC4MD3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 __reserve0 RSRN RSTN FDC

__reserve0 : 0 is always read out.
bits : 0 - 3 (4 bit)
access : read

RSRN : [Clock-Synchronous]
bits : 4 - 8 (5 bit)
access : read-write

RSTN : [Clock-Synchronous]
bits : 5 - 10 (6 bit)
access : read-write

FDC : Output level selection after the final bit transmit (SBOn pin) [Clock-Synchronous]
bits : 6 - 13 (8 bit)
access : read-write


SC4MD4

Serial 4 Mode Register 4
address_offset : 0x88 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC4MD4 SC4MD4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 __reserve0 SMD CSLV

__reserve0 : 0 is always read out.
bits : 0 - 5 (6 bit)
access : read

SMD : Clock-synchronous communication type selection
bits : 6 - 12 (7 bit)
access : read-write

CSLV : SBCS3 polarity selection
bits : 7 - 14 (8 bit)
access : read-write


SC4STR

Serial 4 Status Register
address_offset : 0x89 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC4STR SC4STR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ERE ORE PEK FEF REMP TEMP RBSY TBSY

ERE : Reception error detection
bits : 0 - 0 (1 bit)
access : read

ORE : Overrun error detection
bits : 1 - 2 (2 bit)
access : read

PEK : Parity error detection [UART]
bits : 2 - 4 (3 bit)
access : read

FEF : Framing error detection [UART]
bits : 3 - 6 (4 bit)
access : read

REMP : Reception buffer empty
bits : 4 - 8 (5 bit)
access : read

TEMP : Transmission buffer empty
bits : 5 - 10 (6 bit)
access : read

RBSY : Reception busy detection
bits : 6 - 12 (7 bit)
access : read

TBSY : Transmission busy detection
bits : 7 - 14 (8 bit)
access : read


SC4RB

Serial 4 Receptio4 Data Buffer Register
address_offset : 0x8C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC4RB SC4RB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB

RB : Reception data is read out.
bits : 0 - 7 (8 bit)
access : read


SC4TB

Serial 4 Tra4smissio4 Data Buffer Register
address_offset : 0x90 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC4TB SC4TB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TB

TB : Set the transmission data or the dummy data.
bits : 0 - 7 (8 bit)
access : read-write


SC5MD0

Serial 5 Mode Register 0
address_offset : 0xA0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC5MD0 SC5MD0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LNG STE DIR CTM SSC CE1

LNG : Transfer bit count [Clock-Synchronous] (*2)
bits : 0 - 2 (3 bit)
access : read-write

STE : Start condition selection [Clock-Synchronous] (*1)
bits : 3 - 6 (4 bit)
access : read-write

DIR : Transfer first bit selection
bits : 4 - 8 (5 bit)
access : read-write

CTM : Continuous communication mode selection [Clock-Synchronous]
bits : 5 - 10 (6 bit)
access : read-write

SSC : Clock source selection as operation clock [Clock-Synchronous]
bits : 6 - 12 (7 bit)
access : read-write

CE1 : Clock polarity selection [Clock-Synchronous]
bits : 7 - 14 (8 bit)
access : read-write


SC5MD1

Serial 5 Mode Register 1
address_offset : 0xA1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC5MD1 SC5MD1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD DIV MST CKM SBOS SBIS SBTS IOM

CMD : Communication mode selection
bits : 0 - 0 (1 bit)
access : read-write

DIV : Division value selection of transfer clock
bits : 1 - 2 (2 bit)
access : read-write

MST : Master/salve communication selection [Clock-Synchronous]
bits : 2 - 4 (3 bit)
access : read-write

CKM : Division selection of transfer clock [Clock-Synchronous]
bits : 3 - 6 (4 bit)
access : read-write

SBOS : SBOn(TXDn) pin output control
bits : 4 - 8 (5 bit)
access : read-write

SBIS : SBIn(RXDn)/SBOn(TXDn) pin input control
bits : 5 - 10 (6 bit)
access : read-write

SBTS : SBTn pin control
bits : 6 - 12 (7 bit)
access : read-write

IOM : Data input pin selection
bits : 7 - 14 (8 bit)
access : read-write


SC5MD2

Serial 5 Mode Register 2
address_offset : 0xA4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC5MD2 SC5MD2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BRKE BRKF __reserve0 NPE PM FM

BRKE : Break transmission control [UART]
bits : 0 - 0 (1 bit)
access : read-write

BRKF : Break reception detection [UART]
bits : 1 - 2 (2 bit)
access : read

__reserve0 : 0 is always read out.
bits : 2 - 4 (3 bit)
access : read

NPE : Parity bit selection [UART]
bits : 3 - 6 (4 bit)
access : read-write

PM : Parity bit function selection [UART]
bits : 4 - 9 (6 bit)
access : read-write

FM : The number of character bit and stop bit selection [UART]
bits : 6 - 13 (8 bit)
access : read-write


SC5MD3

Serial 5 Mode Register 3
address_offset : 0xA5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC5MD3 SC5MD3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 __reserve0 RSRN RSTN FDC

__reserve0 : 0 is always read out.
bits : 0 - 3 (4 bit)
access : read

RSRN : [Clock-Synchronous]
bits : 4 - 8 (5 bit)
access : read-write

RSTN : [Clock-Synchronous]
bits : 5 - 10 (6 bit)
access : read-write

FDC : Output level selection after the final bit transmit (SBOn pin) [Clock-Synchronous]
bits : 6 - 13 (8 bit)
access : read-write


SC5MD4

Serial 5 Mode Register 4
address_offset : 0xA8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC5MD4 SC5MD4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 UARTMOD __reserve0 __reserve1

UARTMOD : [Clock-Synchronous]
bits : 0 - 1 (2 bit)
access : read-write

__reserve0 : This bit must be set to 0 .
bits : 2 - 4 (3 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 3 - 10 (8 bit)
access : read


SC5STR

Serial 5 Status Register
address_offset : 0xA9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC5STR SC5STR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ERE ORE PEK FEF REMP TEMP RBSY TBSY

ERE : Reception error detection
bits : 0 - 0 (1 bit)
access : read

ORE : Overrun error detection
bits : 1 - 2 (2 bit)
access : read

PEK : Parity error detection [UART]
bits : 2 - 4 (3 bit)
access : read

FEF : Framing error detection [UART]
bits : 3 - 6 (4 bit)
access : read

REMP : Reception buffer empty
bits : 4 - 8 (5 bit)
access : read

TEMP : Transmission buffer empty
bits : 5 - 10 (6 bit)
access : read

RBSY : Reception busy detection
bits : 6 - 12 (7 bit)
access : read

TBSY : Transmission busy detection
bits : 7 - 14 (8 bit)
access : read


SC5RB

Serial 5 Receptio5 Data Buffer Register
address_offset : 0xAC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC5RB SC5RB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB

RB : Reception data is read out.
bits : 0 - 7 (8 bit)
access : read


SC5TB

Serial 5 Tra5smissio5 Data Buffer Register
address_offset : 0xB0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC5TB SC5TB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TB

TB : Set the transmission data or the dummy data.
bits : 0 - 7 (8 bit)
access : read-write


SC0STR0

Serial 0 Status Register 0
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC0STR0 SC0STR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ORE __reserve0 REMP TEMP __reserve1 BSY

ORE : Overrun error detection
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 4 (4 bit)
access : read

REMP : Reception buffer empty
bits : 4 - 8 (5 bit)
access : read

TEMP : Transmission buffer empty
bits : 5 - 10 (6 bit)
access : read

__reserve1 : 0 is always read out.
bits : 6 - 12 (7 bit)
access : read

BSY : Bus busy detection [Clock-Synchronous]
bits : 7 - 14 (8 bit)
access : read


SCINTSEL

Clock Edge Interrupt Setting Register
address_offset : 0xC0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SCINTSEL SCINTSEL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SC0IGC SC2IGC SC3IGC SC4IGC __reserve0

SC0IGC : Control of SBT1 falling edge interrupt
bits : 0 - 0 (1 bit)
access : read-write

SC2IGC : Control of SBT3 falling edge interrupt
bits : 2 - 4 (3 bit)
access : read-write

SC3IGC : Control of SBT4 falling edge interrupt
bits : 3 - 6 (4 bit)
access : read-write

SC4IGC : Control of SBT5 falling edge interrupt
bits : 4 - 8 (5 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 5 - 12 (8 bit)
access : read


SC0STR1

Serial 0 Status Register 1
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC0STR1 SC0STR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA_ERR GCALL IICBSY BUSBSY STRT ADD_ACC ABT_LST WRS

DATA_ERR : Communication error detection [IIC]
bits : 0 - 0 (1 bit)
access : read-write

GCALL : General call detection [IIC]
bits : 1 - 2 (2 bit)
access : read

IICBSY : IIC communication busy detection [IIC]
bits : 2 - 4 (3 bit)
access : read

BUSBSY : Bus busy detection [IIC]
bits : 3 - 6 (4 bit)
access : read

STRT : Start condition detection [IIC][Slave]
bits : 4 - 8 (5 bit)
access : read

ADD_ACC : Slave address match detection [IIC][Slave]
bits : 5 - 10 (6 bit)
access : read

ABT_LST : Arbitration lost detection [IIC][Master]
bits : 6 - 12 (7 bit)
access : read-write

WRS : Transmission/reception mode [IIC][Slave]
bits : 7 - 14 (8 bit)
access : read


BRTM_S_MODE

Baud Rate Timer Operation Mode Setting Register
address_offset : 0xF00 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

BRTM_S_MODE BRTM_S_MODE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 S0_MODE S1_MODE S3_MODE S4_MODE S5_MODE S6_MODE __reserve0

S0_MODE : Baud rate timer 0 output clock duty setting (High-level : Low-level)
bits : 0 - 0 (1 bit)
access : read-write

S1_MODE : Baud rate timer 1 output clock duty setting (High-level : Low-level)
bits : 1 - 2 (2 bit)
access : read-write

S3_MODE : Baud rate timer 3 output clock duty setting (High-level : Low-level)
bits : 3 - 6 (4 bit)
access : read-write

S4_MODE : Baud rate timer 4 output clock duty setting (High-level : Low-level)
bits : 4 - 8 (5 bit)
access : read-write

S5_MODE : Baud rate timer 5 output clock duty setting (High-level : Low-level)
bits : 5 - 10 (6 bit)
access : read-write

S6_MODE : Baud rate timer 6 output clock duty setting (High-level : Low-level)
bits : 6 - 12 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read


BRTM_S_EN

Baud Rate Timer Operation Enable Register
address_offset : 0xF01 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

BRTM_S_EN BRTM_S_EN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 S0_EN S1_EN S3_EN S4_EN S5_EN S6_EN __reserve0

S0_EN : Baud rate timer 0 operation enable.
bits : 0 - 0 (1 bit)
access : read-write

S1_EN : Baud rate timer 1 operation enable.
bits : 1 - 2 (2 bit)
access : read-write

S3_EN : Baud rate timer 3 operation enable.
bits : 3 - 6 (4 bit)
access : read-write

S4_EN : Baud rate timer 4 operation enable.
bits : 4 - 8 (5 bit)
access : read-write

S5_EN : Baud rate timer 5 operation enable.
bits : 5 - 10 (6 bit)
access : read-write

S6_EN : Baud rate timer 6 operation enable.
bits : 6 - 12 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read


BRTM_S01_CK

Baud Rate Timer 01 Count Clock Selection Register
address_offset : 0xF04 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

BRTM_S01_CK BRTM_S01_CK read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 S0_CK S1_CK

S0_CK : Baud rate timer 0 count clock selection.
bits : 0 - 3 (4 bit)
access : read-write

S1_CK : Baud rate timer 1 count clock selection.
bits : 4 - 11 (8 bit)
access : read-write


BRTM_S23_CK

Baud Rate Timer 23 Count Clock Selection Register
address_offset : 0xF05 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

BRTM_S23_CK BRTM_S23_CK read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 S3_CK

S3_CK : Selection of count clock in baud rate timer 3
bits : 4 - 11 (8 bit)
access : read-write


BRTM_S45_CK

Baud Rate Timer 45 Count Clock Selection Register
address_offset : 0xF08 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

BRTM_S45_CK BRTM_S45_CK read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 S4_CK S5_CK

S4_CK : Selection of count clock in baud rate timer 4
bits : 0 - 3 (4 bit)
access : read-write

S5_CK : Selection of count clock in baud rate timer 5
bits : 4 - 11 (8 bit)
access : read-write


BRTM_S6_CK

Baud Rate Timer 6 Count Clock Selection Register
address_offset : 0xF09 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

BRTM_S6_CK BRTM_S6_CK read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 S6_CK __reserve0

S6_CK : Selection of count clock in baud rate timer 6
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read-write


BRTM_S0_OC

Baud Rate Timer 0 Compare Register
address_offset : 0xF0C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

BRTM_S0_OC BRTM_S0_OC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 Sn_OC

Sn_OC : Set the value to be compared with the counter of baud rate timer n.
bits : 0 - 7 (8 bit)
access : read-write


BRTM_S1_OC

Baud Rate Timer 1 Compare Register
address_offset : 0xF0D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

BRTM_S1_OC BRTM_S1_OC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 Sn_OC

Sn_OC : Set the value to be compared with the counter of baud rate timer n.
bits : 0 - 7 (8 bit)
access : read-write


BRTM_S3_OC

Baud Rate Timer 3 Compare Register
address_offset : 0xF11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

BRTM_S3_OC BRTM_S3_OC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 Sn_OC

Sn_OC : Set the value to be compared with the counter of baud rate timer n.
bits : 0 - 7 (8 bit)
access : read-write


BRTM_S4_OC

Baud Rate Timer 4 Compare Register
address_offset : 0xF14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

BRTM_S4_OC BRTM_S4_OC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 Sn_OC

Sn_OC : Set the value to be compared with the counter of baud rate timer n.
bits : 0 - 7 (8 bit)
access : read-write


BRTM_S5_OC

Baud Rate Timer 5 Compare Register
address_offset : 0xF15 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

BRTM_S5_OC BRTM_S5_OC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 Sn_OC

Sn_OC : Set the value to be compared with the counter of baud rate timer n.
bits : 0 - 7 (8 bit)
access : read-write


BRTM_S6_OC

Baud Rate Timer 6 Compare Register
address_offset : 0xF18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

BRTM_S6_OC BRTM_S6_OC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 Sn_OC

Sn_OC : Set the value to be compared with the counter of baud rate timer n.
bits : 0 - 7 (8 bit)
access : read-write



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