\n

LIN

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xD byte (0x0)
mem_usage : registers
protection :

Registers

LINTXCTR

LINRXCTR

LINERRSTAT

LINTXCHKS

LINRXCHKS


LINTXCTR

LIN Transmission Control Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

LINTXCTR LINTXCTR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SBFSEL SBFEN TXCHSST BITERREN __reserve0

SBFSEL : Synch Break field transmission width selection
bits : 0 - 2 (3 bit)
access : read-write

SBFEN : Synch Break field transmission trigger/monitor(*1)
bits : 3 - 6 (4 bit)
access : read-write

TXCHSST : Check sum operation for transmission
bits : 4 - 8 (5 bit)
access : read-write

BITERREN : Bit error detection function selection
bits : 5 - 10 (6 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 6 - 13 (8 bit)
access : read


LINRXCTR

LIN Reception Control Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

LINRXCTR LINRXCTR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LINEN SBFREC SFREC SBFBSY SFBSY RXCHSST __reserve0 TMIOSEL

LINEN : LIN communication enable
bits : 0 - 0 (1 bit)
access : read-write

SBFREC : Wake up signal and Synch Break field reception enable
bits : 1 - 2 (2 bit)
access : read-write

SFREC : Synch field reception enable
bits : 2 - 4 (3 bit)
access : read-write

SBFBSY : Synch Break field reception busy
bits : 3 - 6 (4 bit)
access : read

SFBSY : Synch field reception busy
bits : 4 - 8 (5 bit)
access : read

RXCHSST : Check sum operation for reception
bits : 5 - 10 (6 bit)
access : read-write

__reserve0 : This bit must be set to 0 .
bits : 6 - 12 (7 bit)
access : read-write

TMIOSEL : Selection of clock source for Timer 0
bits : 7 - 14 (8 bit)
access : read-write


LINERRSTAT

LIN Error Status Register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

LINERRSTAT LINERRSTAT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BITERR __reserve0 CHKSERR __reserve1

BITERR : Bit error detection(*3)
bits : 0 - 0 (1 bit)
access : read

__reserve0 : 0 is always read out.
bits : 1 - 2 (2 bit)
access : read

CHKSERR : Check sum error detection(*1)(*2)
bits : 2 - 4 (3 bit)
access : read

__reserve1 : 0 is always read out.
bits : 3 - 10 (8 bit)
access : read


LINTXCHKS

LIN Transmission Check sum Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

LINTXCHKS LINTXCHKS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TXCHKS

TXCHKS : Check sum value for the transmission data is read out.
bits : 0 - 7 (8 bit)
access : read


LINRXCHKS

LIN Reception Check sum Register
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

LINRXCHKS LINRXCHKS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RXCHKS

RXCHKS : Check sum value for the reception data is read out.
bits : 0 - 7 (8 bit)
access : read



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