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SIF_7

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x510 byte (0x0)
mem_usage : registers
protection :

Registers

SC7I2C_CTR0

SC7I2C_CTR1

SC7RB

SC7TB

SC7I2C_STS0

SC7I2C_STS1

SC7I2C_IRQSTS

SC7STR

SC7I2C_CTR2

SC7I2C_IRQCTR

SC7SI2C_CTR0

SC7SI2C_CTR1

SC7SI2C_CTR2

SC7SI2C_IRQCTR

SC7SSYNC_CTR0

SC7SUART_CTR

SC7S_CTR0

SC7S_CTR1

SC7S_RST

SC7I2C_CLKH

SC7SI2C_STS0

SC7SI2C_IRQSTS

SC7SSTR

SC7I2C_CLKL

BRTM_S7_MODE

BRTM_S7_EN

BRTM_S7_CK

BRTM_S7_OC

SC7I2C_1STADR

SC7CI2C_CTR0

SC7CI2C_CTR1

SC7CI2C_CTR2

SC7CI2C_IRQCTR

SC7CSYNC_CTR0

SC7CUART_CTR

SC7C_CTR0

SC7C_CTR1

SC7C_RST

SC7I2C_TCLKOC

SC7SYNC_CTR0

SC7UART_CTR

SC7_CTR0

SC7_CTR1

SC7_RST


SC7I2C_CTR0

IIC Control Register 0
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7I2C_CTR0 SC7I2C_CTR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SDA_FIXL SCL_FIXL __reserve0 __reserve1 __reserve2 ADREXC_SEL ADRNG_SEL ADROK_SEL

SDA_FIXL : SDAport LOW level output [IIC] (*3)
bits : 0 - 0 (1 bit)
access : read-write

SCL_FIXL : SCL port LOW level output [IIC] (*3)
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 4 (3 bit)
access : read

__reserve1 : This bit must be set to 0 .
bits : 3 - 6 (4 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 4 - 8 (5 bit)
access : read

ADREXC_SEL : Extension code matching operation select [IIC] (*1)(*2)(*3)
bits : 5 - 10 (6 bit)
access : read-write

ADRNG_SEL : Slave address receive mode selection [IIC] (*1)(*3)
bits : 6 - 12 (7 bit)
access : read-write

ADROK_SEL : Slave address receive mode selection [IIC] (*1)(*3)
bits : 7 - 14 (8 bit)
access : read-write


SC7I2C_CTR1

IIC Control Register 1
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7I2C_CTR1 SC7I2C_CTR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TEXT_ON TOUT_ON SCLH_SEL SCLH_ON LPW_LMTSEL LPW_ON __reserve0

TEXT_ON : TLOW:MEXT / TLOW:SEXT detection enable [IIC] (*1)
bits : 0 - 0 (1 bit)
access : read-write

TOUT_ON : Clock Low-level period (TTIMEOUT) detection enable [IIC] (*1)
bits : 1 - 2 (2 bit)
access : read-write

SCLH_SEL : Clock High-level period detection time [IIC] (*1)
bits : 2 - 5 (4 bit)
access : read-write

SCLH_ON : Clock High-level period (THIGH) detection enable [IIC] (*1)
bits : 4 - 8 (5 bit)
access : read-write

LPW_LMTSEL : Bus stop detection period [IIC] (*1)
bits : 5 - 10 (6 bit)
access : read-write

LPW_ON : Bus stop detection enable [IIC] (*1)
bits : 6 - 12 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read


SC7RB

Serial 7 Reception Data Buffer Register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7RB SC7RB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB

RB : Reception data is read out.
bits : 0 - 7 (8 bit)
access : read


SC7TB

Serial 7 Transmission Data Buffer Register
address_offset : 0x12 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7TB SC7TB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TB

TB : Set the transmission data or the dummy data.
bits : 0 - 7 (8 bit)
access : read-write


SC7I2C_STS0

IIC Status Register 0
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7I2C_STS0 SC7I2C_STS0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RWS_SLV ADROK NACK TRANS_BUSY BUS_BUSY ABT_LST ADREXC BUSERR

RWS_SLV : Read/ Write mode determination at Master/Slave communication [IIC] (*4)
bits : 0 - 0 (1 bit)
access : read

ADROK : Slave address matching detection [IIC]
bits : 1 - 2 (2 bit)
access : read

NACK : NACK detection [IIC]
bits : 2 - 4 (3 bit)
access : read

TRANS_BUSY : Communication busy state detection [IIC] (*3)
bits : 3 - 6 (4 bit)
access : read

BUS_BUSY : Bus busy state detection [IIC] (*2)
bits : 4 - 8 (5 bit)
access : read

ABT_LST : Arbitration lost detection [IIC] (*1)
bits : 5 - 10 (6 bit)
access : read-write

ADREXC : Extension code receive detection [IIC]
bits : 6 - 12 (7 bit)
access : read

BUSERR : Bus error detection [IIC] (*1)(*5)
bits : 7 - 14 (8 bit)
access : read-write


SC7I2C_STS1

IIC Status Register 1
address_offset : 0x15 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7I2C_STS1 SC7I2C_STS1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LPW WKUPIE_JUG WKUPIE_DET __reserve0

LPW : Bus stop detection [IIC]
bits : 0 - 0 (1 bit)
access : read

WKUPIE_JUG : WKUP interrupt judgement [IIC]
bits : 1 - 2 (2 bit)
access : read

WKUPIE_DET : CPU WAKEUP interrupt status [IIC]
bits : 2 - 4 (3 bit)
access : read

__reserve0 : 0 is always read out.
bits : 3 - 10 (8 bit)
access : read


SC7I2C_IRQSTS

IIC Inteput Status Register
address_offset : 0x16 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7I2C_IRQSTS SC7I2C_IRQSTS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACKDONE BYTEDONE STOP START ADRNG TOUT WKUP

ACKDONE : ACK communication completion detection (*1) [IIC] (*1)(*2)
bits : 0 - 0 (1 bit)
access : read-write

BYTEDONE : Byte data communication completion detection [IIC] (*1)(*2)
bits : 1 - 2 (2 bit)
access : read-write

STOP : Stop condition detection [IIC] (*1)(*2)
bits : 2 - 4 (3 bit)
access : read-write

START : Start condition detection [IIC] (*1)(*2)(*3)
bits : 3 - 6 (4 bit)
access : read-write

ADRNG : Slave address mismatch detection [IIC] (*1)(*2)
bits : 4 - 8 (5 bit)
access : read-write

TOUT : Time-out detection [IIC] (*2)
bits : 5 - 11 (7 bit)
access : read

WKUP : IIC standby status exit detection [IIC] (*1)(*2)
bits : 7 - 14 (8 bit)
access : read-write


SC7STR

Clock-Synchronous/UART Status Register
address_offset : 0x17 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7STR SC7STR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ERE ORE PEK FEF REMP TEMP RBSY TBSY

ERE : Reception error detection [Clock-Synchronous/UART]
bits : 0 - 0 (1 bit)
access : read

ORE : Overrun error detection [Clock-Synchronous/UART](*1)
bits : 1 - 2 (2 bit)
access : read-write

PEK : Parity error detection [UART](*1)
bits : 2 - 4 (3 bit)
access : read-write

FEF : Framing error detection [UART](*1)
bits : 3 - 6 (4 bit)
access : read-write

REMP : Reception buffer empty [Clock-Synchronous/UART]
bits : 4 - 8 (5 bit)
access : read

TEMP : Transmission buffer empty [Clock-Synchronous/UART]
bits : 5 - 10 (6 bit)
access : read

RBSY : Reception busy detection [Clock-Synchronous/UART]
bits : 6 - 12 (7 bit)
access : read

TBSY : Transmission busy detection [Clock-Synchronous/UART]
bits : 7 - 14 (8 bit)
access : read


SC7I2C_CTR2

IIC Control Register 2
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7I2C_CTR2 SC7I2C_CTR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 __reserve0 __reserve1 TRANS_END ACK_SET RWS_MST STOP_EN START_EN __reserve2

__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read

__reserve1 : 0 is always read out.
bits : 1 - 2 (2 bit)
access : read

TRANS_END : Communication end setting (*4)
bits : 2 - 4 (3 bit)
access : read-write

ACK_SET : Transmission ACK bit selection [IIC] (*4)
bits : 3 - 6 (4 bit)
access : read-write

RWS_MST : Read/Write mode selection at Master [IIC] (*3)(*4)
bits : 4 - 8 (5 bit)
access : read-write

STOP_EN : Stop condition generation selection [IIC Master communication] (*2)(*4)
bits : 5 - 10 (6 bit)
access : read-write

START_EN : Start condition generation selection [IIC] (*1)(*4)
bits : 6 - 12 (7 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read


SC7I2C_IRQCTR

IIC Interrupt Control Register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7I2C_IRQCTR SC7I2C_IRQCTR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACKDONE_IE BYTEDONE_IE STOP_IE START_IE ADRNG_IE TOUT_IE WKUP_IE WKUP_SEL

ACKDONE_IE : Enable ACK communication completion interrupt factor [IIC] (*4)(*5)
bits : 0 - 0 (1 bit)
access : read-write

BYTEDONE_IE : Enable Byte data communication completion interrupt factor [IIC] (*2)(*3)(*5)
bits : 1 - 2 (2 bit)
access : read-write

STOP_IE : Enable Stop condition interrupt factor [IIC] (*5)
bits : 2 - 4 (3 bit)
access : read-write

START_IE : Enable Start condition detection interrupt factor [IIC] (*5)
bits : 3 - 6 (4 bit)
access : read-write

ADRNG_IE : Enable Slave address mismatch interrupt factor [IIC] (*5)
bits : 4 - 8 (5 bit)
access : read-write

TOUT_IE : Enable Time-out interrupt factor [IIC] (*5)
bits : 5 - 10 (6 bit)
access : read-write

WKUP_IE : Enable CPU WAKEUP interrupt factor [IIC] (*1)(*5)
bits : 6 - 12 (7 bit)
access : read-write

WKUP_SEL : Interrupt source selection for exiting CPU standby mode [IIC] (*5)
bits : 7 - 14 (8 bit)
access : read-write


SC7SI2C_CTR0

IIC Control Set Register 0
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7SI2C_CTR0 SC7SI2C_CTR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SDA_FIXL SCL_FIXL __reserve0 __reserve1 __reserve2 ADREXC_SEL ADRNG_SEL ADROK_SEL

SDA_FIXL : Set SC7I2C_CTR0.SDA_FIXL bit to 1
bits : 0 - 0 (1 bit)
access : write

SCL_FIXL : Set SC7I2C_CTR0.SCL_FIXL bit to 1
bits : 1 - 2 (2 bit)
access : write

__reserve0 : This bit must be set to 0 .
bits : 2 - 4 (3 bit)
access : write

__reserve1 : This bit must be set to 0 .
bits : 3 - 6 (4 bit)
access : write

__reserve2 : This bit must be set to 0 .
bits : 4 - 8 (5 bit)
access : write

ADREXC_SEL : Set SC7I2C_CTR0.ADREXC_SEL bit to 1
bits : 5 - 10 (6 bit)
access : write

ADRNG_SEL : Set SC7I2C_CTR0.ADRNG_SEL bit to 1
bits : 6 - 12 (7 bit)
access : write

ADROK_SEL : Set SC7I2C_CTR0.ADROK_SEL bit to 1
bits : 7 - 14 (8 bit)
access : write


SC7SI2C_CTR1

IIC Control Set Register 1
address_offset : 0x31 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7SI2C_CTR1 SC7SI2C_CTR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TEXT_ON TOUT_ON SCLH_SEL SCLH_ON LPW_LMTSEL LPW_ON __reserve0

TEXT_ON : Set SC7I2C_CTR1.TEXT_ON bit to 1
bits : 0 - 0 (1 bit)
access : write

TOUT_ON : Set SC7I2C_CTR1.TOUT_ON bit to 1
bits : 1 - 2 (2 bit)
access : write

SCLH_SEL : Set SC7I2C_CTR1.SCLH_SEL bit to 1
bits : 2 - 5 (4 bit)
access : write

SCLH_ON : Set SC7I2C_CTR1.SCLH_ON bit to 1
bits : 4 - 8 (5 bit)
access : write

LPW_LMTSEL : Set SC7I2C_CTR1.LPW_LMTSEL bit to 1
bits : 5 - 10 (6 bit)
access : write

LPW_ON : Set SC7I2C_CTR1.LPW_ONL bit to 1
bits : 6 - 12 (7 bit)
access : write

__reserve0 : This bit must be set to 0 .
bits : 7 - 14 (8 bit)
access : write


SC7SI2C_CTR2

IIC Control Set Register 2
address_offset : 0x32 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7SI2C_CTR2 SC7SI2C_CTR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 __reserve0 __reserve1 TRANS_END ACK_SET RWS_MST STOP_EN START_EN __reserve2

__reserve0 : This bit must be set to 0 .
bits : 0 - 0 (1 bit)
access : write

__reserve1 : This bit must be set to 0 .
bits : 1 - 2 (2 bit)
access : write

TRANS_END : Set SC7I2C_CTR2.TRANS_ENDL bit to 1 .
bits : 2 - 4 (3 bit)
access : write

ACK_SET : Set SC7I2C_CTR2.ACK_SETL bit to 1 .
bits : 3 - 6 (4 bit)
access : write

RWS_MST : Set SC7I2C_CTR2.RWS_MSTL bit to 1 .
bits : 4 - 8 (5 bit)
access : write

STOP_EN : Set SC7I2C_CTR2.STOP_ENL bit to 1 .
bits : 5 - 10 (6 bit)
access : write

START_EN : Set SC7I2C_CTR2.START_ENL bit to 1 .
bits : 6 - 12 (7 bit)
access : write

__reserve2 : This bit must be set to 0 .
bits : 7 - 14 (8 bit)
access : write


SC7SI2C_IRQCTR

IIC Interrupt Control Set Register
address_offset : 0x33 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7SI2C_IRQCTR SC7SI2C_IRQCTR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACKDONE_IE BYTEDONE_IE STOP_IE START_IE ADRNG_IE TOUT_IE WKUP_IE WKUP_SEL

ACKDONE_IE : Set SC7I2C_IRQCTR.ACKDONE_IE bit to 1 .
bits : 0 - 0 (1 bit)
access : write

BYTEDONE_IE : Set SC7I2C_IRQCTR.BYTEDONE_IE bit to 1 .
bits : 1 - 2 (2 bit)
access : write

STOP_IE : Set SC7I2C_IRQCTR.STOP_IE bit to 1 .
bits : 2 - 4 (3 bit)
access : write

START_IE : Set SC7I2C_IRQCTR.START_IE bit to 1 .
bits : 3 - 6 (4 bit)
access : write

ADRNG_IE : Set SC7I2C_IRQCTR.ADRNG_IE bit to 1 .
bits : 4 - 8 (5 bit)
access : write

TOUT_IE : Set SC7I2C_IRQCTR.TOUT_IE bit to 1 .
bits : 5 - 10 (6 bit)
access : write

WKUP_IE : Set SC7I2C_IRQCTR.WKUP_IE bit to 1 .
bits : 6 - 12 (7 bit)
access : write

WKUP_SEL : Set SC7I2C_IRQCTR.WKUP_SEL bit to 1 .
bits : 7 - 14 (8 bit)
access : write


SC7SSYNC_CTR0

Clock-Synchronous Control Set Register
address_offset : 0x38 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7SSYNC_CTR0 SC7SSYNC_CTR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SBCSLV SBCSEN CKPH CE1 FDC __reserve0

SBCSLV : Set SC7SYNC_CTR0.SBCSLV bit to 1 .
bits : 0 - 0 (1 bit)
access : write

SBCSEN : Set SC7SYNC_CTR0.SBCSEN bit to 1 .
bits : 1 - 2 (2 bit)
access : write

CKPH : Set SC7SYNC_CTR0.CKPH bit to 1 .
bits : 2 - 4 (3 bit)
access : write

CE1 : Set SC7SYNC_CTR0.CE1 bit to 1 .
bits : 3 - 6 (4 bit)
access : write

FDC : This bit must be set to 00 .
bits : 4 - 9 (6 bit)
access : write

__reserve0 : This bit must be set to 0 .
bits : 6 - 13 (8 bit)
access : write


SC7SUART_CTR

UART Control Set Register
address_offset : 0x3A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7SUART_CTR SC7SUART_CTR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BRKE BRKF __reserve0 NPE PM FM __reserve1

BRKE : Set SC7UART_CTR.BRKE bit to 1
bits : 0 - 0 (1 bit)
access : write

BRKF : This bit must be set to 0 .
bits : 1 - 2 (2 bit)
access : write

__reserve0 : This bit must be set to 0 .
bits : 2 - 4 (3 bit)
access : write

NPE : Set SC7UART_CTR.NPE bit to 1
bits : 3 - 6 (4 bit)
access : write

PM : Set SC7UART_CTR.PM bit to 1
bits : 4 - 9 (6 bit)
access : write

FM : Set SC7UART_CTR.FM bit to 1
bits : 6 - 12 (7 bit)
access : write

__reserve1 : This bit must be set to 0 .
bits : 7 - 14 (8 bit)
access : write


SC7S_CTR0

Serial 7 Control Set Register 0
address_offset : 0x3C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7S_CTR0 SC7S_CTR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SBOS SBIS IOM CKM CMD DIR MST

SBOS : Set SC7_CTR0.SBOS bit to 1 .
bits : 0 - 0 (1 bit)
access : write

SBIS : Set SC7_CTR0.SBIS bit to 1 .
bits : 1 - 2 (2 bit)
access : write

IOM : Set SC7_CTR0.IOM bit to 1 .
bits : 2 - 4 (3 bit)
access : write

CKM : Set SC7_CTR0.CKM bit to 1 .
bits : 3 - 6 (4 bit)
access : write

CMD : This bit must be set to 00 .
bits : 4 - 9 (6 bit)
access : write

DIR : Set SC7_CTR0.DIR bit to 1 .
bits : 6 - 12 (7 bit)
access : write

MST : Set SC7_CTR0.MST bit to 1 .
bits : 7 - 14 (8 bit)
access : write


SC7S_CTR1

Serial 7 Control Set Register 1
address_offset : 0x3D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7S_CTR1 SC7S_CTR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 STREQ TRGSEL DIV LNG __reserve0

STREQ : Communication start trigger by software (*1)(*2)
bits : 0 - 0 (1 bit)
access : write

TRGSEL : This bit must be set to 00 .
bits : 1 - 3 (3 bit)
access : write

DIV : Set C7_CTR1.DIV bit to 1 .
bits : 3 - 6 (4 bit)
access : write

LNG : This bit must be set to 000 .
bits : 4 - 10 (7 bit)
access : write

__reserve0 : This bit must be set to 0 .
bits : 7 - 14 (8 bit)
access : write


SC7S_RST

Serial 7 Reset Set Register
address_offset : 0x3E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7S_RST SC7S_RST read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RSTN RSRN __reserve0

RSTN : Set SC7_RST.RSTN bit to 1
bits : 0 - 0 (1 bit)
access : write

RSRN : SetSC7_RST.RSRN bit to 1
bits : 1 - 2 (2 bit)
access : write

__reserve0 : This bit must be set to 00 .
bits : 2 - 9 (8 bit)
access : write


SC7I2C_CLKH

IIC Clock High Level Frequency Setting Register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7I2C_CLKH SC7I2C_CLKH read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SCL_SETH __reserve0

SCL_SETH : High level period of transfer clock at master communication [IIC] (*1)(*2)(*3)
bits : 0 - 6 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read


SC7SI2C_STS0

IIC Status Set Register 0
address_offset : 0x44 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7SI2C_STS0 SC7SI2C_STS0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RWS_SLV ADROK NACK TRANS_BUSY BUS_BUSY ABT_LST ADREXC BUSERR

RWS_SLV : This bit must be set to 0 .
bits : 0 - 0 (1 bit)
access : write

ADROK : This bit must be set to 0 .
bits : 1 - 2 (2 bit)
access : write

NACK : This bit must be set to 0 .
bits : 2 - 4 (3 bit)
access : write

TRANS_BUSY : This bit must be set to 0 .
bits : 3 - 6 (4 bit)
access : write

BUS_BUSY : This bit must be set to 0 .
bits : 4 - 8 (5 bit)
access : write

ABT_LST : Clear SC7I2C_STS0.ABT_LST bit to 0 .
bits : 5 - 10 (6 bit)
access : write

ADREXC : This bit must be set to 0 .
bits : 6 - 12 (7 bit)
access : write

BUSERR : Clear SC7I2C_STS0.BUSERR bit to 0 .
bits : 7 - 14 (8 bit)
access : write


SC7SI2C_IRQSTS

IIC Inteput Clear Status Register
address_offset : 0x46 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7SI2C_IRQSTS SC7SI2C_IRQSTS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACKDONE BYTEDONE STOP START ADRNG TOUT WKUP

ACKDONE : Clear SC7I2C_IRQSTS.ACKDONE bit to 0 .
bits : 0 - 0 (1 bit)
access : write

BYTEDONE : Clear SC7I2C_IRQSTS.BYREDONE bit to 0 .
bits : 1 - 2 (2 bit)
access : write

STOP : Clear SC7I2C_IRQSTS.STOP bit to 0 .
bits : 2 - 4 (3 bit)
access : write

START : Clear C7I2C_IRQSTS.START bit to 0 .
bits : 3 - 6 (4 bit)
access : write

ADRNG : Clear SC7I2C_IRQSTS.ADRNG bit to 0 .
bits : 4 - 8 (5 bit)
access : write

TOUT : This bit must be set to 00 .
bits : 5 - 11 (7 bit)
access : write

WKUP : Clear SC7I2C_IRQSTS.WKUP bit to 0 .
bits : 7 - 14 (8 bit)
access : write


SC7SSTR

Clock-Synchronous/UART Status Set Register
address_offset : 0x47 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7SSTR SC7SSTR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ERE ORE PEK FEF REMP TEMP RBSY TBSY

ERE : This bit must be set to 0 .
bits : 0 - 0 (1 bit)
access : write

ORE : Clear SC7STR.ORE bit to 0 .
bits : 1 - 2 (2 bit)
access : write

PEK : Clear SC7STR.PEK bit to 0 .
bits : 2 - 4 (3 bit)
access : write

FEF : Clear SC7STR.FEF bit to 0 .
bits : 3 - 6 (4 bit)
access : write

REMP : This bit must be set to 0 .
bits : 4 - 8 (5 bit)
access : write

TEMP : This bit must be set to 0 .
bits : 5 - 10 (6 bit)
access : write

RBSY : This bit must be set to 0 .
bits : 6 - 12 (7 bit)
access : write

TBSY : This bit must be set to 0 .
bits : 7 - 14 (8 bit)
access : write


SC7I2C_CLKL

IIC Clock Low Level Frequency Setting Register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7I2C_CLKL SC7I2C_CLKL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SCL_SETL __reserve0

SCL_SETL : Low level period of transfer clock at master communication [IIC] (*1)(*2)(*3)
bits : 0 - 6 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read


BRTM_S7_MODE

Baud Rate Timer 7 Operation Mode Setting Register
address_offset : 0x500 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

BRTM_S7_MODE BRTM_S7_MODE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 S7_MODE __reserve0

S7_MODE : Baud rate timer output clock duty setting (High-level : Low-level)
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 8 (8 bit)
access : read


BRTM_S7_EN

Baud Rate Timer 7 Operation Enable Register
address_offset : 0x501 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

BRTM_S7_EN BRTM_S7_EN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 S7_EN __reserve0

S7_EN : Baud rate timer operation enable.
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 8 (8 bit)
access : read


BRTM_S7_CK

Baud Rate Timer 7 Count Clock Selection Register
address_offset : 0x504 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

BRTM_S7_CK BRTM_S7_CK read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 S7_CK __reserve0

S7_CK : Clock selection of baud rate timer 0
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read


BRTM_S7_OC

Baud Rate Timer 7 Compare Register
address_offset : 0x50C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

BRTM_S7_OC BRTM_S7_OC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 S7_OC

S7_OC : Set the value to be compared with the counter of baud rate timer.
bits : 0 - 7 (8 bit)
access : read-write


SC7I2C_1STADR

IIC Slave Address Setting Register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7I2C_1STADR SC7I2C_1STADR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 __reserve0 SLV_ADR

__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read

SLV_ADR : Set the slave address. [IIC] (*1)(*2)
bits : 1 - 8 (8 bit)
access : read-write


SC7CI2C_CTR0

IIC Control Clear Register 0
address_offset : 0x60 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7CI2C_CTR0 SC7CI2C_CTR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SDA_FIXL SCL_FIXL __reserve0 __reserve1 __reserve2 ADREXC_SEL ADRNG_SEL ADROK_SEL

SDA_FIXL : Clear SC7I2C_CTR0.SDA_FIXL bit to 0
bits : 0 - 0 (1 bit)
access : write

SCL_FIXL : Clear SC7I2C_CTR0.SCL_FIXL bit to 0
bits : 1 - 2 (2 bit)
access : write

__reserve0 : This bit must be set to 0 .
bits : 2 - 4 (3 bit)
access : write

__reserve1 : This bit must be set to 0 .
bits : 3 - 6 (4 bit)
access : write

__reserve2 : This bit must be set to 0 .
bits : 4 - 8 (5 bit)
access : write

ADREXC_SEL : Clear SC7I2C_CTR0.ADREXC_SEL bit to 0
bits : 5 - 10 (6 bit)
access : write

ADRNG_SEL : Clear SC7I2C_CTR0.ADRNG_SEL bit to 0
bits : 6 - 12 (7 bit)
access : write

ADROK_SEL : Clear SC7I2C_CTR0.ADROK_SEL bit to 0
bits : 7 - 14 (8 bit)
access : write


SC7CI2C_CTR1

IIC Control Clear Register 1
address_offset : 0x61 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7CI2C_CTR1 SC7CI2C_CTR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TEXT_ON TOUT_ON SCLH_SEL SCLH_ON LPW_LMTSEL LPW_ON __reserve0

TEXT_ON : Clear SC7I2C_CTR1.TEXT_ON bit to 0 .
bits : 0 - 0 (1 bit)
access : write

TOUT_ON : Clear SC7I2C_CTR1.TOUT_ON bit to 0 .
bits : 1 - 2 (2 bit)
access : write

SCLH_SEL : Clear SC7I2C_CTR1.SCLH_SEL bit to 0 .
bits : 2 - 5 (4 bit)
access : write

SCLH_ON : Clear SC7I2C_CTR1.SCLH_ON bit to 0 .
bits : 4 - 8 (5 bit)
access : write

LPW_LMTSEL : Clear SC7I2C_CTR1.LPW_LMTSEL bit to 0 .
bits : 5 - 10 (6 bit)
access : write

LPW_ON : Clear SC7I2C_CTR1.LPW_ONL bit to 0
bits : 6 - 12 (7 bit)
access : write

__reserve0 : This bit must be set to 0 .
bits : 7 - 14 (8 bit)
access : write


SC7CI2C_CTR2

IIC Control Clear Register 2
address_offset : 0x62 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7CI2C_CTR2 SC7CI2C_CTR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 __reserve0 __reserve1 TRANS_END ACK_SET RWS_MST STOP_EN START_EN __reserve2

__reserve0 : This bit must be set to 0 .
bits : 0 - 0 (1 bit)
access : write

__reserve1 : This bit must be set to 0 .
bits : 1 - 2 (2 bit)
access : write

TRANS_END : Set SC7I2C_CTR2.TRANS_ENDL bit to 0 .
bits : 2 - 4 (3 bit)
access : write

ACK_SET : Set SC7I2C_CTR2.ACK_SETL bit to 0 .
bits : 3 - 6 (4 bit)
access : write

RWS_MST : Set SC7I2C_CTR2.RWS_MSTL bit to 0 .
bits : 4 - 8 (5 bit)
access : write

STOP_EN : Set SC7I2C_CTR2.STOP_ENL bit to 0 .
bits : 5 - 10 (6 bit)
access : write

START_EN : Set SC7I2C_CTR2.START_ENL bit to 0 .
bits : 6 - 12 (7 bit)
access : write

__reserve2 : This bit must be set to 0 .
bits : 7 - 14 (8 bit)
access : write


SC7CI2C_IRQCTR

IIC Interrupt Control Clear Register
address_offset : 0x63 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7CI2C_IRQCTR SC7CI2C_IRQCTR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACKDONE_IE BYTEDONE_IE STOP_IE START_IE ADRNG_IE TOUT_IE WKUP_IE WKUP_SEL

ACKDONE_IE : Clear SC7I2C_IRQCTR.ACKDONE_IE bit to 0 .
bits : 0 - 0 (1 bit)
access : write

BYTEDONE_IE : Clear SC7I2C_IRQCTR.BYTEDONE_IE bit to 0 .
bits : 1 - 2 (2 bit)
access : write

STOP_IE : Clear SC7I2C_IRQCTR.STOP_IE bit to 0 .
bits : 2 - 4 (3 bit)
access : write

START_IE : Clear SC7I2C_IRQCTR.START_IE bit to 0 .
bits : 3 - 6 (4 bit)
access : write

ADRNG_IE : Clear SC7I2C_IRQCTR.ADRNG_IE bit to 0 .
bits : 4 - 8 (5 bit)
access : write

TOUT_IE : Clear SC7I2C_IRQCTR.TOUT_IE bit to 0 .
bits : 5 - 10 (6 bit)
access : write

WKUP_IE : Clear SC7I2C_IRQCTR.WKUP_IE bit to 0 .
bits : 6 - 12 (7 bit)
access : write

WKUP_SEL : Clear SC7I2C_IRQCTR.WKUP_SEL bit to 0 .
bits : 7 - 14 (8 bit)
access : write


SC7CSYNC_CTR0

Clock-Synchronous Control Clear Register
address_offset : 0x68 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7CSYNC_CTR0 SC7CSYNC_CTR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SBCSLV SBCSEN CKPH CE1 FDC __reserve0

SBCSLV : Clear SC7SYNC_CTR0.SBCSLV bit to 0 .
bits : 0 - 0 (1 bit)
access : write

SBCSEN : Clear SC7SYNC_CTR0.SBCSEN bit to 0 .
bits : 1 - 2 (2 bit)
access : write

CKPH : Clear SC7SYNC_CTR0.CKPH bit to 0 .
bits : 2 - 4 (3 bit)
access : write

CE1 : Clear SC7SYNC_CTR0.CE1 bit to 0 .
bits : 3 - 6 (4 bit)
access : write

FDC : This bit must be set to 00 .
bits : 4 - 9 (6 bit)
access : write

__reserve0 : This bit must be set to 00 .
bits : 6 - 13 (8 bit)
access : write


SC7CUART_CTR

UART Control Clear Register
address_offset : 0x6A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7CUART_CTR SC7CUART_CTR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BRKE BRKF __reserve0 NPE PM FM __reserve1

BRKE : Clear SC7UART_CTR.BRKE bit to 0
bits : 0 - 0 (1 bit)
access : write

BRKF : This bit must be set to 0 .
bits : 1 - 2 (2 bit)
access : write

__reserve0 : This bit must be set to 0 .
bits : 2 - 4 (3 bit)
access : write

NPE : Clear SC7UART_CTR.NPE bit to 0
bits : 3 - 6 (4 bit)
access : write

PM : Clear SC7UART_CTR.PM bit to 0
bits : 4 - 9 (6 bit)
access : write

FM : Clear SC7UART_CTR.FM bit to 0
bits : 6 - 12 (7 bit)
access : write

__reserve1 : This bit must be set to 0 .
bits : 7 - 14 (8 bit)
access : write


SC7C_CTR0

Serial 7 Control Clear Register 0
address_offset : 0x6C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7C_CTR0 SC7C_CTR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SBOS SBIS IOM CKM CMD DIR MST

SBOS : Clear SC7_CTR0.SBOS bit to 0 .
bits : 0 - 0 (1 bit)
access : write

SBIS : Clear SC7_CTR0.SBIS bit to 0 .
bits : 1 - 2 (2 bit)
access : write

IOM : Clear SC7_CTR0.IOM bit to 0 .
bits : 2 - 4 (3 bit)
access : write

CKM : Clear SC7_CTR0.CKM bit to 0 .
bits : 3 - 6 (4 bit)
access : write

CMD : This bit must be set to 00 .
bits : 4 - 9 (6 bit)
access : write

DIR : Clear SC7_CTR0.DIR bit to 0 .
bits : 6 - 12 (7 bit)
access : write

MST : Clear SC7_CTR0.MST bit to 0 .
bits : 7 - 14 (8 bit)
access : write


SC7C_CTR1

Serial 7 Control Clear Register 1
address_offset : 0x6D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7C_CTR1 SC7C_CTR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 STREQ TRGSEL DIV LNG __reserve0

STREQ : This bit must be set to 0 .
bits : 0 - 0 (1 bit)
access : write

TRGSEL : This bit must be set to 00 .
bits : 1 - 3 (3 bit)
access : write

DIV : Clear SC7_CTR1.DIV bit to 0 .
bits : 3 - 6 (4 bit)
access : write

LNG : This bit must be set to 000 .
bits : 4 - 10 (7 bit)
access : write

__reserve0 : This bit must be set to 0 .
bits : 7 - 14 (8 bit)
access : write


SC7C_RST

Serial 7 Reset Clear Register
address_offset : 0x6E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7C_RST SC7C_RST read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RSTN RSRN __reserve0

RSTN : Clear SC7_RST.RSTN bit to 0
bits : 0 - 0 (1 bit)
access : write

RSRN : Clear SC7_RST.RSRN bit to 0
bits : 1 - 2 (2 bit)
access : write

__reserve0 : This bit must be set to 0 .
bits : 2 - 9 (8 bit)
access : write


SC7I2C_TCLKOC

IIC Timeout Clock Compare Register
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7I2C_TCLKOC SC7I2C_TCLKOC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TCLKOC __reserve0

TCLKOC : Time-out clock source division counter compare setting [IIC] (*1)(*2)
bits : 0 - 6 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read


SC7SYNC_CTR0

Clock-Synchronous Control Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7SYNC_CTR0 SC7SYNC_CTR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SBCSLV SBCSEN CKPH CE1 FDC __reserve0

SBCSLV : SBCS7 polarity selection [Clock-Synchronous]
bits : 0 - 0 (1 bit)
access : read-write

SBCSEN : SBCSn function selection [Clock-Synchronous]
bits : 1 - 2 (2 bit)
access : read-write

CKPH : Clock Source Edge Selection [Clock-Synchronous]
bits : 2 - 4 (3 bit)
access : read-write

CE1 : Clock polarity selection (SBT7) [Clock-Synchronous]
bits : 3 - 6 (4 bit)
access : read-write

FDC : Output level selection after the final bit transmit (SBO7 pin) [Clock-Synchronous]
bits : 4 - 9 (6 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 6 - 13 (8 bit)
access : read


SC7UART_CTR

UART Control Register
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7UART_CTR SC7UART_CTR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BRKE BRKF __reserve0 NPE PM FM __reserve1

BRKE : Break transmission control [UART]
bits : 0 - 0 (1 bit)
access : read-write

BRKF : Break reception detection [UART]
bits : 1 - 2 (2 bit)
access : read

__reserve0 : 0 is always read out.
bits : 2 - 4 (3 bit)
access : read

NPE : Parity bit selection [UART]
bits : 3 - 6 (4 bit)
access : read-write

PM : Parity bit function selection [UART]
bits : 4 - 9 (6 bit)
access : read-write

FM : The number of character bit and stop bit selection [UART]
bits : 6 - 12 (7 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read


SC7_CTR0

Serial 7 control register 0
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7_CTR0 SC7_CTR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SBOS SBIS IOM CKM CMD DIR MST

SBOS : SBOn(SDAn) pin output control (*2)
bits : 0 - 0 (1 bit)
access : read-write

SBIS : SBIn/SBOn(SDAn) pin input control (*2)
bits : 1 - 2 (2 bit)
access : read-write

IOM : Data input pin selection (*2)
bits : 2 - 4 (3 bit)
access : read-write

CKM : [Clock-Synchronous] Division selection of transfer clock
bits : 3 - 6 (4 bit)
access : read-write

CMD : Communication mode selection
bits : 4 - 9 (6 bit)
access : read-write

DIR : Transfer first bit selection
bits : 6 - 12 (7 bit)
access : read-write

MST : [Clock-Synchronous]
bits : 7 - 14 (8 bit)
access : read-write


SC7_CTR1

Serial 7 control register 1
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7_CTR1 SC7_CTR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 STREQ TRGSEL DIV LNG __reserve0

STREQ : Communication start trigger by software (*1)(*2)
bits : 0 - 0 (1 bit)
access : read

TRGSEL : Selection of communication start factor(*1)
bits : 1 - 3 (3 bit)
access : read-write

DIV : Division value selection of transfer clock
bits : 3 - 6 (4 bit)
access : read-write

LNG : Transfer bit count settings [Clock-Synchronous/UART]
bits : 4 - 10 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read


SC7_RST

Serial 7 Reset Register
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

SC7_RST SC7_RST read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RSTN RSRN __reserve0

RSTN : [Clock-Synchronous / IIC]
bits : 0 - 0 (1 bit)
access : read-write

RSRN : [Clock-Synchronous]
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 00 is always read out.
bits : 2 - 9 (8 bit)
access : read



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