\n

CAN

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x960 byte (0x0)
mem_usage : registers
protection :

Registers

CAN0_CREL

CAN0_TEST

CAN0_RWD

CAN0_CCCR

CAN0_NBTP

CAN0_TSCC

CAN1_CREL

CAN1_DBTP

CAN1_TEST

CAN1_RWD

CAN1_CCCR

CAN1_NBTP

CAN1_TSCC

CAN1_TSCV

CAN1_TOCC

CAN1_TOCV

CAN0_TSCV

CAN1_ECR

CAN1_PSR

CAN1_TDCR

CAN1_IR

CAN1_IE

CAN1_ILS

CAN1_ILE

CAN0_TOCC

CAN1_GFC

CAN1_SIDFC

CAN1_XIDFC

CAN1_XIDAM

CAN1_HPMS

CAN1_NDAT1

CAN1_NDAT2

CAN1_RXF0C

CAN1_RXF0S

CAN1_RXF0A

CAN1_RXBC

CAN1_RXF1C

CAN1_RXF1S

CAN1_RXF1A

CAN1_RXESC

CAN0_TOCV

CAN1_TXBC

CAN1_TXFQS

CAN1_TXESC

CAN1_TXBRP

CAN1_TXBAR

CAN1_TXBCR

CAN1_TXBTO

CAN1_TXBCF

CAN1_TXBTIE

CAN1_TXBCIE

CAN1_TXEFC

CAN1_TXEFS

CAN1_TXEFA

CAN0_ECR

CAN0_PSR

CAN0_TDCR

CAN0_IR

CAN0_IE

CAN0_ILS

CAN0_ILE

CAN0_GFC

CANC_EXTS_CNTEN

CANC_EXTS_CNTDT

CANC_EXTS_CNTCLR

CANC_EXTS_DIV

CANC_EXTS_CMP

CANC_DBGMSG_CNT

CAN0_SIDFC

CAN0_XIDFC

CAN0_XIDAM

CANC_ECCCTRL

CANC_ECCST

CANC_ECCRAM_DBGSEL

CANC_ECCRAM_DBG

CANC_ERR_MULTPL_ADDR

CANC_ERR_MULTPL_DATA

CANC_ERR_MULTPL_SYND

CANC_ERR_DETECT_ADDR_0

CANC_ERR_DETECT_DATA_0

CANC_ERR_DETECT_SYND_0

CANC_ERR_DETECT_EBIT_0

CANC_ERR_DETECT_ADDR_1

CANC_ERR_DETECT_DATA_1

CANC_ERR_DETECT_SYND_1

CANC_ERR_DETECT_EBIT_1

CAN0_HPMS

CANC_ERR_DETECT_ADDR_2

CANC_ERR_DETECT_DATA_2

CANC_ERR_DETECT_SYND_2

CANC_ERR_DETECT_EBIT_2

CANC_ERR_DETECT_ADDR_3

CANC_ERR_DETECT_DATA_3

CANC_ERR_DETECT_SYND_3

CANC_ERR_DETECT_EBIT_3

CAN0_NDAT1

CAN0_NDAT2

CAN0_RXF0C

CAN0_RXF0S

CAN0_RXF0A

CAN0_RXBC

CAN0_RXF1C

CAN0_RXF1S

CAN0_RXF1A

CAN0_RXESC

CAN0_DBTP

CAN0_TXBC

CAN0_TXFQS

CAN0_TXESC

CAN0_TXBRP

CAN0_TXBAR

CAN0_TXBCR

CAN0_TXBTO

CAN0_TXBCF

CAN0_TXBTIE

CAN0_TXBCIE

CAN0_TXEFC

CAN0_TXEFS

CAN0_TXEFA


CAN0_CREL

CAN0 Core Release Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_CREL CAN0_CREL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAY MON YEAR SUBSTEP STEP REL

DAY : Time Stamp Day
bits : 0 - 7 (8 bit)
access : read

MON : Time Stamp Month
bits : 8 - 23 (16 bit)
access : read

YEAR : Time Stamp Year
bits : 16 - 35 (20 bit)
access : read

SUBSTEP : Sub-step of Core Release
bits : 20 - 43 (24 bit)
access : read

STEP : Step of Core Release
bits : 24 - 51 (28 bit)
access : read

REL : Core Release Version
bits : 28 - 59 (32 bit)
access : read


CAN0_TEST

CAN0 Test Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_TEST CAN0_TEST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 LBCK TX RX __reserve1

__reserve0 : 0 is always read out.
bits : 0 - 3 (4 bit)
access : read

LBCK : Loop Back Mode
bits : 4 - 8 (5 bit)
access : read-write

TX : Control of Transmit Pin CTX (*1)
bits : 5 - 11 (7 bit)
access : read-write

RX : Monitors the actual value of CRX pin
bits : 7 - 14 (8 bit)
access : read

__reserve1 : 0 is always read out.
bits : 8 - 39 (32 bit)
access : read


CAN0_RWD

CAN0 RAM Watchdog Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_RWD CAN0_RWD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDC WDV __reserve0

WDC : Watchdog Configuration
bits : 0 - 7 (8 bit)
access : read-write

WDV : Watchdog Value
bits : 8 - 23 (16 bit)
access : read

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


CAN0_CCCR

CAN0 CC Co0trol Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_CCCR CAN0_CCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT CCE ASM CSA CSR MON DAR TEST FDOE BRSE __reserve0 PXHD EFBI TXP NISO __reserve1

INIT : Initialization (*5)
bits : 0 - 0 (1 bit)
access : read-write

CCE : Configuration Change Enable (*1)(*4)
bits : 1 - 2 (2 bit)
access : read-write

ASM : Restricted Operation Mode (*2)
bits : 2 - 4 (3 bit)
access : read-write

CSA : Clock Stop Acknowledge
bits : 3 - 6 (4 bit)
access : read

CSR : Clock Stop Request (*3)
bits : 4 - 8 (5 bit)
access : read-write

MON : Bus Monitoring Mode (*2)
bits : 5 - 10 (6 bit)
access : read-write

DAR : Disable Automatic Retransmission (*1)
bits : 6 - 12 (7 bit)
access : read-write

TEST : Test Mode Enable (*2)
bits : 7 - 14 (8 bit)
access : read-write

FDOE : CAN FD Operation Enable (*1)
bits : 8 - 16 (9 bit)
access : read-write

BRSE : Bit Rate Switch Enable (*1)
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 21 (12 bit)
access : read

PXHD : Protocol Exception Handling Disable (*1)
bits : 12 - 24 (13 bit)
access : read-write

EFBI : Edge Filtering during Bus Integration (*1)
bits : 13 - 26 (14 bit)
access : read-write

TXP : Transmit Pause
bits : 14 - 28 (15 bit)
access : read-write

NISO : Non ISO Operation (*1)
bits : 15 - 30 (16 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


CAN0_NBTP

CAN0 Nomi0al Bit Timi0g and Prescaler Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_NBTP CAN0_NBTP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NTSEG2 __reserve0 NTSEG1 NBRP NSJW

NTSEG2 : Nominal Time segment (TSEG2) after sample point
bits : 0 - 6 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read

NTSEG1 : Nominal Time segment (TSEG1) before sample point
bits : 8 - 23 (16 bit)
access : read-write

NBRP : Nominal Bit Rate Prescaler
bits : 16 - 40 (25 bit)
access : read-write

NSJW : Nominal (Re)Synchronization Jump Width
bits : 25 - 56 (32 bit)
access : read-write


CAN0_TSCC

CAN0 Timestamp Cou0ter Co0figuratio0 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_TSCC CAN0_TSCC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSS __reserve0 TCP __reserve1

TSS : Timestamp Selection
bits : 0 - 1 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read

TCP : Timestamp Counter Prescaler
bits : 16 - 35 (20 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 20 - 51 (32 bit)
access : read


CAN1_CREL

CAN1 Core Release Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_CREL CAN1_CREL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAY MON YEAR SUBSTEP STEP REL

DAY : Time Stamp Day
bits : 0 - 7 (8 bit)
access : read

MON : Time Stamp Month
bits : 8 - 23 (16 bit)
access : read

YEAR : Time Stamp Year
bits : 16 - 35 (20 bit)
access : read

SUBSTEP : Sub-step of Core Release
bits : 20 - 43 (24 bit)
access : read

STEP : Step of Core Release
bits : 24 - 51 (28 bit)
access : read

REL : Core Release Version
bits : 28 - 59 (32 bit)
access : read


CAN1_DBTP

CAN1 Data Bit Timi1g and Prescaler Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_DBTP CAN1_DBTP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSJW DTSEG2 DTSEG1 __reserve0 DBRP __reserve1 TDC __reserve2

DSJW : Data (Re)Synchronization Jump Width
bits : 0 - 3 (4 bit)
access : read-write

DTSEG2 : Data time segment after sample point
bits : 4 - 11 (8 bit)
access : read-write

DTSEG1 : Data time segment before sample point
bits : 8 - 20 (13 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 13 - 28 (16 bit)
access : read

DBRP : Data Bit Rate Prescaler (*1)
bits : 16 - 36 (21 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 21 - 43 (23 bit)
access : read

TDC : Transmitter Delay Compensation
bits : 23 - 46 (24 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 24 - 55 (32 bit)
access : read


CAN1_TEST

CAN1 Test Register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_TEST CAN1_TEST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 LBCK TX RX __reserve1

__reserve0 : 0 is always read out.
bits : 0 - 3 (4 bit)
access : read

LBCK : Loop Back Mode
bits : 4 - 8 (5 bit)
access : read-write

TX : Control of Transmit Pin CTX (*1)
bits : 5 - 11 (7 bit)
access : read-write

RX : Monitors the actual value of CRX pin
bits : 7 - 14 (8 bit)
access : read

__reserve1 : 0 is always read out.
bits : 8 - 39 (32 bit)
access : read


CAN1_RWD

CAN1 RAM Watchdog Register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_RWD CAN1_RWD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDC WDV __reserve0

WDC : Watchdog Configuration
bits : 0 - 7 (8 bit)
access : read-write

WDV : Watchdog Value
bits : 8 - 23 (16 bit)
access : read

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


CAN1_CCCR

CAN1 CC Co1trol Register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_CCCR CAN1_CCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT CCE ASM CSA CSR MON DAR TEST FDOE BRSE __reserve0 PXHD EFBI TXP NISO __reserve1

INIT : Initialization (*5)
bits : 0 - 0 (1 bit)
access : read-write

CCE : Configuration Change Enable (*1)(*4)
bits : 1 - 2 (2 bit)
access : read-write

ASM : Restricted Operation Mode (*2)
bits : 2 - 4 (3 bit)
access : read-write

CSA : Clock Stop Acknowledge
bits : 3 - 6 (4 bit)
access : read

CSR : Clock Stop Request (*3)
bits : 4 - 8 (5 bit)
access : read-write

MON : Bus Monitoring Mode (*2)
bits : 5 - 10 (6 bit)
access : read-write

DAR : Disable Automatic Retransmission (*1)
bits : 6 - 12 (7 bit)
access : read-write

TEST : Test Mode Enable (*2)
bits : 7 - 14 (8 bit)
access : read-write

FDOE : CAN FD Operation Enable (*1)
bits : 8 - 16 (9 bit)
access : read-write

BRSE : Bit Rate Switch Enable (*1)
bits : 9 - 18 (10 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 10 - 21 (12 bit)
access : read

PXHD : Protocol Exception Handling Disable (*1)
bits : 12 - 24 (13 bit)
access : read-write

EFBI : Edge Filtering during Bus Integration (*1)
bits : 13 - 26 (14 bit)
access : read-write

TXP : Transmit Pause
bits : 14 - 28 (15 bit)
access : read-write

NISO : Non ISO Operation (*1)
bits : 15 - 30 (16 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


CAN1_NBTP

CAN1 Nomi1al Bit Timi1g and Prescaler Register
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_NBTP CAN1_NBTP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NTSEG2 __reserve0 NTSEG1 NBRP NSJW

NTSEG2 : Nominal Time segment (TSEG2) after sample point
bits : 0 - 6 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read

NTSEG1 : Nominal Time segment (TSEG1) before sample point
bits : 8 - 23 (16 bit)
access : read-write

NBRP : Nominal Bit Rate Prescaler
bits : 16 - 40 (25 bit)
access : read-write

NSJW : Nominal (Re)Synchronization Jump Width
bits : 25 - 56 (32 bit)
access : read-write


CAN1_TSCC

CAN1 Timestamp Cou1ter Co1figuratio1 Register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_TSCC CAN1_TSCC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSS __reserve0 TCP __reserve1

TSS : Timestamp Selection
bits : 0 - 1 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read

TCP : Timestamp Counter Prescaler
bits : 16 - 35 (20 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 20 - 51 (32 bit)
access : read


CAN1_TSCV

CAN1 Timestamp Cou1ter Value Register
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_TSCV CAN1_TSCV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSC __reserve0

TSC : Timestamp Counter
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


CAN1_TOCC

CAN1 Timeout Cou1ter Co1figuratio1 Register
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_TOCC CAN1_TOCC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETOC TOS __reserve0 TOP

ETOC : Enable Timeout Counter
bits : 0 - 0 (1 bit)
access : read-write

TOS : Timeout Counter Operation mode Selection
bits : 1 - 3 (3 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 3 - 18 (16 bit)
access : read

TOP : Start value of the Timeout Counter (down-counter). Configures the Timeout Period.
bits : 16 - 47 (32 bit)
access : read-write


CAN1_TOCV

CAN1 Timeout Cou1ter Value Register
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_TOCV CAN1_TOCV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOC __reserve0

TOC : Timeout Counter Value
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


CAN0_TSCV

CAN0 Timestamp Cou0ter Value Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_TSCV CAN0_TSCV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSC __reserve0

TSC : Timestamp Counter
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


CAN1_ECR

CAN1 Error Cou1ter Register
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_ECR CAN1_ECR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEC REC RP CEL __reserve0

TEC : Transmit Error Counter
bits : 0 - 7 (8 bit)
access : read

REC : Receive Error Counter
bits : 8 - 22 (15 bit)
access : read

RP : Receive Error Passive
bits : 15 - 30 (16 bit)
access : read

CEL : CAN Error Logging (*1)
bits : 16 - 39 (24 bit)
access : read

__reserve0 : 0 is always read out.
bits : 24 - 55 (32 bit)
access : read


CAN1_PSR

CAN1 Protocol Status Register
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_PSR CAN1_PSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEC ACT EP EW BO DLEC RESI RBRS RFDF PXE __reserve0 TDCV __reserve1

LEC : Last error code to occur on the CAN bus.(*4)(*5)
bits : 0 - 2 (3 bit)
access : read

ACT : Activity
bits : 3 - 7 (5 bit)
access : read

EP : CANn Error Passive
bits : 5 - 10 (6 bit)
access : read

EW : Warning Status
bits : 6 - 12 (7 bit)
access : read

BO : Bus_Off Status
bits : 7 - 14 (8 bit)
access : read

DLEC : Data Phase Last Error Code
bits : 8 - 18 (11 bit)
access : read

RESI : ESI flag of last received CAN FD Message (*1)
bits : 11 - 22 (12 bit)
access : read

RBRS : BRS flag of last received CAN FD Message (*1)
bits : 12 - 24 (13 bit)
access : read

RFDF : Received a CAN FD Message (*1)
bits : 13 - 26 (14 bit)
access : read

PXE : Protocol Exception Event (*1)
bits : 14 - 28 (15 bit)
access : read

__reserve0 : 0 is always read out.
bits : 15 - 30 (16 bit)
access : read

TDCV : Transmitter Delay Compensation Value (Position of the secondary sample point)
bits : 16 - 38 (23 bit)
access : read

__reserve1 : 0 is always read out.
bits : 23 - 54 (32 bit)
access : read


CAN1_TDCR

CAN1 Tra1smitter Delay Compe1satio1 Register
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_TDCR CAN1_TDCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDCF __reserve0 TDCO __reserve1

TDCF : Transmitter Delay Compensation Filter Window Length (*1)
bits : 0 - 6 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read

TDCO : Transmitter Delay Compensation Offset
bits : 8 - 22 (15 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 15 - 46 (32 bit)
access : read


CAN1_IR

CAN1 I1terrupt Factor Register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_IR CAN1_IR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RF0N RF0W RF0F RF0L RF1N RF1W RF1F RF1L HPM TC TCF TFE TEFN TEFW TEFF TEFL TSW MRAF TOO DRX BEC BEU ELO EP EW BO WDI PEA PED ARA __reserve0

RF0N : Rx FIFO 0 New Message Interrupt factor
bits : 0 - 0 (1 bit)
access : read-write

RF0W : Rx FIFO 0 Watermark Reached Interrupt factor
bits : 1 - 2 (2 bit)
access : read-write

RF0F : Rx FIFO 0 Full Interrupt factor
bits : 2 - 4 (3 bit)
access : read-write

RF0L : Rx FIFO 0 Message Lost Interrupt factor
bits : 3 - 6 (4 bit)
access : read-write

RF1N : Rx FIFO 1 New Message Interrupt factor
bits : 4 - 8 (5 bit)
access : read-write

RF1W : Rx FIFO 1 Watermark Reached Interrupt factor
bits : 5 - 10 (6 bit)
access : read-write

RF1F : Rx FIFO 1 Full Interrupt factor
bits : 6 - 12 (7 bit)
access : read-write

RF1L : Rx FIFO 1 Message Lost Interrupt factor
bits : 7 - 14 (8 bit)
access : read-write

HPM : High Priority Message Interrupt factor
bits : 8 - 16 (9 bit)
access : read-write

TC : Transmission Completed Interrupt factor
bits : 9 - 18 (10 bit)
access : read-write

TCF : Transmission Cancellation Finished Interrupt factor
bits : 10 - 20 (11 bit)
access : read-write

TFE : Tx FIFO Empty Interrupt factor
bits : 11 - 22 (12 bit)
access : read-write

TEFN : Tx Event FIFO New Entry Interrupt factor
bits : 12 - 24 (13 bit)
access : read-write

TEFW : Tx Event FIFO Watermark Reached Interrupt factor
bits : 13 - 26 (14 bit)
access : read-write

TEFF : Tx Event FIFO Full Interrupt factor
bits : 14 - 28 (15 bit)
access : read-write

TEFL : Tx Event FIFO Element Lost Interrupt factor
bits : 15 - 30 (16 bit)
access : read-write

TSW : Timestamp Wraparound Interrupt factor
bits : 16 - 32 (17 bit)
access : read-write

MRAF : Message RAM Access Failure Interrupt factor
bits : 17 - 34 (18 bit)
access : read-write

TOO : Timeout Occurred Interrupt factor
bits : 18 - 36 (19 bit)
access : read-write

DRX : Message stored to Dedicated Rx Buffer Interrupt factor
bits : 19 - 38 (20 bit)
access : read-write

BEC : Bit Error Corrected Interrupt factor
bits : 20 - 40 (21 bit)
access : read-write

BEU : Bit Error Uncorrected Interrupt factor
bits : 21 - 42 (22 bit)
access : read-write

ELO : Error Logging Overflow Interrupt factor
bits : 22 - 44 (23 bit)
access : read-write

EP : Error Passive Interrupt factor
bits : 23 - 46 (24 bit)
access : read-write

EW : Warning Status Interrupt factor
bits : 24 - 48 (25 bit)
access : read-write

BO : Bus_Off Status Interrupt factor
bits : 25 - 50 (26 bit)
access : read-write

WDI : Watchdog Interrupt factor
bits : 26 - 52 (27 bit)
access : read-write

PEA : Protocol Error in Arbitration Phase Interrupt factor (Nominal Bit Time is used)
bits : 27 - 54 (28 bit)
access : read-write

PED : Protocol Error in Data Phase Interrupt factor (Data Bit Time is used)
bits : 28 - 56 (29 bit)
access : read-write

ARA : Access to Reserved Address Interrupt factor
bits : 29 - 58 (30 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 30 - 61 (32 bit)
access : read


CAN1_IE

CAN1 I1terrupt Factor E1able Register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_IE CAN1_IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RF0NE RF0WE RF0FE RF0LE RF1NE RF1WE RF1FE RF1LE HPME TCE TCFE TFEE TEFNE TEFWE TEFFE TEFLE TSWE MRAFE TOOE DRXE BECE BEUE ELOE EPE EWE BOE WDIE PEAE PEDE ARAE __reserve0

RF0NE : Rx FIFO 0 New Message Interrupt Factor Enable
bits : 0 - 0 (1 bit)
access : read-write

RF0WE : Rx FIFO 0 Watermark Reached Interrupt Factor Enable
bits : 1 - 2 (2 bit)
access : read-write

RF0FE : Rx FIFO 0 Full Interrupt Factor Enable
bits : 2 - 4 (3 bit)
access : read-write

RF0LE : Rx FIFO 0 Message Lost Interrupt Factor Enable
bits : 3 - 6 (4 bit)
access : read-write

RF1NE : Rx FIFO 1 New Message Interrupt Factor Enable
bits : 4 - 8 (5 bit)
access : read-write

RF1WE : Rx FIFO 1 Watermark Reached Interrupt Factor Enable
bits : 5 - 10 (6 bit)
access : read-write

RF1FE : Rx FIFO 1 Full Interrupt Factor Enable
bits : 6 - 12 (7 bit)
access : read-write

RF1LE : Rx FIFO 1 Message Lost Interrupt Factor Enable
bits : 7 - 14 (8 bit)
access : read-write

HPME : High Priority Message Interrupt Factor Enable
bits : 8 - 16 (9 bit)
access : read-write

TCE : Transmission Completed Interrupt Factor Enable
bits : 9 - 18 (10 bit)
access : read-write

TCFE : Transmission Cancellation Finished Interrupt Factor Enable
bits : 10 - 20 (11 bit)
access : read-write

TFEE : Tx FIFO Empty Interrupt Factor Enable
bits : 11 - 22 (12 bit)
access : read-write

TEFNE : Tx Event FIFO New Entry Interrupt Factor Enable
bits : 12 - 24 (13 bit)
access : read-write

TEFWE : Tx Event FIFO Watermark Reached Interrupt Factor Enable
bits : 13 - 26 (14 bit)
access : read-write

TEFFE : Tx Event FIFO Full Interrupt Factor Enable
bits : 14 - 28 (15 bit)
access : read-write

TEFLE : Tx Event FIFO Event Lost Interrupt Factor Enable
bits : 15 - 30 (16 bit)
access : read-write

TSWE : Timestamp Wraparound Interrupt Factor Enable
bits : 16 - 32 (17 bit)
access : read-write

MRAFE : Message RAM Access Failure Interrupt Factor Enable
bits : 17 - 34 (18 bit)
access : read-write

TOOE : Timeout Occurred Interrupt Factor Enable
bits : 18 - 36 (19 bit)
access : read-write

DRXE : Message stored to Dedicated Rx Buffer Interrupt Factor Enable
bits : 19 - 38 (20 bit)
access : read-write

BECE : Bit Error Corrected Interrupt Factor Enable
bits : 20 - 40 (21 bit)
access : read-write

BEUE : Bit Error Uncorrected Interrupt Factor Enable
bits : 21 - 42 (22 bit)
access : read-write

ELOE : Error Logging Overflow Interrupt Factor Enable
bits : 22 - 44 (23 bit)
access : read-write

EPE : Error Passive Interrupt Factor Enable
bits : 23 - 46 (24 bit)
access : read-write

EWE : Warning Status Interrupt Factor Enable
bits : 24 - 48 (25 bit)
access : read-write

BOE : Bus_Off Status Interrupt Factor Enable
bits : 25 - 50 (26 bit)
access : read-write

WDIE : Watchdog Interrupt Factor Enable
bits : 26 - 52 (27 bit)
access : read-write

PEAE : Protocol Error in Arbitration Phase Interrupt Factor Enable
bits : 27 - 54 (28 bit)
access : read-write

PEDE : Protocol Error in Data Phase Interrupt Factor Enable
bits : 28 - 56 (29 bit)
access : read-write

ARAE : Access to Reserved Address Interrupt Factor Enable
bits : 29 - 58 (30 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 30 - 61 (32 bit)
access : read


CAN1_ILS

CAN1 I1terrupt Li1e Select Register
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_ILS CAN1_ILS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RF0NL RF0WL RF0FL RF0LL RF1NL RF1WL RF1FL RF1LL HPML TCL TCFL TFEL TEFNL TEFWL TEFFL TEFLL TSWL MRAFL TOOL DRXL BECL BEUL ELOL EPL EWL BOL WDIL PEAL PEDL ARAL __reserve0

RF0NL : Rx FIFO 0 New Message Interrupt Line
bits : 0 - 0 (1 bit)
access : read-write

RF0WL : Rx FIFO 0 Watermark Reached Interrupt Line
bits : 1 - 2 (2 bit)
access : read-write

RF0FL : Rx FIFO 0 Full Interrupt Line
bits : 2 - 4 (3 bit)
access : read-write

RF0LL : Rx FIFO 0 Message Lost Interrupt Line
bits : 3 - 6 (4 bit)
access : read-write

RF1NL : Rx FIFO 1 New Message Interrupt Line
bits : 4 - 8 (5 bit)
access : read-write

RF1WL : Rx FIFO 1 Watermark Reached Interrupt Line
bits : 5 - 10 (6 bit)
access : read-write

RF1FL : Rx FIFO 1 Full Interrupt Line
bits : 6 - 12 (7 bit)
access : read-write

RF1LL : Rx FIFO 1 Message Lost Interrupt Line
bits : 7 - 14 (8 bit)
access : read-write

HPML : High Priority Message Interrupt Line
bits : 8 - 16 (9 bit)
access : read-write

TCL : Transmission Completed Interrupt Line
bits : 9 - 18 (10 bit)
access : read-write

TCFL : Transmission Cancellation Finished Interrupt Line
bits : 10 - 20 (11 bit)
access : read-write

TFEL : Tx FIFO Empty Interrupt Line
bits : 11 - 22 (12 bit)
access : read-write

TEFNL : Tx Event FIFO New Entry Interrupt Line
bits : 12 - 24 (13 bit)
access : read-write

TEFWL : Tx Event FIFO Watermark Reached Interrupt Line
bits : 13 - 26 (14 bit)
access : read-write

TEFFL : Tx Event FIFO Full Interrupt Line
bits : 14 - 28 (15 bit)
access : read-write

TEFLL : Tx Event FIFO Event Lost Interrupt Line
bits : 15 - 30 (16 bit)
access : read-write

TSWL : Timestamp Wraparound Interrupt Line
bits : 16 - 32 (17 bit)
access : read-write

MRAFL : Message RAM Access Failure Interrupt Line
bits : 17 - 34 (18 bit)
access : read-write

TOOL : Timeout Occurred Interrupt Line
bits : 18 - 36 (19 bit)
access : read-write

DRXL : Message stored to Dedicated Rx Buffer Interrupt Line
bits : 19 - 38 (20 bit)
access : read-write

BECL : Bit Error Corrected Interrupt Line
bits : 20 - 40 (21 bit)
access : read-write

BEUL : Bit Error Uncorrected Interrupt Line
bits : 21 - 42 (22 bit)
access : read-write

ELOL : Error Logging Overflow Interrupt Line
bits : 22 - 44 (23 bit)
access : read-write

EPL : Error Passive Interrupt Line
bits : 23 - 46 (24 bit)
access : read-write

EWL : Warning Status Interrupt Line
bits : 24 - 48 (25 bit)
access : read-write

BOL : Bus_Off Status Interrupt Line
bits : 25 - 50 (26 bit)
access : read-write

WDIL : Watchdog Interrupt Line
bits : 26 - 52 (27 bit)
access : read-write

PEAL : Protocol Error in Arbitration Phase Line
bits : 27 - 54 (28 bit)
access : read-write

PEDL : Protocol Error in Data Phase Line
bits : 28 - 56 (29 bit)
access : read-write

ARAL : Access to Reserved Address Line
bits : 29 - 58 (30 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 30 - 61 (32 bit)
access : read


CAN1_ILE

CAN1 I1terrupt Li1e E1able Register
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_ILE CAN1_ILE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EINT0 EINT1 __reserve0

EINT0 : Enable CANn-0 Interrupt
bits : 0 - 0 (1 bit)
access : read-write

EINT1 : Enable CANn-1 Interrupt
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 33 (32 bit)
access : read


CAN0_TOCC

CAN0 Timeout Cou0ter Co0figuratio0 Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_TOCC CAN0_TOCC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETOC TOS __reserve0 TOP

ETOC : Enable Timeout Counter
bits : 0 - 0 (1 bit)
access : read-write

TOS : Timeout Counter Operation mode Selection
bits : 1 - 3 (3 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 3 - 18 (16 bit)
access : read

TOP : Start value of the Timeout Counter (down-counter). Configures the Timeout Period.
bits : 16 - 47 (32 bit)
access : read-write


CAN1_GFC

CAN1 Global Filter Co1figuratio1 Register
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_GFC CAN1_GFC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRFE RRFS ANFE ANFS __reserve0

RRFE : Reject Remote Frames Extended Message ID (29-bit)
bits : 0 - 0 (1 bit)
access : read-write

RRFS : Reject Remote Frames Standard Message ID (11-bit)
bits : 1 - 2 (2 bit)
access : read-write

ANFE : Accept Non-matching Frames Extended Message ID (29-bit)
bits : 2 - 5 (4 bit)
access : read-write

ANFS : Accept Non-matching Frames Standard Message ID (11-bit)
bits : 4 - 9 (6 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 6 - 37 (32 bit)
access : read


CAN1_SIDFC

CAN1 Sta1dard ID Filter Co1figuratio1 Register
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_SIDFC CAN1_SIDFC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLSSA LSS __reserve0

FLSSA : Start address of Standard Message ID (11-bit) filter list (*1)
bits : 0 - 15 (16 bit)
access : read-write

LSS : List Size Standard Message ID (11-bit)
bits : 16 - 39 (24 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 24 - 55 (32 bit)
access : read


CAN1_XIDFC

CAN1 Exte1ded ID Filter Co1figuratio1 Register
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_XIDFC CAN1_XIDFC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLESA LSE __reserve0

FLESA : Start address of Extended Message ID (29-bit) filter list (*1)
bits : 0 - 15 (16 bit)
access : read-write

LSE : List Size Extended Message ID (29-bit)
bits : 16 - 38 (23 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 23 - 54 (32 bit)
access : read


CAN1_XIDAM

CAN1 Exte1ded ID AND Mask Register
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_XIDAM CAN1_XIDAM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EIDM __reserve0

EIDM : Extended Message ID Mask (*1)
bits : 0 - 28 (29 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 29 - 60 (32 bit)
access : read


CAN1_HPMS

CAN1 High Priority Message Status Register
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_HPMS CAN1_HPMS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIDX MSI FIDX FLST __reserve0

BIDX : Buffer Index
bits : 0 - 5 (6 bit)
access : read

MSI : Message Storage Indicator
bits : 6 - 13 (8 bit)
access : read

FIDX : Filter Index
bits : 8 - 22 (15 bit)
access : read

FLST : Filter List
bits : 15 - 30 (16 bit)
access : read

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


CAN1_NDAT1

CAN1 New Data 1 Register
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_NDAT1 CAN1_NDAT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ND1

ND1 : New Data flags of Rx Buffers 0 to 31 (bp0 to 31)
bits : 0 - 31 (32 bit)
access : read-write


CAN1_NDAT2

CAN1 New Data 2 Register
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_NDAT2 CAN1_NDAT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ND2

ND2 : New Data flags of Rx Buffers 32 to 63 (bp0 to 31)
bits : 0 - 31 (32 bit)
access : read-write


CAN1_RXF0C

CAN1 Rx FIFO 0 Co1figuratio1 Register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_RXF0C CAN1_RXF0C read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0SA F0S __reserve0 F0WM F0OM

F0SA : Start address of Rx FIFO 0 in Message RAM (*1)
bits : 0 - 15 (16 bit)
access : read-write

F0S : Rx FIFO 0 Size
bits : 16 - 38 (23 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 23 - 46 (24 bit)
access : read

F0WM : Rx FIFO 0 Watermark
bits : 24 - 54 (31 bit)
access : read-write

F0OM : FIFO 0 Operation Mode
bits : 31 - 62 (32 bit)
access : read-write


CAN1_RXF0S

CAN1 Rx FIFO 0 Status Register
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_RXF0S CAN1_RXF0S read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0FL __reserve0 F0GI __reserve1 F0PI __reserve2 F0F RF0L __reserve3

F0FL : Rx FIFO 0 Fill Level
bits : 0 - 6 (7 bit)
access : read

__reserve0 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read

F0GI : Rx FIFO 0 Get Index
bits : 8 - 21 (14 bit)
access : read

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read

F0PI : Rx FIFO 0 Put Index
bits : 16 - 37 (22 bit)
access : read

__reserve2 : 0 is always read out.
bits : 22 - 45 (24 bit)
access : read

F0F : Rx FIFO 0 Full
bits : 24 - 48 (25 bit)
access : read

RF0L : Rx FIFO 0 Message Lost (*1)(*2)
bits : 25 - 50 (26 bit)
access : read

__reserve3 : 0 is always read out.
bits : 26 - 57 (32 bit)
access : read


CAN1_RXF0A

CAN1 Rx FIFO 0 Ack1owledge Register
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_RXF0A CAN1_RXF0A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0AI __reserve0

F0AI : Rx FIFO 0 Acknowledge Index (*1)
bits : 0 - 5 (6 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 6 - 37 (32 bit)
access : read


CAN1_RXBC

CAN1 Rx Buffer Co1figuratio1 Register
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_RXBC CAN1_RXBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RBSA __reserve0

RBSA : Start address of Rx Buffers in Message RAM (*1)(*2)
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


CAN1_RXF1C

CAN1 Rx FIFO 1 Co1figuratio1 Register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_RXF1C CAN1_RXF1C read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F1SA F1S __reserve0 F1WM F1OM

F1SA : Start address of Rx FIFO 1 in Message RAM (*1)
bits : 0 - 15 (16 bit)
access : read-write

F1S : Rx FIFO 1 Size
bits : 16 - 38 (23 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 23 - 46 (24 bit)
access : read

F1WM : Rx FIFO 1 Watermark
bits : 24 - 54 (31 bit)
access : read-write

F1OM : Rx FIFO 1 Operation Mode
bits : 31 - 62 (32 bit)
access : read-write


CAN1_RXF1S

CAN1 Rx FIFO 1 Status Register
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_RXF1S CAN1_RXF1S read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F1FL __reserve0 F1GI __reserve1 F1PI __reserve2 F1F RF1L __reserve3 DMS

F1FL : Rx FIFO 1 Fill Level
bits : 0 - 6 (7 bit)
access : read

__reserve0 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read

F1GI : Rx FIFO 1 Get Index
bits : 8 - 21 (14 bit)
access : read

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read

F1PI : Rx FIFO 1 Put Index
bits : 16 - 37 (22 bit)
access : read

__reserve2 : 0 is always read out.
bits : 22 - 45 (24 bit)
access : read

F1F : Rx FIFO 1 Full
bits : 24 - 48 (25 bit)
access : read

RF1L : Rx FIFO 1 Message Lost (*1)(*2)
bits : 25 - 50 (26 bit)
access : read

__reserve3 : 0 is always read out.
bits : 26 - 55 (30 bit)
access : read

DMS : Debug Message Status
bits : 30 - 61 (32 bit)
access : read


CAN1_RXF1A

CAN1 Rx FIFO 1 Ack1owledge Register
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_RXF1A CAN1_RXF1A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F1AI __reserve0

F1AI : Rx FIFO 1 Acknowledge Index
bits : 0 - 5 (6 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 6 - 37 (32 bit)
access : read


CAN1_RXESC

CAN1 Rx Buffer/ FIFO Eleme1t Size Co1figuratio1 Register
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_RXESC CAN1_RXESC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0DS __reserve0 F1DS __reserve1 RBDS __reserve2

F0DS : Rx FIFO 0 Data Field Size (*1)
bits : 0 - 2 (3 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 3 - 6 (4 bit)
access : read

F1DS : Rx FIFO 1 Data Field Size (*1)
bits : 4 - 10 (7 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read

RBDS : Rx Buffer Data Field Size (*1)
bits : 8 - 18 (11 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 11 - 42 (32 bit)
access : read


CAN0_TOCV

CAN0 Timeout Cou0ter Value Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_TOCV CAN0_TOCV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOC __reserve0

TOC : Timeout Counter Value
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


CAN1_TXBC

CAN1 Tx Buffer Co1figuratio1 Register
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_TXBC CAN1_TXBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBSA NDTB __reserve0 TFQS TFQM __reserve1

TBSA : Start address of Tx Buffers in Message RAM (*2)(*3)
bits : 0 - 15 (16 bit)
access : read-write

NDTB : Number of Dedicated Tx Buffers (*1)
bits : 16 - 37 (22 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 22 - 45 (24 bit)
access : read

TFQS : Tx FIFO/Queue Size (*1)
bits : 24 - 53 (30 bit)
access : read-write

TFQM : Tx FIFO/Queue Mode
bits : 30 - 60 (31 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 31 - 62 (32 bit)
access : read


CAN1_TXFQS

CAN1 Tx FIFO/Queue Status Register
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_TXFQS CAN1_TXFQS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFFL __reserve0 TFGI __reserve1 TFQPI TFQF __reserve2

TFFL : Tx FIFO Free Level
bits : 0 - 5 (6 bit)
access : read

__reserve0 : 0 is always read out.
bits : 6 - 13 (8 bit)
access : read

TFGI : Tx FIFO Get Index (*1)
bits : 8 - 20 (13 bit)
access : read

__reserve1 : 0 is always read out.
bits : 13 - 28 (16 bit)
access : read

TFQPI : Tx FIFO/Queue Put Index
bits : 16 - 36 (21 bit)
access : read

TFQF : Tx FIFO/Queue Full
bits : 21 - 42 (22 bit)
access : read

__reserve2 : 0 is always read out.
bits : 22 - 53 (32 bit)
access : read


CAN1_TXESC

CAN1 Tx Buffer Eleme1t Size Co1figuratio1 Register
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_TXESC CAN1_TXESC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBDS __reserve0

TBDS : Tx Buffer Data Field Size (*1)
bits : 0 - 2 (3 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 3 - 34 (32 bit)
access : read


CAN1_TXBRP

CAN1 Tx Buffer Request Pe1di1g Register
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_TXBRP CAN1_TXBRP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRP

TRP : Transmission Request Pending
bits : 0 - 31 (32 bit)
access : read


CAN1_TXBAR

CAN1 Tx Buffer Add Request Register
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_TXBAR CAN1_TXBAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AR

AR : Add Request
bits : 0 - 31 (32 bit)
access : read-write


CAN1_TXBCR

CAN1 Tx Buffer Ca1cellatio1 Request Register
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_TXBCR CAN1_TXBCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CR

CR : Cancellation Request
bits : 0 - 31 (32 bit)
access : read-write


CAN1_TXBTO

CAN1 Tx Buffer Tra1smissio1 Occurred Register
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_TXBTO CAN1_TXBTO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TO

TO : Transmission Occurred
bits : 0 - 31 (32 bit)
access : read


CAN1_TXBCF

CAN1 Tx Buffer Ca1cellatio1 Fi1ished Register
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_TXBCF CAN1_TXBCF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CF

CF : Transmit Buffer Cancellation Finished
bits : 0 - 31 (32 bit)
access : read


CAN1_TXBTIE

CAN1 Tx Buffer Tra1smissio1 I1terrupt E1able Register
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_TXBTIE CAN1_TXBTIE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIE

TIE : Tx Buffer Transmission Interrupt Enable
bits : 0 - 31 (32 bit)
access : read-write


CAN1_TXBCIE

CAN1 Tx Buffer Ca1cellatio1 Fi1ished I1terrupt E1able Register
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_TXBCIE CAN1_TXBCIE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFIE

CFIE : Tx Buffer Cancellation Finished Interrupt Enable
bits : 0 - 31 (32 bit)
access : read-write


CAN1_TXEFC

CAN1 Tx Eve1t FIFO Co1figuratio1 Register
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_TXEFC CAN1_TXEFC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EFSA EFS __reserve0 EFWM __reserve1

EFSA : Start address of Tx Event FIFO in Message RAM (*1)
bits : 0 - 15 (16 bit)
access : read-write

EFS : Event FIFO Size
bits : 16 - 37 (22 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 22 - 45 (24 bit)
access : read

EFWM : Event FIFO Watermark
bits : 24 - 53 (30 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 30 - 61 (32 bit)
access : read


CAN1_TXEFS

CAN1 Tx Eve1t FIFO Status Register
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_TXEFS CAN1_TXEFS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EFFL __reserve0 EFGI __reserve1 EFPI __reserve2 EFF TEFL __reserve3

EFFL : Event FIFO Fill Level
bits : 0 - 5 (6 bit)
access : read

__reserve0 : 0 is always read out.
bits : 6 - 13 (8 bit)
access : read

EFGI : Event FIFO Get Index
bits : 8 - 20 (13 bit)
access : read

__reserve1 : 0 is always read out.
bits : 13 - 28 (16 bit)
access : read

EFPI : Event FIFO Put Index
bits : 16 - 36 (21 bit)
access : read

__reserve2 : 0 is always read out.
bits : 21 - 44 (24 bit)
access : read

EFF : Event FIFO Full
bits : 24 - 48 (25 bit)
access : read

TEFL : Tx Event FIFO Element Lost (*1)
bits : 25 - 50 (26 bit)
access : read

__reserve3 : 0 is always read out.
bits : 26 - 57 (32 bit)
access : read


CAN1_TXEFA

CAN1 Tx Eve1t FIFO Ack1owledge Register
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN1_TXEFA CAN1_TXEFA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EFAI __reserve0

EFAI : Event FIFO Acknowledge Index
bits : 0 - 4 (5 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 5 - 36 (32 bit)
access : read


CAN0_ECR

CAN0 Error Cou0ter Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_ECR CAN0_ECR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEC REC RP CEL __reserve0

TEC : Transmit Error Counter
bits : 0 - 7 (8 bit)
access : read

REC : Receive Error Counter
bits : 8 - 22 (15 bit)
access : read

RP : Receive Error Passive
bits : 15 - 30 (16 bit)
access : read

CEL : CAN Error Logging (*1)
bits : 16 - 39 (24 bit)
access : read

__reserve0 : 0 is always read out.
bits : 24 - 55 (32 bit)
access : read


CAN0_PSR

CAN0 Protocol Status Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_PSR CAN0_PSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEC ACT EP EW BO DLEC RESI RBRS RFDF PXE __reserve0 TDCV __reserve1

LEC : Last error code to occur on the CAN bus.(*4)(*5)
bits : 0 - 2 (3 bit)
access : read

ACT : Activity
bits : 3 - 7 (5 bit)
access : read

EP : CANn Error Passive
bits : 5 - 10 (6 bit)
access : read

EW : Warning Status
bits : 6 - 12 (7 bit)
access : read

BO : Bus_Off Status
bits : 7 - 14 (8 bit)
access : read

DLEC : Data Phase Last Error Code
bits : 8 - 18 (11 bit)
access : read

RESI : ESI flag of last received CAN FD Message (*1)
bits : 11 - 22 (12 bit)
access : read

RBRS : BRS flag of last received CAN FD Message (*1)
bits : 12 - 24 (13 bit)
access : read

RFDF : Received a CAN FD Message (*1)
bits : 13 - 26 (14 bit)
access : read

PXE : Protocol Exception Event (*1)
bits : 14 - 28 (15 bit)
access : read

__reserve0 : 0 is always read out.
bits : 15 - 30 (16 bit)
access : read

TDCV : Transmitter Delay Compensation Value (Position of the secondary sample point)
bits : 16 - 38 (23 bit)
access : read

__reserve1 : 0 is always read out.
bits : 23 - 54 (32 bit)
access : read


CAN0_TDCR

CAN0 Tra0smitter Delay Compe0satio0 Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_TDCR CAN0_TDCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDCF __reserve0 TDCO __reserve1

TDCF : Transmitter Delay Compensation Filter Window Length (*1)
bits : 0 - 6 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read

TDCO : Transmitter Delay Compensation Offset
bits : 8 - 22 (15 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 15 - 46 (32 bit)
access : read


CAN0_IR

CAN0 I0terrupt Factor Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_IR CAN0_IR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RF0N RF0W RF0F RF0L RF1N RF1W RF1F RF1L HPM TC TCF TFE TEFN TEFW TEFF TEFL TSW MRAF TOO DRX BEC BEU ELO EP EW BO WDI PEA PED ARA __reserve0

RF0N : Rx FIFO 0 New Message Interrupt factor
bits : 0 - 0 (1 bit)
access : read-write

RF0W : Rx FIFO 0 Watermark Reached Interrupt factor
bits : 1 - 2 (2 bit)
access : read-write

RF0F : Rx FIFO 0 Full Interrupt factor
bits : 2 - 4 (3 bit)
access : read-write

RF0L : Rx FIFO 0 Message Lost Interrupt factor
bits : 3 - 6 (4 bit)
access : read-write

RF1N : Rx FIFO 1 New Message Interrupt factor
bits : 4 - 8 (5 bit)
access : read-write

RF1W : Rx FIFO 1 Watermark Reached Interrupt factor
bits : 5 - 10 (6 bit)
access : read-write

RF1F : Rx FIFO 1 Full Interrupt factor
bits : 6 - 12 (7 bit)
access : read-write

RF1L : Rx FIFO 1 Message Lost Interrupt factor
bits : 7 - 14 (8 bit)
access : read-write

HPM : High Priority Message Interrupt factor
bits : 8 - 16 (9 bit)
access : read-write

TC : Transmission Completed Interrupt factor
bits : 9 - 18 (10 bit)
access : read-write

TCF : Transmission Cancellation Finished Interrupt factor
bits : 10 - 20 (11 bit)
access : read-write

TFE : Tx FIFO Empty Interrupt factor
bits : 11 - 22 (12 bit)
access : read-write

TEFN : Tx Event FIFO New Entry Interrupt factor
bits : 12 - 24 (13 bit)
access : read-write

TEFW : Tx Event FIFO Watermark Reached Interrupt factor
bits : 13 - 26 (14 bit)
access : read-write

TEFF : Tx Event FIFO Full Interrupt factor
bits : 14 - 28 (15 bit)
access : read-write

TEFL : Tx Event FIFO Element Lost Interrupt factor
bits : 15 - 30 (16 bit)
access : read-write

TSW : Timestamp Wraparound Interrupt factor
bits : 16 - 32 (17 bit)
access : read-write

MRAF : Message RAM Access Failure Interrupt factor
bits : 17 - 34 (18 bit)
access : read-write

TOO : Timeout Occurred Interrupt factor
bits : 18 - 36 (19 bit)
access : read-write

DRX : Message stored to Dedicated Rx Buffer Interrupt factor
bits : 19 - 38 (20 bit)
access : read-write

BEC : Bit Error Corrected Interrupt factor
bits : 20 - 40 (21 bit)
access : read-write

BEU : Bit Error Uncorrected Interrupt factor
bits : 21 - 42 (22 bit)
access : read-write

ELO : Error Logging Overflow Interrupt factor
bits : 22 - 44 (23 bit)
access : read-write

EP : Error Passive Interrupt factor
bits : 23 - 46 (24 bit)
access : read-write

EW : Warning Status Interrupt factor
bits : 24 - 48 (25 bit)
access : read-write

BO : Bus_Off Status Interrupt factor
bits : 25 - 50 (26 bit)
access : read-write

WDI : Watchdog Interrupt factor
bits : 26 - 52 (27 bit)
access : read-write

PEA : Protocol Error in Arbitration Phase Interrupt factor (Nominal Bit Time is used)
bits : 27 - 54 (28 bit)
access : read-write

PED : Protocol Error in Data Phase Interrupt factor (Data Bit Time is used)
bits : 28 - 56 (29 bit)
access : read-write

ARA : Access to Reserved Address Interrupt factor
bits : 29 - 58 (30 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 30 - 61 (32 bit)
access : read


CAN0_IE

CAN0 I0terrupt Factor E0able Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_IE CAN0_IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RF0NE RF0WE RF0FE RF0LE RF1NE RF1WE RF1FE RF1LE HPME TCE TCFE TFEE TEFNE TEFWE TEFFE TEFLE TSWE MRAFE TOOE DRXE BECE BEUE ELOE EPE EWE BOE WDIE PEAE PEDE ARAE __reserve0

RF0NE : Rx FIFO 0 New Message Interrupt Factor Enable
bits : 0 - 0 (1 bit)
access : read-write

RF0WE : Rx FIFO 0 Watermark Reached Interrupt Factor Enable
bits : 1 - 2 (2 bit)
access : read-write

RF0FE : Rx FIFO 0 Full Interrupt Factor Enable
bits : 2 - 4 (3 bit)
access : read-write

RF0LE : Rx FIFO 0 Message Lost Interrupt Factor Enable
bits : 3 - 6 (4 bit)
access : read-write

RF1NE : Rx FIFO 1 New Message Interrupt Factor Enable
bits : 4 - 8 (5 bit)
access : read-write

RF1WE : Rx FIFO 1 Watermark Reached Interrupt Factor Enable
bits : 5 - 10 (6 bit)
access : read-write

RF1FE : Rx FIFO 1 Full Interrupt Factor Enable
bits : 6 - 12 (7 bit)
access : read-write

RF1LE : Rx FIFO 1 Message Lost Interrupt Factor Enable
bits : 7 - 14 (8 bit)
access : read-write

HPME : High Priority Message Interrupt Factor Enable
bits : 8 - 16 (9 bit)
access : read-write

TCE : Transmission Completed Interrupt Factor Enable
bits : 9 - 18 (10 bit)
access : read-write

TCFE : Transmission Cancellation Finished Interrupt Factor Enable
bits : 10 - 20 (11 bit)
access : read-write

TFEE : Tx FIFO Empty Interrupt Factor Enable
bits : 11 - 22 (12 bit)
access : read-write

TEFNE : Tx Event FIFO New Entry Interrupt Factor Enable
bits : 12 - 24 (13 bit)
access : read-write

TEFWE : Tx Event FIFO Watermark Reached Interrupt Factor Enable
bits : 13 - 26 (14 bit)
access : read-write

TEFFE : Tx Event FIFO Full Interrupt Factor Enable
bits : 14 - 28 (15 bit)
access : read-write

TEFLE : Tx Event FIFO Event Lost Interrupt Factor Enable
bits : 15 - 30 (16 bit)
access : read-write

TSWE : Timestamp Wraparound Interrupt Factor Enable
bits : 16 - 32 (17 bit)
access : read-write

MRAFE : Message RAM Access Failure Interrupt Factor Enable
bits : 17 - 34 (18 bit)
access : read-write

TOOE : Timeout Occurred Interrupt Factor Enable
bits : 18 - 36 (19 bit)
access : read-write

DRXE : Message stored to Dedicated Rx Buffer Interrupt Factor Enable
bits : 19 - 38 (20 bit)
access : read-write

BECE : Bit Error Corrected Interrupt Factor Enable
bits : 20 - 40 (21 bit)
access : read-write

BEUE : Bit Error Uncorrected Interrupt Factor Enable
bits : 21 - 42 (22 bit)
access : read-write

ELOE : Error Logging Overflow Interrupt Factor Enable
bits : 22 - 44 (23 bit)
access : read-write

EPE : Error Passive Interrupt Factor Enable
bits : 23 - 46 (24 bit)
access : read-write

EWE : Warning Status Interrupt Factor Enable
bits : 24 - 48 (25 bit)
access : read-write

BOE : Bus_Off Status Interrupt Factor Enable
bits : 25 - 50 (26 bit)
access : read-write

WDIE : Watchdog Interrupt Factor Enable
bits : 26 - 52 (27 bit)
access : read-write

PEAE : Protocol Error in Arbitration Phase Interrupt Factor Enable
bits : 27 - 54 (28 bit)
access : read-write

PEDE : Protocol Error in Data Phase Interrupt Factor Enable
bits : 28 - 56 (29 bit)
access : read-write

ARAE : Access to Reserved Address Interrupt Factor Enable
bits : 29 - 58 (30 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 30 - 61 (32 bit)
access : read


CAN0_ILS

CAN0 I0terrupt Li0e Select Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_ILS CAN0_ILS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RF0NL RF0WL RF0FL RF0LL RF1NL RF1WL RF1FL RF1LL HPML TCL TCFL TFEL TEFNL TEFWL TEFFL TEFLL TSWL MRAFL TOOL DRXL BECL BEUL ELOL EPL EWL BOL WDIL PEAL PEDL ARAL __reserve0

RF0NL : Rx FIFO 0 New Message Interrupt Line
bits : 0 - 0 (1 bit)
access : read-write

RF0WL : Rx FIFO 0 Watermark Reached Interrupt Line
bits : 1 - 2 (2 bit)
access : read-write

RF0FL : Rx FIFO 0 Full Interrupt Line
bits : 2 - 4 (3 bit)
access : read-write

RF0LL : Rx FIFO 0 Message Lost Interrupt Line
bits : 3 - 6 (4 bit)
access : read-write

RF1NL : Rx FIFO 1 New Message Interrupt Line
bits : 4 - 8 (5 bit)
access : read-write

RF1WL : Rx FIFO 1 Watermark Reached Interrupt Line
bits : 5 - 10 (6 bit)
access : read-write

RF1FL : Rx FIFO 1 Full Interrupt Line
bits : 6 - 12 (7 bit)
access : read-write

RF1LL : Rx FIFO 1 Message Lost Interrupt Line
bits : 7 - 14 (8 bit)
access : read-write

HPML : High Priority Message Interrupt Line
bits : 8 - 16 (9 bit)
access : read-write

TCL : Transmission Completed Interrupt Line
bits : 9 - 18 (10 bit)
access : read-write

TCFL : Transmission Cancellation Finished Interrupt Line
bits : 10 - 20 (11 bit)
access : read-write

TFEL : Tx FIFO Empty Interrupt Line
bits : 11 - 22 (12 bit)
access : read-write

TEFNL : Tx Event FIFO New Entry Interrupt Line
bits : 12 - 24 (13 bit)
access : read-write

TEFWL : Tx Event FIFO Watermark Reached Interrupt Line
bits : 13 - 26 (14 bit)
access : read-write

TEFFL : Tx Event FIFO Full Interrupt Line
bits : 14 - 28 (15 bit)
access : read-write

TEFLL : Tx Event FIFO Event Lost Interrupt Line
bits : 15 - 30 (16 bit)
access : read-write

TSWL : Timestamp Wraparound Interrupt Line
bits : 16 - 32 (17 bit)
access : read-write

MRAFL : Message RAM Access Failure Interrupt Line
bits : 17 - 34 (18 bit)
access : read-write

TOOL : Timeout Occurred Interrupt Line
bits : 18 - 36 (19 bit)
access : read-write

DRXL : Message stored to Dedicated Rx Buffer Interrupt Line
bits : 19 - 38 (20 bit)
access : read-write

BECL : Bit Error Corrected Interrupt Line
bits : 20 - 40 (21 bit)
access : read-write

BEUL : Bit Error Uncorrected Interrupt Line
bits : 21 - 42 (22 bit)
access : read-write

ELOL : Error Logging Overflow Interrupt Line
bits : 22 - 44 (23 bit)
access : read-write

EPL : Error Passive Interrupt Line
bits : 23 - 46 (24 bit)
access : read-write

EWL : Warning Status Interrupt Line
bits : 24 - 48 (25 bit)
access : read-write

BOL : Bus_Off Status Interrupt Line
bits : 25 - 50 (26 bit)
access : read-write

WDIL : Watchdog Interrupt Line
bits : 26 - 52 (27 bit)
access : read-write

PEAL : Protocol Error in Arbitration Phase Line
bits : 27 - 54 (28 bit)
access : read-write

PEDL : Protocol Error in Data Phase Line
bits : 28 - 56 (29 bit)
access : read-write

ARAL : Access to Reserved Address Line
bits : 29 - 58 (30 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 30 - 61 (32 bit)
access : read


CAN0_ILE

CAN0 I0terrupt Li0e E0able Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_ILE CAN0_ILE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EINT0 EINT1 __reserve0

EINT0 : Enable CANn-0 Interrupt
bits : 0 - 0 (1 bit)
access : read-write

EINT1 : Enable CANn-1 Interrupt
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 33 (32 bit)
access : read


CAN0_GFC

CAN0 Global Filter Co0figuratio0 Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_GFC CAN0_GFC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRFE RRFS ANFE ANFS __reserve0

RRFE : Reject Remote Frames Extended Message ID (29-bit)
bits : 0 - 0 (1 bit)
access : read-write

RRFS : Reject Remote Frames Standard Message ID (11-bit)
bits : 1 - 2 (2 bit)
access : read-write

ANFE : Accept Non-matching Frames Extended Message ID (29-bit)
bits : 2 - 5 (4 bit)
access : read-write

ANFS : Accept Non-matching Frames Standard Message ID (11-bit)
bits : 4 - 9 (6 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 6 - 37 (32 bit)
access : read


CANC_EXTS_CNTEN

External Timestamp Counter Control Register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_EXTS_CNTEN CANC_EXTS_CNTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTEN __reserve0

CNTEN : Operation control of External timestamp counter
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


CANC_EXTS_CNTDT

External Timestamp Counter Display Register
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_EXTS_CNTDT CANC_EXTS_CNTDT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTDT WRAPAROUND __reserve0

CNTDT : Display the value of External timestamp counter.
bits : 0 - 15 (16 bit)
access : read

WRAPAROUND : Status of External timestamp counter
bits : 16 - 32 (17 bit)
access : read

__reserve0 : 0 is always read out.
bits : 17 - 48 (32 bit)
access : read


CANC_EXTS_CNTCLR

External Timestamp Counter Clear Register
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_EXTS_CNTCLR CANC_EXTS_CNTCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTCLR __reserve0

CNTCLR : Clear the value of External timestamp counter (*1)
bits : 0 - 0 (1 bit)
access : write

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


CANC_EXTS_DIV

External Timestamp Counter Dividing Register
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_EXTS_DIV CANC_EXTS_DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV __reserve0

DIV : Clock dividing ratio of External timestamp counter (*1)
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


CANC_EXTS_CMP

External Timestamp Counter Compare Clear Register
address_offset : 0x810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_EXTS_CMP CANC_EXTS_CMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP __reserve0

CMP : Set the compare value of External timestamp counter.
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


CANC_DBGMSG_CNT

Debug Message Control Register
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_DBGMSG_CNT CANC_DBGMSG_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBGMSG0 DBGMSG1 __reserve0

DBGMSG0 : Debug Message Request of CAN0
bits : 0 - 0 (1 bit)
access : read-write

DBGMSG1 : Debug Message Request of CAN1
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 33 (32 bit)
access : read


CAN0_SIDFC

CAN0 Sta0dard ID Filter Co0figuratio0 Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_SIDFC CAN0_SIDFC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLSSA LSS __reserve0

FLSSA : Start address of Standard Message ID (11-bit) filter list (*1)
bits : 0 - 15 (16 bit)
access : read-write

LSS : List Size Standard Message ID (11-bit)
bits : 16 - 39 (24 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 24 - 55 (32 bit)
access : read


CAN0_XIDFC

CAN0 Exte0ded ID Filter Co0figuratio0 Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_XIDFC CAN0_XIDFC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLESA LSE __reserve0

FLESA : Start address of Extended Message ID (29-bit) filter list (*1)
bits : 0 - 15 (16 bit)
access : read-write

LSE : List Size Extended Message ID (29-bit)
bits : 16 - 38 (23 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 23 - 54 (32 bit)
access : read


CAN0_XIDAM

CAN0 Exte0ded ID AND Mask Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_XIDAM CAN0_XIDAM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EIDM __reserve0

EIDM : Extended Message ID Mask (*1)
bits : 0 - 28 (29 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 29 - 60 (32 bit)
access : read


CANC_ECCCTRL

ECC Function Setting Register
address_offset : 0x900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_ECCCTRL CANC_ECCCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECC_OFF __reserve0 IRQ_SEL __reserve1 __reserve2 MULTPL_EN CLR_MULTPL __reserve3 DETECT_EN CLR_DETECT __reserve4

ECC_OFF : ECC function ON/OFF
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 8 (8 bit)
access : read

IRQ_SEL : Interrupt factor selection when ECC error occurs
bits : 8 - 16 (9 bit)
access : read-write

__reserve1 : This bit must be set to 0 .
bits : 9 - 18 (10 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read

MULTPL_EN : Enable each status information detection function when ECC error (2 bits) occurs
bits : 16 - 32 (17 bit)
access : read-write

CLR_MULTPL : Clear each status information detected when ECC error (2 bits) occurs (*1)
bits : 17 - 34 (18 bit)
access : read-write

__reserve3 : 0 is always read out.
bits : 18 - 41 (24 bit)
access : read

DETECT_EN : Enable each status information detection function when ECC error (1 bit or more) occurs
bits : 24 - 48 (25 bit)
access : read-write

CLR_DETECT : Clear each status information detected when ECC error (1 bit or more) occurs (*1)
bits : 25 - 50 (26 bit)
access : read-write

__reserve4 : 0 is always read out.
bits : 26 - 57 (32 bit)
access : read


CANC_ECCST

ECC Error Detection Flag Register
address_offset : 0x904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_ECCST CANC_ECCST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MULTIPL_FLG DETECT_FLG_0 DETECT_FLG_1 DETECT_FLG_2 DETECT_FLG_3 __reserve0

MULTIPL_FLG : ECC error (2 bits) occurrence detection (*2)
bits : 0 - 0 (1 bit)
access : read

DETECT_FLG_0 : ECC error (1 bit or more) occurrence (*1)
bits : 1 - 2 (2 bit)
access : read

DETECT_FLG_1 : ECC error (1 bit or more) occurrence (*1)
bits : 2 - 4 (3 bit)
access : read

DETECT_FLG_2 : ECC error (1 bit or more) occurrence (*1)
bits : 3 - 6 (4 bit)
access : read

DETECT_FLG_3 : ECC error (1 bit or more) occurrence (*1)
bits : 4 - 8 (5 bit)
access : read

__reserve0 : 0 is always read out.
bits : 5 - 36 (32 bit)
access : read


CANC_ECCRAM_DBGSEL

ECCRAM Debug Area Selection Register
address_offset : 0x908 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_ECCRAM_DBGSEL CANC_ECCRAM_DBGSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL __reserve0

SEL : Switching access surface to ECC part in Message RAM
bits : 0 - 1 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 33 (32 bit)
access : read


CANC_ECCRAM_DBG

ECCRAM Debug Register
address_offset : 0x90C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_ECCRAM_DBG CANC_ECCRAM_DBG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECCRAM_DBG_KEY

ECCRAM_DBG_KEY : Switching access route to ECC part of message RAM
bits : 0 - 31 (32 bit)
access : read-write


CANC_ERR_MULTPL_ADDR

ECC Error (2 bits) Detection Address Register
address_offset : 0x910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_ERR_MULTPL_ADDR CANC_ERR_MULTPL_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR_MULTPL_ADDR

ERR_MULTPL_ADDR : Detect and display address at the time of ECC error (2 bits) occurrence.
bits : 0 - 31 (32 bit)
access : read


CANC_ERR_MULTPL_DATA

ECC Error (2 bits) Detection Data Register
address_offset : 0x914 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_ERR_MULTPL_DATA CANC_ERR_MULTPL_DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR_MULTPL_DATA

ERR_MULTPL_DATA : Detect and display data at the time of ECC error (2 bits) occurrence.
bits : 0 - 31 (32 bit)
access : read


CANC_ERR_MULTPL_SYND

ECC Error (2 bits) Detection ECC Data Register
address_offset : 0x918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_ERR_MULTPL_SYND CANC_ERR_MULTPL_SYND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR_MULTPL_SYND __reserve0

ERR_MULTPL_SYND : Detect and display ECC data at the time of ECC error (2 bits) occurrence.
bits : 0 - 6 (7 bit)
access : read

__reserve0 : 0 is always read out.
bits : 7 - 38 (32 bit)
access : read


CANC_ERR_DETECT_ADDR_0

ECC Error (1 bit or more) Detection Address Register0
address_offset : 0x920 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_ERR_DETECT_ADDR_0 CANC_ERR_DETECT_ADDR_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR_DETECT_ADDR_0

ERR_DETECT_ADDR_0 : Detect and display address at the time of ECC error (1 bit or more) occurrence.
bits : 0 - 31 (32 bit)
access : read


CANC_ERR_DETECT_DATA_0

ECC Error (1 bit or more) Detection Data Register0
address_offset : 0x924 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_ERR_DETECT_DATA_0 CANC_ERR_DETECT_DATA_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR_DETECT_DATA_0

ERR_DETECT_DATA_0 : Detect data at the time of ECC error (1 bit or more) occurrence, and display the value before correction.
bits : 0 - 31 (32 bit)
access : read


CANC_ERR_DETECT_SYND_0

ECC Error (1 bit or more) Detection ECC Data Register0
address_offset : 0x928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_ERR_DETECT_SYND_0 CANC_ERR_DETECT_SYND_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR_DETECT_SYND_0 __reserve0

ERR_DETECT_SYND_0 : Detect ECC data at the time of ECC error (1 bit or more) occurrence, and display the value before correction.
bits : 0 - 6 (7 bit)
access : read

__reserve0 : 0 is always read out.
bits : 7 - 38 (32 bit)
access : read


CANC_ERR_DETECT_EBIT_0

ECC Error (1 bit or more) Target Bit Register0
address_offset : 0x92C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_ERR_DETECT_EBIT_0 CANC_ERR_DETECT_EBIT_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR_DETECT_EBIT_0 __reserve0

ERR_DETECT_EBIT_0 : Detect and display the target bit at the time of ECC error (1 bit or more) occurrence.
bits : 0 - 6 (7 bit)
access : read

__reserve0 : 0 is always read out.
bits : 7 - 38 (32 bit)
access : read


CANC_ERR_DETECT_ADDR_1

ECC Error (1 bit or more) Detection Address Register1
address_offset : 0x930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_ERR_DETECT_ADDR_1 CANC_ERR_DETECT_ADDR_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR_DETECT_ADDR_1

ERR_DETECT_ADDR_1 : Detect and display address at the time of ECC error (1 bit or more) occurrence.
bits : 0 - 31 (32 bit)
access : read


CANC_ERR_DETECT_DATA_1

ECC Error (1 bit or more) Detection Data Register1
address_offset : 0x934 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_ERR_DETECT_DATA_1 CANC_ERR_DETECT_DATA_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR_DETECT_DATA_1

ERR_DETECT_DATA_1 : Detect data at the time of ECC error (1 bit or more) occurrence, and display the value before correction.
bits : 0 - 31 (32 bit)
access : read


CANC_ERR_DETECT_SYND_1

ECC Error (1 bit or more) Detection ECC Data Register1
address_offset : 0x938 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_ERR_DETECT_SYND_1 CANC_ERR_DETECT_SYND_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR_DETECT_SYND_1 __reserve0

ERR_DETECT_SYND_1 : Detect ECC data at the time of ECC error (1 bit or more) occurrence, and display the value before correction.
bits : 0 - 6 (7 bit)
access : read

__reserve0 : 0 is always read out.
bits : 7 - 38 (32 bit)
access : read


CANC_ERR_DETECT_EBIT_1

ECC Error (1 bit or more) Target Bit Register1
address_offset : 0x93C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_ERR_DETECT_EBIT_1 CANC_ERR_DETECT_EBIT_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR_DETECT_EBIT_1 __reserve0

ERR_DETECT_EBIT_1 : Detect and display the target bit at the time of ECC error (1 bit or more) occurrence. (2nd stage FIFO)
bits : 0 - 6 (7 bit)
access : read

__reserve0 : 0 is always read out.
bits : 7 - 38 (32 bit)
access : read


CAN0_HPMS

CAN0 High Priority Message Status Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_HPMS CAN0_HPMS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIDX MSI FIDX FLST __reserve0

BIDX : Buffer Index
bits : 0 - 5 (6 bit)
access : read

MSI : Message Storage Indicator
bits : 6 - 13 (8 bit)
access : read

FIDX : Filter Index
bits : 8 - 22 (15 bit)
access : read

FLST : Filter List
bits : 15 - 30 (16 bit)
access : read

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


CANC_ERR_DETECT_ADDR_2

ECC Error (1 bit or more) Detection Address Register2
address_offset : 0x940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_ERR_DETECT_ADDR_2 CANC_ERR_DETECT_ADDR_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR_DETECT_ADDR_2

ERR_DETECT_ADDR_2 : Detect and display address at the time of ECC error (1 bit or more) occurrence.
bits : 0 - 31 (32 bit)
access : read


CANC_ERR_DETECT_DATA_2

ECC Error (1 bit or more) Detection Data Register2
address_offset : 0x944 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_ERR_DETECT_DATA_2 CANC_ERR_DETECT_DATA_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR_DETECT_DATA_2

ERR_DETECT_DATA_2 : Detect data at the time of ECC error (1bit or more) occurrence, and display the value before correction.
bits : 0 - 31 (32 bit)
access : read


CANC_ERR_DETECT_SYND_2

ECC Error (1 bit or more) Detection ECC Data Register2
address_offset : 0x948 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_ERR_DETECT_SYND_2 CANC_ERR_DETECT_SYND_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR_DETECT_SYND_2 __reserve0

ERR_DETECT_SYND_2 : Detect ECC data at the time of ECC error (1bit or more) occurrence, and display the value before correction.
bits : 0 - 6 (7 bit)
access : read

__reserve0 : 0 is always read out.
bits : 7 - 38 (32 bit)
access : read


CANC_ERR_DETECT_EBIT_2

ECC Error (1 bit or more) Target Bit Register2
address_offset : 0x94C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_ERR_DETECT_EBIT_2 CANC_ERR_DETECT_EBIT_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR_DETECT_EBIT_2 __reserve0

ERR_DETECT_EBIT_2 : Detect and display the target bit at the time of ECC error (1 bit or more) occurrence. (3rd stage FIFO)
bits : 0 - 6 (7 bit)
access : read

__reserve0 : 0 is always read out.
bits : 7 - 38 (32 bit)
access : read


CANC_ERR_DETECT_ADDR_3

ECC Error (1 bit or more) Detection Address Register3
address_offset : 0x950 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_ERR_DETECT_ADDR_3 CANC_ERR_DETECT_ADDR_3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR_DETECT_ADDR_3

ERR_DETECT_ADDR_3 : Detect and display address at the time of ECC error (1 bit or more) occurrence.
bits : 0 - 31 (32 bit)
access : read


CANC_ERR_DETECT_DATA_3

ECC Error (1 bit or more) Detection Data Register3
address_offset : 0x954 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_ERR_DETECT_DATA_3 CANC_ERR_DETECT_DATA_3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR_DETECT_DATA_3

ERR_DETECT_DATA_3 : Detect data at the time of ECC error (1bit or more) occurrence, and display the value before correction.
bits : 0 - 31 (32 bit)
access : read


CANC_ERR_DETECT_SYND_3

ECC Error (1 bit or more) Detection ECC Data Register3
address_offset : 0x958 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_ERR_DETECT_SYND_3 CANC_ERR_DETECT_SYND_3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR_DETECT_SYND_3 __reserve0

ERR_DETECT_SYND_3 : Detect ECC data at the time of ECC error (1bit or more) occurrence, and display the value before correction.
bits : 0 - 6 (7 bit)
access : read

__reserve0 : 0 is always read out.
bits : 7 - 38 (32 bit)
access : read


CANC_ERR_DETECT_EBIT_3

ECC Error (1 bit or more) Target Bit Register3
address_offset : 0x95C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CANC_ERR_DETECT_EBIT_3 CANC_ERR_DETECT_EBIT_3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR_DETECT_EBIT_3 __reserve0

ERR_DETECT_EBIT_3 : Detect and display the target bit at the time of ECC error (1 bit or more) occurrence. (4th stage FIFO)
bits : 0 - 6 (7 bit)
access : read

__reserve0 : 0 is always read out.
bits : 7 - 38 (32 bit)
access : read


CAN0_NDAT1

CAN0 New Data 1 Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_NDAT1 CAN0_NDAT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ND1

ND1 : New Data flags of Rx Buffers 0 to 31 (bp0 to 31)
bits : 0 - 31 (32 bit)
access : read-write


CAN0_NDAT2

CAN0 New Data 2 Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_NDAT2 CAN0_NDAT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ND2

ND2 : New Data flags of Rx Buffers 32 to 63 (bp0 to 31)
bits : 0 - 31 (32 bit)
access : read-write


CAN0_RXF0C

CAN0 Rx FIFO 0 Co0figuratio0 Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_RXF0C CAN0_RXF0C read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0SA F0S __reserve0 F0WM F0OM

F0SA : Start address of Rx FIFO 0 in Message RAM (*1)
bits : 0 - 15 (16 bit)
access : read-write

F0S : Rx FIFO 0 Size
bits : 16 - 38 (23 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 23 - 46 (24 bit)
access : read

F0WM : Rx FIFO 0 Watermark
bits : 24 - 54 (31 bit)
access : read-write

F0OM : FIFO 0 Operation Mode
bits : 31 - 62 (32 bit)
access : read-write


CAN0_RXF0S

CAN0 Rx FIFO 0 Status Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_RXF0S CAN0_RXF0S read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0FL __reserve0 F0GI __reserve1 F0PI __reserve2 F0F RF0L __reserve3

F0FL : Rx FIFO 0 Fill Level
bits : 0 - 6 (7 bit)
access : read

__reserve0 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read

F0GI : Rx FIFO 0 Get Index
bits : 8 - 21 (14 bit)
access : read

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read

F0PI : Rx FIFO 0 Put Index
bits : 16 - 37 (22 bit)
access : read

__reserve2 : 0 is always read out.
bits : 22 - 45 (24 bit)
access : read

F0F : Rx FIFO 0 Full
bits : 24 - 48 (25 bit)
access : read

RF0L : Rx FIFO 0 Message Lost (*1)(*2)
bits : 25 - 50 (26 bit)
access : read

__reserve3 : 0 is always read out.
bits : 26 - 57 (32 bit)
access : read


CAN0_RXF0A

CAN0 Rx FIFO 0 Ack0owledge Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_RXF0A CAN0_RXF0A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0AI __reserve0

F0AI : Rx FIFO 0 Acknowledge Index (*1)
bits : 0 - 5 (6 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 6 - 37 (32 bit)
access : read


CAN0_RXBC

CAN0 Rx Buffer Co0figuratio0 Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_RXBC CAN0_RXBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RBSA __reserve0

RBSA : Start address of Rx Buffers in Message RAM (*1)(*2)
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


CAN0_RXF1C

CAN0 Rx FIFO 1 Co0figuratio0 Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_RXF1C CAN0_RXF1C read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F1SA F1S __reserve0 F1WM F1OM

F1SA : Start address of Rx FIFO 1 in Message RAM (*1)
bits : 0 - 15 (16 bit)
access : read-write

F1S : Rx FIFO 1 Size
bits : 16 - 38 (23 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 23 - 46 (24 bit)
access : read

F1WM : Rx FIFO 1 Watermark
bits : 24 - 54 (31 bit)
access : read-write

F1OM : Rx FIFO 1 Operation Mode
bits : 31 - 62 (32 bit)
access : read-write


CAN0_RXF1S

CAN0 Rx FIFO 1 Status Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_RXF1S CAN0_RXF1S read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F1FL __reserve0 F1GI __reserve1 F1PI __reserve2 F1F RF1L __reserve3 DMS

F1FL : Rx FIFO 1 Fill Level
bits : 0 - 6 (7 bit)
access : read

__reserve0 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read

F1GI : Rx FIFO 1 Get Index
bits : 8 - 21 (14 bit)
access : read

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read

F1PI : Rx FIFO 1 Put Index
bits : 16 - 37 (22 bit)
access : read

__reserve2 : 0 is always read out.
bits : 22 - 45 (24 bit)
access : read

F1F : Rx FIFO 1 Full
bits : 24 - 48 (25 bit)
access : read

RF1L : Rx FIFO 1 Message Lost (*1)(*2)
bits : 25 - 50 (26 bit)
access : read

__reserve3 : 0 is always read out.
bits : 26 - 55 (30 bit)
access : read

DMS : Debug Message Status
bits : 30 - 61 (32 bit)
access : read


CAN0_RXF1A

CAN0 Rx FIFO 1 Ack0owledge Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_RXF1A CAN0_RXF1A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F1AI __reserve0

F1AI : Rx FIFO 1 Acknowledge Index
bits : 0 - 5 (6 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 6 - 37 (32 bit)
access : read


CAN0_RXESC

CAN0 Rx Buffer/ FIFO Eleme0t Size Co0figuratio0 Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_RXESC CAN0_RXESC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0DS __reserve0 F1DS __reserve1 RBDS __reserve2

F0DS : Rx FIFO 0 Data Field Size (*1)
bits : 0 - 2 (3 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 3 - 6 (4 bit)
access : read

F1DS : Rx FIFO 1 Data Field Size (*1)
bits : 4 - 10 (7 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read

RBDS : Rx Buffer Data Field Size (*1)
bits : 8 - 18 (11 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 11 - 42 (32 bit)
access : read


CAN0_DBTP

CAN0 Data Bit Timi0g and Prescaler Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_DBTP CAN0_DBTP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSJW DTSEG2 DTSEG1 __reserve0 DBRP __reserve1 TDC __reserve2

DSJW : Data (Re)Synchronization Jump Width
bits : 0 - 3 (4 bit)
access : read-write

DTSEG2 : Data time segment after sample point
bits : 4 - 11 (8 bit)
access : read-write

DTSEG1 : Data time segment before sample point
bits : 8 - 20 (13 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 13 - 28 (16 bit)
access : read

DBRP : Data Bit Rate Prescaler (*1)
bits : 16 - 36 (21 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 21 - 43 (23 bit)
access : read

TDC : Transmitter Delay Compensation
bits : 23 - 46 (24 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 24 - 55 (32 bit)
access : read


CAN0_TXBC

CAN0 Tx Buffer Co0figuratio0 Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_TXBC CAN0_TXBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBSA NDTB __reserve0 TFQS TFQM __reserve1

TBSA : Start address of Tx Buffers in Message RAM (*2)(*3)
bits : 0 - 15 (16 bit)
access : read-write

NDTB : Number of Dedicated Tx Buffers (*1)
bits : 16 - 37 (22 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 22 - 45 (24 bit)
access : read

TFQS : Tx FIFO/Queue Size (*1)
bits : 24 - 53 (30 bit)
access : read-write

TFQM : Tx FIFO/Queue Mode
bits : 30 - 60 (31 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 31 - 62 (32 bit)
access : read


CAN0_TXFQS

CAN0 Tx FIFO/Queue Status Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_TXFQS CAN0_TXFQS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFFL __reserve0 TFGI __reserve1 TFQPI TFQF __reserve2

TFFL : Tx FIFO Free Level
bits : 0 - 5 (6 bit)
access : read

__reserve0 : 0 is always read out.
bits : 6 - 13 (8 bit)
access : read

TFGI : Tx FIFO Get Index (*1)
bits : 8 - 20 (13 bit)
access : read

__reserve1 : 0 is always read out.
bits : 13 - 28 (16 bit)
access : read

TFQPI : Tx FIFO/Queue Put Index
bits : 16 - 36 (21 bit)
access : read

TFQF : Tx FIFO/Queue Full
bits : 21 - 42 (22 bit)
access : read

__reserve2 : 0 is always read out.
bits : 22 - 53 (32 bit)
access : read


CAN0_TXESC

CAN0 Tx Buffer Eleme0t Size Co0figuratio0 Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_TXESC CAN0_TXESC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBDS __reserve0

TBDS : Tx Buffer Data Field Size (*1)
bits : 0 - 2 (3 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 3 - 34 (32 bit)
access : read


CAN0_TXBRP

CAN0 Tx Buffer Request Pe0di0g Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_TXBRP CAN0_TXBRP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRP

TRP : Transmission Request Pending
bits : 0 - 31 (32 bit)
access : read


CAN0_TXBAR

CAN0 Tx Buffer Add Request Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_TXBAR CAN0_TXBAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AR

AR : Add Request
bits : 0 - 31 (32 bit)
access : read-write


CAN0_TXBCR

CAN0 Tx Buffer Ca0cellatio0 Request Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_TXBCR CAN0_TXBCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CR

CR : Cancellation Request
bits : 0 - 31 (32 bit)
access : read-write


CAN0_TXBTO

CAN0 Tx Buffer Tra0smissio0 Occurred Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_TXBTO CAN0_TXBTO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TO

TO : Transmission Occurred
bits : 0 - 31 (32 bit)
access : read


CAN0_TXBCF

CAN0 Tx Buffer Ca0cellatio0 Fi0ished Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_TXBCF CAN0_TXBCF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CF

CF : Transmit Buffer Cancellation Finished
bits : 0 - 31 (32 bit)
access : read


CAN0_TXBTIE

CAN0 Tx Buffer Tra0smissio0 I0terrupt E0able Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_TXBTIE CAN0_TXBTIE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIE

TIE : Tx Buffer Transmission Interrupt Enable
bits : 0 - 31 (32 bit)
access : read-write


CAN0_TXBCIE

CAN0 Tx Buffer Ca0cellatio0 Fi0ished I0terrupt E0able Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_TXBCIE CAN0_TXBCIE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFIE

CFIE : Tx Buffer Cancellation Finished Interrupt Enable
bits : 0 - 31 (32 bit)
access : read-write


CAN0_TXEFC

CAN0 Tx Eve0t FIFO Co0figuratio0 Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_TXEFC CAN0_TXEFC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EFSA EFS __reserve0 EFWM __reserve1

EFSA : Start address of Tx Event FIFO in Message RAM (*1)
bits : 0 - 15 (16 bit)
access : read-write

EFS : Event FIFO Size
bits : 16 - 37 (22 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 22 - 45 (24 bit)
access : read

EFWM : Event FIFO Watermark
bits : 24 - 53 (30 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 30 - 61 (32 bit)
access : read


CAN0_TXEFS

CAN0 Tx Eve0t FIFO Status Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_TXEFS CAN0_TXEFS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EFFL __reserve0 EFGI __reserve1 EFPI __reserve2 EFF TEFL __reserve3

EFFL : Event FIFO Fill Level
bits : 0 - 5 (6 bit)
access : read

__reserve0 : 0 is always read out.
bits : 6 - 13 (8 bit)
access : read

EFGI : Event FIFO Get Index
bits : 8 - 20 (13 bit)
access : read

__reserve1 : 0 is always read out.
bits : 13 - 28 (16 bit)
access : read

EFPI : Event FIFO Put Index
bits : 16 - 36 (21 bit)
access : read

__reserve2 : 0 is always read out.
bits : 21 - 44 (24 bit)
access : read

EFF : Event FIFO Full
bits : 24 - 48 (25 bit)
access : read

TEFL : Tx Event FIFO Element Lost (*1)
bits : 25 - 50 (26 bit)
access : read

__reserve3 : 0 is always read out.
bits : 26 - 57 (32 bit)
access : read


CAN0_TXEFA

CAN0 Tx Eve0t FIFO Ack0owledge Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CAN0_TXEFA CAN0_TXEFA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EFAI __reserve0

EFAI : Event FIFO Acknowledge Index
bits : 0 - 4 (5 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 5 - 36 (32 bit)
access : read



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.