\n
address_offset : 0x0 Bytes (0x0)
size : 0x960 byte (0x0)
mem_usage : registers
protection :
CAN0 Core Release Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DAY : Time Stamp Day
bits : 0 - 7 (8 bit)
access : read
MON : Time Stamp Month
bits : 8 - 23 (16 bit)
access : read
YEAR : Time Stamp Year
bits : 16 - 35 (20 bit)
access : read
SUBSTEP : Sub-step of Core Release
bits : 20 - 43 (24 bit)
access : read
STEP : Step of Core Release
bits : 24 - 51 (28 bit)
access : read
REL : Core Release Version
bits : 28 - 59 (32 bit)
access : read
CAN0 Test Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
__reserve0 : 0 is always read out.
bits : 0 - 3 (4 bit)
access : read
LBCK : Loop Back Mode
bits : 4 - 8 (5 bit)
access : read-write
TX : Control of Transmit Pin CTX (*1)
bits : 5 - 11 (7 bit)
access : read-write
RX : Monitors the actual value of CRX pin
bits : 7 - 14 (8 bit)
access : read
__reserve1 : 0 is always read out.
bits : 8 - 39 (32 bit)
access : read
CAN0 RAM Watchdog Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
WDC : Watchdog Configuration
bits : 0 - 7 (8 bit)
access : read-write
WDV : Watchdog Value
bits : 8 - 23 (16 bit)
access : read
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
CAN0 CC Co0trol Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
INIT : Initialization (*5)
bits : 0 - 0 (1 bit)
access : read-write
CCE : Configuration Change Enable (*1)(*4)
bits : 1 - 2 (2 bit)
access : read-write
ASM : Restricted Operation Mode (*2)
bits : 2 - 4 (3 bit)
access : read-write
CSA : Clock Stop Acknowledge
bits : 3 - 6 (4 bit)
access : read
CSR : Clock Stop Request (*3)
bits : 4 - 8 (5 bit)
access : read-write
MON : Bus Monitoring Mode (*2)
bits : 5 - 10 (6 bit)
access : read-write
DAR : Disable Automatic Retransmission (*1)
bits : 6 - 12 (7 bit)
access : read-write
TEST : Test Mode Enable (*2)
bits : 7 - 14 (8 bit)
access : read-write
FDOE : CAN FD Operation Enable (*1)
bits : 8 - 16 (9 bit)
access : read-write
BRSE : Bit Rate Switch Enable (*1)
bits : 9 - 18 (10 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 10 - 21 (12 bit)
access : read
PXHD : Protocol Exception Handling Disable (*1)
bits : 12 - 24 (13 bit)
access : read-write
EFBI : Edge Filtering during Bus Integration (*1)
bits : 13 - 26 (14 bit)
access : read-write
TXP : Transmit Pause
bits : 14 - 28 (15 bit)
access : read-write
NISO : Non ISO Operation (*1)
bits : 15 - 30 (16 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
CAN0 Nomi0al Bit Timi0g and Prescaler Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
NTSEG2 : Nominal Time segment (TSEG2) after sample point
bits : 0 - 6 (7 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read
NTSEG1 : Nominal Time segment (TSEG1) before sample point
bits : 8 - 23 (16 bit)
access : read-write
NBRP : Nominal Bit Rate Prescaler
bits : 16 - 40 (25 bit)
access : read-write
NSJW : Nominal (Re)Synchronization Jump Width
bits : 25 - 56 (32 bit)
access : read-write
CAN0 Timestamp Cou0ter Co0figuratio0 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TSS : Timestamp Selection
bits : 0 - 1 (2 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read
TCP : Timestamp Counter Prescaler
bits : 16 - 35 (20 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 20 - 51 (32 bit)
access : read
CAN1 Core Release Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DAY : Time Stamp Day
bits : 0 - 7 (8 bit)
access : read
MON : Time Stamp Month
bits : 8 - 23 (16 bit)
access : read
YEAR : Time Stamp Year
bits : 16 - 35 (20 bit)
access : read
SUBSTEP : Sub-step of Core Release
bits : 20 - 43 (24 bit)
access : read
STEP : Step of Core Release
bits : 24 - 51 (28 bit)
access : read
REL : Core Release Version
bits : 28 - 59 (32 bit)
access : read
CAN1 Data Bit Timi1g and Prescaler Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DSJW : Data (Re)Synchronization Jump Width
bits : 0 - 3 (4 bit)
access : read-write
DTSEG2 : Data time segment after sample point
bits : 4 - 11 (8 bit)
access : read-write
DTSEG1 : Data time segment before sample point
bits : 8 - 20 (13 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 13 - 28 (16 bit)
access : read
DBRP : Data Bit Rate Prescaler (*1)
bits : 16 - 36 (21 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 21 - 43 (23 bit)
access : read
TDC : Transmitter Delay Compensation
bits : 23 - 46 (24 bit)
access : read-write
__reserve2 : 0 is always read out.
bits : 24 - 55 (32 bit)
access : read
CAN1 Test Register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
__reserve0 : 0 is always read out.
bits : 0 - 3 (4 bit)
access : read
LBCK : Loop Back Mode
bits : 4 - 8 (5 bit)
access : read-write
TX : Control of Transmit Pin CTX (*1)
bits : 5 - 11 (7 bit)
access : read-write
RX : Monitors the actual value of CRX pin
bits : 7 - 14 (8 bit)
access : read
__reserve1 : 0 is always read out.
bits : 8 - 39 (32 bit)
access : read
CAN1 RAM Watchdog Register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
WDC : Watchdog Configuration
bits : 0 - 7 (8 bit)
access : read-write
WDV : Watchdog Value
bits : 8 - 23 (16 bit)
access : read
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
CAN1 CC Co1trol Register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
INIT : Initialization (*5)
bits : 0 - 0 (1 bit)
access : read-write
CCE : Configuration Change Enable (*1)(*4)
bits : 1 - 2 (2 bit)
access : read-write
ASM : Restricted Operation Mode (*2)
bits : 2 - 4 (3 bit)
access : read-write
CSA : Clock Stop Acknowledge
bits : 3 - 6 (4 bit)
access : read
CSR : Clock Stop Request (*3)
bits : 4 - 8 (5 bit)
access : read-write
MON : Bus Monitoring Mode (*2)
bits : 5 - 10 (6 bit)
access : read-write
DAR : Disable Automatic Retransmission (*1)
bits : 6 - 12 (7 bit)
access : read-write
TEST : Test Mode Enable (*2)
bits : 7 - 14 (8 bit)
access : read-write
FDOE : CAN FD Operation Enable (*1)
bits : 8 - 16 (9 bit)
access : read-write
BRSE : Bit Rate Switch Enable (*1)
bits : 9 - 18 (10 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 10 - 21 (12 bit)
access : read
PXHD : Protocol Exception Handling Disable (*1)
bits : 12 - 24 (13 bit)
access : read-write
EFBI : Edge Filtering during Bus Integration (*1)
bits : 13 - 26 (14 bit)
access : read-write
TXP : Transmit Pause
bits : 14 - 28 (15 bit)
access : read-write
NISO : Non ISO Operation (*1)
bits : 15 - 30 (16 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
CAN1 Nomi1al Bit Timi1g and Prescaler Register
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
NTSEG2 : Nominal Time segment (TSEG2) after sample point
bits : 0 - 6 (7 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read
NTSEG1 : Nominal Time segment (TSEG1) before sample point
bits : 8 - 23 (16 bit)
access : read-write
NBRP : Nominal Bit Rate Prescaler
bits : 16 - 40 (25 bit)
access : read-write
NSJW : Nominal (Re)Synchronization Jump Width
bits : 25 - 56 (32 bit)
access : read-write
CAN1 Timestamp Cou1ter Co1figuratio1 Register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TSS : Timestamp Selection
bits : 0 - 1 (2 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read
TCP : Timestamp Counter Prescaler
bits : 16 - 35 (20 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 20 - 51 (32 bit)
access : read
CAN1 Timestamp Cou1ter Value Register
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TSC : Timestamp Counter
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
CAN1 Timeout Cou1ter Co1figuratio1 Register
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ETOC : Enable Timeout Counter
bits : 0 - 0 (1 bit)
access : read-write
TOS : Timeout Counter Operation mode Selection
bits : 1 - 3 (3 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 3 - 18 (16 bit)
access : read
TOP : Start value of the Timeout Counter (down-counter). Configures the Timeout Period.
bits : 16 - 47 (32 bit)
access : read-write
CAN1 Timeout Cou1ter Value Register
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TOC : Timeout Counter Value
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
CAN0 Timestamp Cou0ter Value Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TSC : Timestamp Counter
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
CAN1 Error Cou1ter Register
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TEC : Transmit Error Counter
bits : 0 - 7 (8 bit)
access : read
REC : Receive Error Counter
bits : 8 - 22 (15 bit)
access : read
RP : Receive Error Passive
bits : 15 - 30 (16 bit)
access : read
CEL : CAN Error Logging (*1)
bits : 16 - 39 (24 bit)
access : read
__reserve0 : 0 is always read out.
bits : 24 - 55 (32 bit)
access : read
CAN1 Protocol Status Register
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
LEC : Last error code to occur on the CAN bus.(*4)(*5)
bits : 0 - 2 (3 bit)
access : read
ACT : Activity
bits : 3 - 7 (5 bit)
access : read
EP : CANn Error Passive
bits : 5 - 10 (6 bit)
access : read
EW : Warning Status
bits : 6 - 12 (7 bit)
access : read
BO : Bus_Off Status
bits : 7 - 14 (8 bit)
access : read
DLEC : Data Phase Last Error Code
bits : 8 - 18 (11 bit)
access : read
RESI : ESI flag of last received CAN FD Message (*1)
bits : 11 - 22 (12 bit)
access : read
RBRS : BRS flag of last received CAN FD Message (*1)
bits : 12 - 24 (13 bit)
access : read
RFDF : Received a CAN FD Message (*1)
bits : 13 - 26 (14 bit)
access : read
PXE : Protocol Exception Event (*1)
bits : 14 - 28 (15 bit)
access : read
__reserve0 : 0 is always read out.
bits : 15 - 30 (16 bit)
access : read
TDCV : Transmitter Delay Compensation Value (Position of the secondary sample point)
bits : 16 - 38 (23 bit)
access : read
__reserve1 : 0 is always read out.
bits : 23 - 54 (32 bit)
access : read
CAN1 Tra1smitter Delay Compe1satio1 Register
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TDCF : Transmitter Delay Compensation Filter Window Length (*1)
bits : 0 - 6 (7 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read
TDCO : Transmitter Delay Compensation Offset
bits : 8 - 22 (15 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 15 - 46 (32 bit)
access : read
CAN1 I1terrupt Factor Register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RF0N : Rx FIFO 0 New Message Interrupt factor
bits : 0 - 0 (1 bit)
access : read-write
RF0W : Rx FIFO 0 Watermark Reached Interrupt factor
bits : 1 - 2 (2 bit)
access : read-write
RF0F : Rx FIFO 0 Full Interrupt factor
bits : 2 - 4 (3 bit)
access : read-write
RF0L : Rx FIFO 0 Message Lost Interrupt factor
bits : 3 - 6 (4 bit)
access : read-write
RF1N : Rx FIFO 1 New Message Interrupt factor
bits : 4 - 8 (5 bit)
access : read-write
RF1W : Rx FIFO 1 Watermark Reached Interrupt factor
bits : 5 - 10 (6 bit)
access : read-write
RF1F : Rx FIFO 1 Full Interrupt factor
bits : 6 - 12 (7 bit)
access : read-write
RF1L : Rx FIFO 1 Message Lost Interrupt factor
bits : 7 - 14 (8 bit)
access : read-write
HPM : High Priority Message Interrupt factor
bits : 8 - 16 (9 bit)
access : read-write
TC : Transmission Completed Interrupt factor
bits : 9 - 18 (10 bit)
access : read-write
TCF : Transmission Cancellation Finished Interrupt factor
bits : 10 - 20 (11 bit)
access : read-write
TFE : Tx FIFO Empty Interrupt factor
bits : 11 - 22 (12 bit)
access : read-write
TEFN : Tx Event FIFO New Entry Interrupt factor
bits : 12 - 24 (13 bit)
access : read-write
TEFW : Tx Event FIFO Watermark Reached Interrupt factor
bits : 13 - 26 (14 bit)
access : read-write
TEFF : Tx Event FIFO Full Interrupt factor
bits : 14 - 28 (15 bit)
access : read-write
TEFL : Tx Event FIFO Element Lost Interrupt factor
bits : 15 - 30 (16 bit)
access : read-write
TSW : Timestamp Wraparound Interrupt factor
bits : 16 - 32 (17 bit)
access : read-write
MRAF : Message RAM Access Failure Interrupt factor
bits : 17 - 34 (18 bit)
access : read-write
TOO : Timeout Occurred Interrupt factor
bits : 18 - 36 (19 bit)
access : read-write
DRX : Message stored to Dedicated Rx Buffer Interrupt factor
bits : 19 - 38 (20 bit)
access : read-write
BEC : Bit Error Corrected Interrupt factor
bits : 20 - 40 (21 bit)
access : read-write
BEU : Bit Error Uncorrected Interrupt factor
bits : 21 - 42 (22 bit)
access : read-write
ELO : Error Logging Overflow Interrupt factor
bits : 22 - 44 (23 bit)
access : read-write
EP : Error Passive Interrupt factor
bits : 23 - 46 (24 bit)
access : read-write
EW : Warning Status Interrupt factor
bits : 24 - 48 (25 bit)
access : read-write
BO : Bus_Off Status Interrupt factor
bits : 25 - 50 (26 bit)
access : read-write
WDI : Watchdog Interrupt factor
bits : 26 - 52 (27 bit)
access : read-write
PEA : Protocol Error in Arbitration Phase Interrupt factor (Nominal Bit Time is used)
bits : 27 - 54 (28 bit)
access : read-write
PED : Protocol Error in Data Phase Interrupt factor (Data Bit Time is used)
bits : 28 - 56 (29 bit)
access : read-write
ARA : Access to Reserved Address Interrupt factor
bits : 29 - 58 (30 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 30 - 61 (32 bit)
access : read
CAN1 I1terrupt Factor E1able Register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RF0NE : Rx FIFO 0 New Message Interrupt Factor Enable
bits : 0 - 0 (1 bit)
access : read-write
RF0WE : Rx FIFO 0 Watermark Reached Interrupt Factor Enable
bits : 1 - 2 (2 bit)
access : read-write
RF0FE : Rx FIFO 0 Full Interrupt Factor Enable
bits : 2 - 4 (3 bit)
access : read-write
RF0LE : Rx FIFO 0 Message Lost Interrupt Factor Enable
bits : 3 - 6 (4 bit)
access : read-write
RF1NE : Rx FIFO 1 New Message Interrupt Factor Enable
bits : 4 - 8 (5 bit)
access : read-write
RF1WE : Rx FIFO 1 Watermark Reached Interrupt Factor Enable
bits : 5 - 10 (6 bit)
access : read-write
RF1FE : Rx FIFO 1 Full Interrupt Factor Enable
bits : 6 - 12 (7 bit)
access : read-write
RF1LE : Rx FIFO 1 Message Lost Interrupt Factor Enable
bits : 7 - 14 (8 bit)
access : read-write
HPME : High Priority Message Interrupt Factor Enable
bits : 8 - 16 (9 bit)
access : read-write
TCE : Transmission Completed Interrupt Factor Enable
bits : 9 - 18 (10 bit)
access : read-write
TCFE : Transmission Cancellation Finished Interrupt Factor Enable
bits : 10 - 20 (11 bit)
access : read-write
TFEE : Tx FIFO Empty Interrupt Factor Enable
bits : 11 - 22 (12 bit)
access : read-write
TEFNE : Tx Event FIFO New Entry Interrupt Factor Enable
bits : 12 - 24 (13 bit)
access : read-write
TEFWE : Tx Event FIFO Watermark Reached Interrupt Factor Enable
bits : 13 - 26 (14 bit)
access : read-write
TEFFE : Tx Event FIFO Full Interrupt Factor Enable
bits : 14 - 28 (15 bit)
access : read-write
TEFLE : Tx Event FIFO Event Lost Interrupt Factor Enable
bits : 15 - 30 (16 bit)
access : read-write
TSWE : Timestamp Wraparound Interrupt Factor Enable
bits : 16 - 32 (17 bit)
access : read-write
MRAFE : Message RAM Access Failure Interrupt Factor Enable
bits : 17 - 34 (18 bit)
access : read-write
TOOE : Timeout Occurred Interrupt Factor Enable
bits : 18 - 36 (19 bit)
access : read-write
DRXE : Message stored to Dedicated Rx Buffer Interrupt Factor Enable
bits : 19 - 38 (20 bit)
access : read-write
BECE : Bit Error Corrected Interrupt Factor Enable
bits : 20 - 40 (21 bit)
access : read-write
BEUE : Bit Error Uncorrected Interrupt Factor Enable
bits : 21 - 42 (22 bit)
access : read-write
ELOE : Error Logging Overflow Interrupt Factor Enable
bits : 22 - 44 (23 bit)
access : read-write
EPE : Error Passive Interrupt Factor Enable
bits : 23 - 46 (24 bit)
access : read-write
EWE : Warning Status Interrupt Factor Enable
bits : 24 - 48 (25 bit)
access : read-write
BOE : Bus_Off Status Interrupt Factor Enable
bits : 25 - 50 (26 bit)
access : read-write
WDIE : Watchdog Interrupt Factor Enable
bits : 26 - 52 (27 bit)
access : read-write
PEAE : Protocol Error in Arbitration Phase Interrupt Factor Enable
bits : 27 - 54 (28 bit)
access : read-write
PEDE : Protocol Error in Data Phase Interrupt Factor Enable
bits : 28 - 56 (29 bit)
access : read-write
ARAE : Access to Reserved Address Interrupt Factor Enable
bits : 29 - 58 (30 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 30 - 61 (32 bit)
access : read
CAN1 I1terrupt Li1e Select Register
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RF0NL : Rx FIFO 0 New Message Interrupt Line
bits : 0 - 0 (1 bit)
access : read-write
RF0WL : Rx FIFO 0 Watermark Reached Interrupt Line
bits : 1 - 2 (2 bit)
access : read-write
RF0FL : Rx FIFO 0 Full Interrupt Line
bits : 2 - 4 (3 bit)
access : read-write
RF0LL : Rx FIFO 0 Message Lost Interrupt Line
bits : 3 - 6 (4 bit)
access : read-write
RF1NL : Rx FIFO 1 New Message Interrupt Line
bits : 4 - 8 (5 bit)
access : read-write
RF1WL : Rx FIFO 1 Watermark Reached Interrupt Line
bits : 5 - 10 (6 bit)
access : read-write
RF1FL : Rx FIFO 1 Full Interrupt Line
bits : 6 - 12 (7 bit)
access : read-write
RF1LL : Rx FIFO 1 Message Lost Interrupt Line
bits : 7 - 14 (8 bit)
access : read-write
HPML : High Priority Message Interrupt Line
bits : 8 - 16 (9 bit)
access : read-write
TCL : Transmission Completed Interrupt Line
bits : 9 - 18 (10 bit)
access : read-write
TCFL : Transmission Cancellation Finished Interrupt Line
bits : 10 - 20 (11 bit)
access : read-write
TFEL : Tx FIFO Empty Interrupt Line
bits : 11 - 22 (12 bit)
access : read-write
TEFNL : Tx Event FIFO New Entry Interrupt Line
bits : 12 - 24 (13 bit)
access : read-write
TEFWL : Tx Event FIFO Watermark Reached Interrupt Line
bits : 13 - 26 (14 bit)
access : read-write
TEFFL : Tx Event FIFO Full Interrupt Line
bits : 14 - 28 (15 bit)
access : read-write
TEFLL : Tx Event FIFO Event Lost Interrupt Line
bits : 15 - 30 (16 bit)
access : read-write
TSWL : Timestamp Wraparound Interrupt Line
bits : 16 - 32 (17 bit)
access : read-write
MRAFL : Message RAM Access Failure Interrupt Line
bits : 17 - 34 (18 bit)
access : read-write
TOOL : Timeout Occurred Interrupt Line
bits : 18 - 36 (19 bit)
access : read-write
DRXL : Message stored to Dedicated Rx Buffer Interrupt Line
bits : 19 - 38 (20 bit)
access : read-write
BECL : Bit Error Corrected Interrupt Line
bits : 20 - 40 (21 bit)
access : read-write
BEUL : Bit Error Uncorrected Interrupt Line
bits : 21 - 42 (22 bit)
access : read-write
ELOL : Error Logging Overflow Interrupt Line
bits : 22 - 44 (23 bit)
access : read-write
EPL : Error Passive Interrupt Line
bits : 23 - 46 (24 bit)
access : read-write
EWL : Warning Status Interrupt Line
bits : 24 - 48 (25 bit)
access : read-write
BOL : Bus_Off Status Interrupt Line
bits : 25 - 50 (26 bit)
access : read-write
WDIL : Watchdog Interrupt Line
bits : 26 - 52 (27 bit)
access : read-write
PEAL : Protocol Error in Arbitration Phase Line
bits : 27 - 54 (28 bit)
access : read-write
PEDL : Protocol Error in Data Phase Line
bits : 28 - 56 (29 bit)
access : read-write
ARAL : Access to Reserved Address Line
bits : 29 - 58 (30 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 30 - 61 (32 bit)
access : read
CAN1 I1terrupt Li1e E1able Register
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EINT0 : Enable CANn-0 Interrupt
bits : 0 - 0 (1 bit)
access : read-write
EINT1 : Enable CANn-1 Interrupt
bits : 1 - 2 (2 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 2 - 33 (32 bit)
access : read
CAN0 Timeout Cou0ter Co0figuratio0 Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ETOC : Enable Timeout Counter
bits : 0 - 0 (1 bit)
access : read-write
TOS : Timeout Counter Operation mode Selection
bits : 1 - 3 (3 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 3 - 18 (16 bit)
access : read
TOP : Start value of the Timeout Counter (down-counter). Configures the Timeout Period.
bits : 16 - 47 (32 bit)
access : read-write
CAN1 Global Filter Co1figuratio1 Register
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RRFE : Reject Remote Frames Extended Message ID (29-bit)
bits : 0 - 0 (1 bit)
access : read-write
RRFS : Reject Remote Frames Standard Message ID (11-bit)
bits : 1 - 2 (2 bit)
access : read-write
ANFE : Accept Non-matching Frames Extended Message ID (29-bit)
bits : 2 - 5 (4 bit)
access : read-write
ANFS : Accept Non-matching Frames Standard Message ID (11-bit)
bits : 4 - 9 (6 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 6 - 37 (32 bit)
access : read
CAN1 Sta1dard ID Filter Co1figuratio1 Register
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FLSSA : Start address of Standard Message ID (11-bit) filter list (*1)
bits : 0 - 15 (16 bit)
access : read-write
LSS : List Size Standard Message ID (11-bit)
bits : 16 - 39 (24 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 24 - 55 (32 bit)
access : read
CAN1 Exte1ded ID Filter Co1figuratio1 Register
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FLESA : Start address of Extended Message ID (29-bit) filter list (*1)
bits : 0 - 15 (16 bit)
access : read-write
LSE : List Size Extended Message ID (29-bit)
bits : 16 - 38 (23 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 23 - 54 (32 bit)
access : read
CAN1 Exte1ded ID AND Mask Register
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EIDM : Extended Message ID Mask (*1)
bits : 0 - 28 (29 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 29 - 60 (32 bit)
access : read
CAN1 High Priority Message Status Register
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
BIDX : Buffer Index
bits : 0 - 5 (6 bit)
access : read
MSI : Message Storage Indicator
bits : 6 - 13 (8 bit)
access : read
FIDX : Filter Index
bits : 8 - 22 (15 bit)
access : read
FLST : Filter List
bits : 15 - 30 (16 bit)
access : read
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
CAN1 New Data 1 Register
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ND1 : New Data flags of Rx Buffers 0 to 31 (bp0 to 31)
bits : 0 - 31 (32 bit)
access : read-write
CAN1 New Data 2 Register
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ND2 : New Data flags of Rx Buffers 32 to 63 (bp0 to 31)
bits : 0 - 31 (32 bit)
access : read-write
CAN1 Rx FIFO 0 Co1figuratio1 Register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
F0SA : Start address of Rx FIFO 0 in Message RAM (*1)
bits : 0 - 15 (16 bit)
access : read-write
F0S : Rx FIFO 0 Size
bits : 16 - 38 (23 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 23 - 46 (24 bit)
access : read
F0WM : Rx FIFO 0 Watermark
bits : 24 - 54 (31 bit)
access : read-write
F0OM : FIFO 0 Operation Mode
bits : 31 - 62 (32 bit)
access : read-write
CAN1 Rx FIFO 0 Status Register
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
F0FL : Rx FIFO 0 Fill Level
bits : 0 - 6 (7 bit)
access : read
__reserve0 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read
F0GI : Rx FIFO 0 Get Index
bits : 8 - 21 (14 bit)
access : read
__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read
F0PI : Rx FIFO 0 Put Index
bits : 16 - 37 (22 bit)
access : read
__reserve2 : 0 is always read out.
bits : 22 - 45 (24 bit)
access : read
F0F : Rx FIFO 0 Full
bits : 24 - 48 (25 bit)
access : read
RF0L : Rx FIFO 0 Message Lost (*1)(*2)
bits : 25 - 50 (26 bit)
access : read
__reserve3 : 0 is always read out.
bits : 26 - 57 (32 bit)
access : read
CAN1 Rx FIFO 0 Ack1owledge Register
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
F0AI : Rx FIFO 0 Acknowledge Index (*1)
bits : 0 - 5 (6 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 6 - 37 (32 bit)
access : read
CAN1 Rx Buffer Co1figuratio1 Register
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RBSA : Start address of Rx Buffers in Message RAM (*1)(*2)
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
CAN1 Rx FIFO 1 Co1figuratio1 Register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
F1SA : Start address of Rx FIFO 1 in Message RAM (*1)
bits : 0 - 15 (16 bit)
access : read-write
F1S : Rx FIFO 1 Size
bits : 16 - 38 (23 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 23 - 46 (24 bit)
access : read
F1WM : Rx FIFO 1 Watermark
bits : 24 - 54 (31 bit)
access : read-write
F1OM : Rx FIFO 1 Operation Mode
bits : 31 - 62 (32 bit)
access : read-write
CAN1 Rx FIFO 1 Status Register
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
F1FL : Rx FIFO 1 Fill Level
bits : 0 - 6 (7 bit)
access : read
__reserve0 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read
F1GI : Rx FIFO 1 Get Index
bits : 8 - 21 (14 bit)
access : read
__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read
F1PI : Rx FIFO 1 Put Index
bits : 16 - 37 (22 bit)
access : read
__reserve2 : 0 is always read out.
bits : 22 - 45 (24 bit)
access : read
F1F : Rx FIFO 1 Full
bits : 24 - 48 (25 bit)
access : read
RF1L : Rx FIFO 1 Message Lost (*1)(*2)
bits : 25 - 50 (26 bit)
access : read
__reserve3 : 0 is always read out.
bits : 26 - 55 (30 bit)
access : read
DMS : Debug Message Status
bits : 30 - 61 (32 bit)
access : read
CAN1 Rx FIFO 1 Ack1owledge Register
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
F1AI : Rx FIFO 1 Acknowledge Index
bits : 0 - 5 (6 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 6 - 37 (32 bit)
access : read
CAN1 Rx Buffer/ FIFO Eleme1t Size Co1figuratio1 Register
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
F0DS : Rx FIFO 0 Data Field Size (*1)
bits : 0 - 2 (3 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 3 - 6 (4 bit)
access : read
F1DS : Rx FIFO 1 Data Field Size (*1)
bits : 4 - 10 (7 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read
RBDS : Rx Buffer Data Field Size (*1)
bits : 8 - 18 (11 bit)
access : read-write
__reserve2 : 0 is always read out.
bits : 11 - 42 (32 bit)
access : read
CAN0 Timeout Cou0ter Value Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TOC : Timeout Counter Value
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
CAN1 Tx Buffer Co1figuratio1 Register
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TBSA : Start address of Tx Buffers in Message RAM (*2)(*3)
bits : 0 - 15 (16 bit)
access : read-write
NDTB : Number of Dedicated Tx Buffers (*1)
bits : 16 - 37 (22 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 22 - 45 (24 bit)
access : read
TFQS : Tx FIFO/Queue Size (*1)
bits : 24 - 53 (30 bit)
access : read-write
TFQM : Tx FIFO/Queue Mode
bits : 30 - 60 (31 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 31 - 62 (32 bit)
access : read
CAN1 Tx FIFO/Queue Status Register
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TFFL : Tx FIFO Free Level
bits : 0 - 5 (6 bit)
access : read
__reserve0 : 0 is always read out.
bits : 6 - 13 (8 bit)
access : read
TFGI : Tx FIFO Get Index (*1)
bits : 8 - 20 (13 bit)
access : read
__reserve1 : 0 is always read out.
bits : 13 - 28 (16 bit)
access : read
TFQPI : Tx FIFO/Queue Put Index
bits : 16 - 36 (21 bit)
access : read
TFQF : Tx FIFO/Queue Full
bits : 21 - 42 (22 bit)
access : read
__reserve2 : 0 is always read out.
bits : 22 - 53 (32 bit)
access : read
CAN1 Tx Buffer Eleme1t Size Co1figuratio1 Register
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TBDS : Tx Buffer Data Field Size (*1)
bits : 0 - 2 (3 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 3 - 34 (32 bit)
access : read
CAN1 Tx Buffer Request Pe1di1g Register
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TRP : Transmission Request Pending
bits : 0 - 31 (32 bit)
access : read
CAN1 Tx Buffer Add Request Register
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
AR : Add Request
bits : 0 - 31 (32 bit)
access : read-write
CAN1 Tx Buffer Ca1cellatio1 Request Register
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CR : Cancellation Request
bits : 0 - 31 (32 bit)
access : read-write
CAN1 Tx Buffer Tra1smissio1 Occurred Register
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TO : Transmission Occurred
bits : 0 - 31 (32 bit)
access : read
CAN1 Tx Buffer Ca1cellatio1 Fi1ished Register
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CF : Transmit Buffer Cancellation Finished
bits : 0 - 31 (32 bit)
access : read
CAN1 Tx Buffer Tra1smissio1 I1terrupt E1able Register
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TIE : Tx Buffer Transmission Interrupt Enable
bits : 0 - 31 (32 bit)
access : read-write
CAN1 Tx Buffer Ca1cellatio1 Fi1ished I1terrupt E1able Register
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CFIE : Tx Buffer Cancellation Finished Interrupt Enable
bits : 0 - 31 (32 bit)
access : read-write
CAN1 Tx Eve1t FIFO Co1figuratio1 Register
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EFSA : Start address of Tx Event FIFO in Message RAM (*1)
bits : 0 - 15 (16 bit)
access : read-write
EFS : Event FIFO Size
bits : 16 - 37 (22 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 22 - 45 (24 bit)
access : read
EFWM : Event FIFO Watermark
bits : 24 - 53 (30 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 30 - 61 (32 bit)
access : read
CAN1 Tx Eve1t FIFO Status Register
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EFFL : Event FIFO Fill Level
bits : 0 - 5 (6 bit)
access : read
__reserve0 : 0 is always read out.
bits : 6 - 13 (8 bit)
access : read
EFGI : Event FIFO Get Index
bits : 8 - 20 (13 bit)
access : read
__reserve1 : 0 is always read out.
bits : 13 - 28 (16 bit)
access : read
EFPI : Event FIFO Put Index
bits : 16 - 36 (21 bit)
access : read
__reserve2 : 0 is always read out.
bits : 21 - 44 (24 bit)
access : read
EFF : Event FIFO Full
bits : 24 - 48 (25 bit)
access : read
TEFL : Tx Event FIFO Element Lost (*1)
bits : 25 - 50 (26 bit)
access : read
__reserve3 : 0 is always read out.
bits : 26 - 57 (32 bit)
access : read
CAN1 Tx Eve1t FIFO Ack1owledge Register
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EFAI : Event FIFO Acknowledge Index
bits : 0 - 4 (5 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 5 - 36 (32 bit)
access : read
CAN0 Error Cou0ter Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TEC : Transmit Error Counter
bits : 0 - 7 (8 bit)
access : read
REC : Receive Error Counter
bits : 8 - 22 (15 bit)
access : read
RP : Receive Error Passive
bits : 15 - 30 (16 bit)
access : read
CEL : CAN Error Logging (*1)
bits : 16 - 39 (24 bit)
access : read
__reserve0 : 0 is always read out.
bits : 24 - 55 (32 bit)
access : read
CAN0 Protocol Status Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
LEC : Last error code to occur on the CAN bus.(*4)(*5)
bits : 0 - 2 (3 bit)
access : read
ACT : Activity
bits : 3 - 7 (5 bit)
access : read
EP : CANn Error Passive
bits : 5 - 10 (6 bit)
access : read
EW : Warning Status
bits : 6 - 12 (7 bit)
access : read
BO : Bus_Off Status
bits : 7 - 14 (8 bit)
access : read
DLEC : Data Phase Last Error Code
bits : 8 - 18 (11 bit)
access : read
RESI : ESI flag of last received CAN FD Message (*1)
bits : 11 - 22 (12 bit)
access : read
RBRS : BRS flag of last received CAN FD Message (*1)
bits : 12 - 24 (13 bit)
access : read
RFDF : Received a CAN FD Message (*1)
bits : 13 - 26 (14 bit)
access : read
PXE : Protocol Exception Event (*1)
bits : 14 - 28 (15 bit)
access : read
__reserve0 : 0 is always read out.
bits : 15 - 30 (16 bit)
access : read
TDCV : Transmitter Delay Compensation Value (Position of the secondary sample point)
bits : 16 - 38 (23 bit)
access : read
__reserve1 : 0 is always read out.
bits : 23 - 54 (32 bit)
access : read
CAN0 Tra0smitter Delay Compe0satio0 Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TDCF : Transmitter Delay Compensation Filter Window Length (*1)
bits : 0 - 6 (7 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read
TDCO : Transmitter Delay Compensation Offset
bits : 8 - 22 (15 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 15 - 46 (32 bit)
access : read
CAN0 I0terrupt Factor Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RF0N : Rx FIFO 0 New Message Interrupt factor
bits : 0 - 0 (1 bit)
access : read-write
RF0W : Rx FIFO 0 Watermark Reached Interrupt factor
bits : 1 - 2 (2 bit)
access : read-write
RF0F : Rx FIFO 0 Full Interrupt factor
bits : 2 - 4 (3 bit)
access : read-write
RF0L : Rx FIFO 0 Message Lost Interrupt factor
bits : 3 - 6 (4 bit)
access : read-write
RF1N : Rx FIFO 1 New Message Interrupt factor
bits : 4 - 8 (5 bit)
access : read-write
RF1W : Rx FIFO 1 Watermark Reached Interrupt factor
bits : 5 - 10 (6 bit)
access : read-write
RF1F : Rx FIFO 1 Full Interrupt factor
bits : 6 - 12 (7 bit)
access : read-write
RF1L : Rx FIFO 1 Message Lost Interrupt factor
bits : 7 - 14 (8 bit)
access : read-write
HPM : High Priority Message Interrupt factor
bits : 8 - 16 (9 bit)
access : read-write
TC : Transmission Completed Interrupt factor
bits : 9 - 18 (10 bit)
access : read-write
TCF : Transmission Cancellation Finished Interrupt factor
bits : 10 - 20 (11 bit)
access : read-write
TFE : Tx FIFO Empty Interrupt factor
bits : 11 - 22 (12 bit)
access : read-write
TEFN : Tx Event FIFO New Entry Interrupt factor
bits : 12 - 24 (13 bit)
access : read-write
TEFW : Tx Event FIFO Watermark Reached Interrupt factor
bits : 13 - 26 (14 bit)
access : read-write
TEFF : Tx Event FIFO Full Interrupt factor
bits : 14 - 28 (15 bit)
access : read-write
TEFL : Tx Event FIFO Element Lost Interrupt factor
bits : 15 - 30 (16 bit)
access : read-write
TSW : Timestamp Wraparound Interrupt factor
bits : 16 - 32 (17 bit)
access : read-write
MRAF : Message RAM Access Failure Interrupt factor
bits : 17 - 34 (18 bit)
access : read-write
TOO : Timeout Occurred Interrupt factor
bits : 18 - 36 (19 bit)
access : read-write
DRX : Message stored to Dedicated Rx Buffer Interrupt factor
bits : 19 - 38 (20 bit)
access : read-write
BEC : Bit Error Corrected Interrupt factor
bits : 20 - 40 (21 bit)
access : read-write
BEU : Bit Error Uncorrected Interrupt factor
bits : 21 - 42 (22 bit)
access : read-write
ELO : Error Logging Overflow Interrupt factor
bits : 22 - 44 (23 bit)
access : read-write
EP : Error Passive Interrupt factor
bits : 23 - 46 (24 bit)
access : read-write
EW : Warning Status Interrupt factor
bits : 24 - 48 (25 bit)
access : read-write
BO : Bus_Off Status Interrupt factor
bits : 25 - 50 (26 bit)
access : read-write
WDI : Watchdog Interrupt factor
bits : 26 - 52 (27 bit)
access : read-write
PEA : Protocol Error in Arbitration Phase Interrupt factor (Nominal Bit Time is used)
bits : 27 - 54 (28 bit)
access : read-write
PED : Protocol Error in Data Phase Interrupt factor (Data Bit Time is used)
bits : 28 - 56 (29 bit)
access : read-write
ARA : Access to Reserved Address Interrupt factor
bits : 29 - 58 (30 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 30 - 61 (32 bit)
access : read
CAN0 I0terrupt Factor E0able Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RF0NE : Rx FIFO 0 New Message Interrupt Factor Enable
bits : 0 - 0 (1 bit)
access : read-write
RF0WE : Rx FIFO 0 Watermark Reached Interrupt Factor Enable
bits : 1 - 2 (2 bit)
access : read-write
RF0FE : Rx FIFO 0 Full Interrupt Factor Enable
bits : 2 - 4 (3 bit)
access : read-write
RF0LE : Rx FIFO 0 Message Lost Interrupt Factor Enable
bits : 3 - 6 (4 bit)
access : read-write
RF1NE : Rx FIFO 1 New Message Interrupt Factor Enable
bits : 4 - 8 (5 bit)
access : read-write
RF1WE : Rx FIFO 1 Watermark Reached Interrupt Factor Enable
bits : 5 - 10 (6 bit)
access : read-write
RF1FE : Rx FIFO 1 Full Interrupt Factor Enable
bits : 6 - 12 (7 bit)
access : read-write
RF1LE : Rx FIFO 1 Message Lost Interrupt Factor Enable
bits : 7 - 14 (8 bit)
access : read-write
HPME : High Priority Message Interrupt Factor Enable
bits : 8 - 16 (9 bit)
access : read-write
TCE : Transmission Completed Interrupt Factor Enable
bits : 9 - 18 (10 bit)
access : read-write
TCFE : Transmission Cancellation Finished Interrupt Factor Enable
bits : 10 - 20 (11 bit)
access : read-write
TFEE : Tx FIFO Empty Interrupt Factor Enable
bits : 11 - 22 (12 bit)
access : read-write
TEFNE : Tx Event FIFO New Entry Interrupt Factor Enable
bits : 12 - 24 (13 bit)
access : read-write
TEFWE : Tx Event FIFO Watermark Reached Interrupt Factor Enable
bits : 13 - 26 (14 bit)
access : read-write
TEFFE : Tx Event FIFO Full Interrupt Factor Enable
bits : 14 - 28 (15 bit)
access : read-write
TEFLE : Tx Event FIFO Event Lost Interrupt Factor Enable
bits : 15 - 30 (16 bit)
access : read-write
TSWE : Timestamp Wraparound Interrupt Factor Enable
bits : 16 - 32 (17 bit)
access : read-write
MRAFE : Message RAM Access Failure Interrupt Factor Enable
bits : 17 - 34 (18 bit)
access : read-write
TOOE : Timeout Occurred Interrupt Factor Enable
bits : 18 - 36 (19 bit)
access : read-write
DRXE : Message stored to Dedicated Rx Buffer Interrupt Factor Enable
bits : 19 - 38 (20 bit)
access : read-write
BECE : Bit Error Corrected Interrupt Factor Enable
bits : 20 - 40 (21 bit)
access : read-write
BEUE : Bit Error Uncorrected Interrupt Factor Enable
bits : 21 - 42 (22 bit)
access : read-write
ELOE : Error Logging Overflow Interrupt Factor Enable
bits : 22 - 44 (23 bit)
access : read-write
EPE : Error Passive Interrupt Factor Enable
bits : 23 - 46 (24 bit)
access : read-write
EWE : Warning Status Interrupt Factor Enable
bits : 24 - 48 (25 bit)
access : read-write
BOE : Bus_Off Status Interrupt Factor Enable
bits : 25 - 50 (26 bit)
access : read-write
WDIE : Watchdog Interrupt Factor Enable
bits : 26 - 52 (27 bit)
access : read-write
PEAE : Protocol Error in Arbitration Phase Interrupt Factor Enable
bits : 27 - 54 (28 bit)
access : read-write
PEDE : Protocol Error in Data Phase Interrupt Factor Enable
bits : 28 - 56 (29 bit)
access : read-write
ARAE : Access to Reserved Address Interrupt Factor Enable
bits : 29 - 58 (30 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 30 - 61 (32 bit)
access : read
CAN0 I0terrupt Li0e Select Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RF0NL : Rx FIFO 0 New Message Interrupt Line
bits : 0 - 0 (1 bit)
access : read-write
RF0WL : Rx FIFO 0 Watermark Reached Interrupt Line
bits : 1 - 2 (2 bit)
access : read-write
RF0FL : Rx FIFO 0 Full Interrupt Line
bits : 2 - 4 (3 bit)
access : read-write
RF0LL : Rx FIFO 0 Message Lost Interrupt Line
bits : 3 - 6 (4 bit)
access : read-write
RF1NL : Rx FIFO 1 New Message Interrupt Line
bits : 4 - 8 (5 bit)
access : read-write
RF1WL : Rx FIFO 1 Watermark Reached Interrupt Line
bits : 5 - 10 (6 bit)
access : read-write
RF1FL : Rx FIFO 1 Full Interrupt Line
bits : 6 - 12 (7 bit)
access : read-write
RF1LL : Rx FIFO 1 Message Lost Interrupt Line
bits : 7 - 14 (8 bit)
access : read-write
HPML : High Priority Message Interrupt Line
bits : 8 - 16 (9 bit)
access : read-write
TCL : Transmission Completed Interrupt Line
bits : 9 - 18 (10 bit)
access : read-write
TCFL : Transmission Cancellation Finished Interrupt Line
bits : 10 - 20 (11 bit)
access : read-write
TFEL : Tx FIFO Empty Interrupt Line
bits : 11 - 22 (12 bit)
access : read-write
TEFNL : Tx Event FIFO New Entry Interrupt Line
bits : 12 - 24 (13 bit)
access : read-write
TEFWL : Tx Event FIFO Watermark Reached Interrupt Line
bits : 13 - 26 (14 bit)
access : read-write
TEFFL : Tx Event FIFO Full Interrupt Line
bits : 14 - 28 (15 bit)
access : read-write
TEFLL : Tx Event FIFO Event Lost Interrupt Line
bits : 15 - 30 (16 bit)
access : read-write
TSWL : Timestamp Wraparound Interrupt Line
bits : 16 - 32 (17 bit)
access : read-write
MRAFL : Message RAM Access Failure Interrupt Line
bits : 17 - 34 (18 bit)
access : read-write
TOOL : Timeout Occurred Interrupt Line
bits : 18 - 36 (19 bit)
access : read-write
DRXL : Message stored to Dedicated Rx Buffer Interrupt Line
bits : 19 - 38 (20 bit)
access : read-write
BECL : Bit Error Corrected Interrupt Line
bits : 20 - 40 (21 bit)
access : read-write
BEUL : Bit Error Uncorrected Interrupt Line
bits : 21 - 42 (22 bit)
access : read-write
ELOL : Error Logging Overflow Interrupt Line
bits : 22 - 44 (23 bit)
access : read-write
EPL : Error Passive Interrupt Line
bits : 23 - 46 (24 bit)
access : read-write
EWL : Warning Status Interrupt Line
bits : 24 - 48 (25 bit)
access : read-write
BOL : Bus_Off Status Interrupt Line
bits : 25 - 50 (26 bit)
access : read-write
WDIL : Watchdog Interrupt Line
bits : 26 - 52 (27 bit)
access : read-write
PEAL : Protocol Error in Arbitration Phase Line
bits : 27 - 54 (28 bit)
access : read-write
PEDL : Protocol Error in Data Phase Line
bits : 28 - 56 (29 bit)
access : read-write
ARAL : Access to Reserved Address Line
bits : 29 - 58 (30 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 30 - 61 (32 bit)
access : read
CAN0 I0terrupt Li0e E0able Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EINT0 : Enable CANn-0 Interrupt
bits : 0 - 0 (1 bit)
access : read-write
EINT1 : Enable CANn-1 Interrupt
bits : 1 - 2 (2 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 2 - 33 (32 bit)
access : read
CAN0 Global Filter Co0figuratio0 Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RRFE : Reject Remote Frames Extended Message ID (29-bit)
bits : 0 - 0 (1 bit)
access : read-write
RRFS : Reject Remote Frames Standard Message ID (11-bit)
bits : 1 - 2 (2 bit)
access : read-write
ANFE : Accept Non-matching Frames Extended Message ID (29-bit)
bits : 2 - 5 (4 bit)
access : read-write
ANFS : Accept Non-matching Frames Standard Message ID (11-bit)
bits : 4 - 9 (6 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 6 - 37 (32 bit)
access : read
External Timestamp Counter Control Register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CNTEN : Operation control of External timestamp counter
bits : 0 - 0 (1 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read
External Timestamp Counter Display Register
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CNTDT : Display the value of External timestamp counter.
bits : 0 - 15 (16 bit)
access : read
WRAPAROUND : Status of External timestamp counter
bits : 16 - 32 (17 bit)
access : read
__reserve0 : 0 is always read out.
bits : 17 - 48 (32 bit)
access : read
External Timestamp Counter Clear Register
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CNTCLR : Clear the value of External timestamp counter (*1)
bits : 0 - 0 (1 bit)
access : write
__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read
External Timestamp Counter Dividing Register
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DIV : Clock dividing ratio of External timestamp counter (*1)
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
External Timestamp Counter Compare Clear Register
address_offset : 0x810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CMP : Set the compare value of External timestamp counter.
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
Debug Message Control Register
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DBGMSG0 : Debug Message Request of CAN0
bits : 0 - 0 (1 bit)
access : read-write
DBGMSG1 : Debug Message Request of CAN1
bits : 1 - 2 (2 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 2 - 33 (32 bit)
access : read
CAN0 Sta0dard ID Filter Co0figuratio0 Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FLSSA : Start address of Standard Message ID (11-bit) filter list (*1)
bits : 0 - 15 (16 bit)
access : read-write
LSS : List Size Standard Message ID (11-bit)
bits : 16 - 39 (24 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 24 - 55 (32 bit)
access : read
CAN0 Exte0ded ID Filter Co0figuratio0 Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FLESA : Start address of Extended Message ID (29-bit) filter list (*1)
bits : 0 - 15 (16 bit)
access : read-write
LSE : List Size Extended Message ID (29-bit)
bits : 16 - 38 (23 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 23 - 54 (32 bit)
access : read
CAN0 Exte0ded ID AND Mask Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EIDM : Extended Message ID Mask (*1)
bits : 0 - 28 (29 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 29 - 60 (32 bit)
access : read
ECC Function Setting Register
address_offset : 0x900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ECC_OFF : ECC function ON/OFF
bits : 0 - 0 (1 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 1 - 8 (8 bit)
access : read
IRQ_SEL : Interrupt factor selection when ECC error occurs
bits : 8 - 16 (9 bit)
access : read-write
__reserve1 : This bit must be set to 0 .
bits : 9 - 18 (10 bit)
access : read-write
__reserve2 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read
MULTPL_EN : Enable each status information detection function when ECC error (2 bits) occurs
bits : 16 - 32 (17 bit)
access : read-write
CLR_MULTPL : Clear each status information detected when ECC error (2 bits) occurs (*1)
bits : 17 - 34 (18 bit)
access : read-write
__reserve3 : 0 is always read out.
bits : 18 - 41 (24 bit)
access : read
DETECT_EN : Enable each status information detection function when ECC error (1 bit or more) occurs
bits : 24 - 48 (25 bit)
access : read-write
CLR_DETECT : Clear each status information detected when ECC error (1 bit or more) occurs (*1)
bits : 25 - 50 (26 bit)
access : read-write
__reserve4 : 0 is always read out.
bits : 26 - 57 (32 bit)
access : read
ECC Error Detection Flag Register
address_offset : 0x904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
MULTIPL_FLG : ECC error (2 bits) occurrence detection (*2)
bits : 0 - 0 (1 bit)
access : read
DETECT_FLG_0 : ECC error (1 bit or more) occurrence (*1)
bits : 1 - 2 (2 bit)
access : read
DETECT_FLG_1 : ECC error (1 bit or more) occurrence (*1)
bits : 2 - 4 (3 bit)
access : read
DETECT_FLG_2 : ECC error (1 bit or more) occurrence (*1)
bits : 3 - 6 (4 bit)
access : read
DETECT_FLG_3 : ECC error (1 bit or more) occurrence (*1)
bits : 4 - 8 (5 bit)
access : read
__reserve0 : 0 is always read out.
bits : 5 - 36 (32 bit)
access : read
ECCRAM Debug Area Selection Register
address_offset : 0x908 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SEL : Switching access surface to ECC part in Message RAM
bits : 0 - 1 (2 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 2 - 33 (32 bit)
access : read
ECCRAM Debug Register
address_offset : 0x90C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ECCRAM_DBG_KEY : Switching access route to ECC part of message RAM
bits : 0 - 31 (32 bit)
access : read-write
ECC Error (2 bits) Detection Address Register
address_offset : 0x910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ERR_MULTPL_ADDR : Detect and display address at the time of ECC error (2 bits) occurrence.
bits : 0 - 31 (32 bit)
access : read
ECC Error (2 bits) Detection Data Register
address_offset : 0x914 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ERR_MULTPL_DATA : Detect and display data at the time of ECC error (2 bits) occurrence.
bits : 0 - 31 (32 bit)
access : read
ECC Error (2 bits) Detection ECC Data Register
address_offset : 0x918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ERR_MULTPL_SYND : Detect and display ECC data at the time of ECC error (2 bits) occurrence.
bits : 0 - 6 (7 bit)
access : read
__reserve0 : 0 is always read out.
bits : 7 - 38 (32 bit)
access : read
ECC Error (1 bit or more) Detection Address Register0
address_offset : 0x920 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ERR_DETECT_ADDR_0 : Detect and display address at the time of ECC error (1 bit or more) occurrence.
bits : 0 - 31 (32 bit)
access : read
ECC Error (1 bit or more) Detection Data Register0
address_offset : 0x924 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ERR_DETECT_DATA_0 : Detect data at the time of ECC error (1 bit or more) occurrence, and display the value before correction.
bits : 0 - 31 (32 bit)
access : read
ECC Error (1 bit or more) Detection ECC Data Register0
address_offset : 0x928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ERR_DETECT_SYND_0 : Detect ECC data at the time of ECC error (1 bit or more) occurrence, and display the value before correction.
bits : 0 - 6 (7 bit)
access : read
__reserve0 : 0 is always read out.
bits : 7 - 38 (32 bit)
access : read
ECC Error (1 bit or more) Target Bit Register0
address_offset : 0x92C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ERR_DETECT_EBIT_0 : Detect and display the target bit at the time of ECC error (1 bit or more) occurrence.
bits : 0 - 6 (7 bit)
access : read
__reserve0 : 0 is always read out.
bits : 7 - 38 (32 bit)
access : read
ECC Error (1 bit or more) Detection Address Register1
address_offset : 0x930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ERR_DETECT_ADDR_1 : Detect and display address at the time of ECC error (1 bit or more) occurrence.
bits : 0 - 31 (32 bit)
access : read
ECC Error (1 bit or more) Detection Data Register1
address_offset : 0x934 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ERR_DETECT_DATA_1 : Detect data at the time of ECC error (1 bit or more) occurrence, and display the value before correction.
bits : 0 - 31 (32 bit)
access : read
ECC Error (1 bit or more) Detection ECC Data Register1
address_offset : 0x938 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ERR_DETECT_SYND_1 : Detect ECC data at the time of ECC error (1 bit or more) occurrence, and display the value before correction.
bits : 0 - 6 (7 bit)
access : read
__reserve0 : 0 is always read out.
bits : 7 - 38 (32 bit)
access : read
ECC Error (1 bit or more) Target Bit Register1
address_offset : 0x93C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ERR_DETECT_EBIT_1 : Detect and display the target bit at the time of ECC error (1 bit or more) occurrence. (2nd stage FIFO)
bits : 0 - 6 (7 bit)
access : read
__reserve0 : 0 is always read out.
bits : 7 - 38 (32 bit)
access : read
CAN0 High Priority Message Status Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
BIDX : Buffer Index
bits : 0 - 5 (6 bit)
access : read
MSI : Message Storage Indicator
bits : 6 - 13 (8 bit)
access : read
FIDX : Filter Index
bits : 8 - 22 (15 bit)
access : read
FLST : Filter List
bits : 15 - 30 (16 bit)
access : read
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
ECC Error (1 bit or more) Detection Address Register2
address_offset : 0x940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ERR_DETECT_ADDR_2 : Detect and display address at the time of ECC error (1 bit or more) occurrence.
bits : 0 - 31 (32 bit)
access : read
ECC Error (1 bit or more) Detection Data Register2
address_offset : 0x944 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ERR_DETECT_DATA_2 : Detect data at the time of ECC error (1bit or more) occurrence, and display the value before correction.
bits : 0 - 31 (32 bit)
access : read
ECC Error (1 bit or more) Detection ECC Data Register2
address_offset : 0x948 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ERR_DETECT_SYND_2 : Detect ECC data at the time of ECC error (1bit or more) occurrence, and display the value before correction.
bits : 0 - 6 (7 bit)
access : read
__reserve0 : 0 is always read out.
bits : 7 - 38 (32 bit)
access : read
ECC Error (1 bit or more) Target Bit Register2
address_offset : 0x94C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ERR_DETECT_EBIT_2 : Detect and display the target bit at the time of ECC error (1 bit or more) occurrence. (3rd stage FIFO)
bits : 0 - 6 (7 bit)
access : read
__reserve0 : 0 is always read out.
bits : 7 - 38 (32 bit)
access : read
ECC Error (1 bit or more) Detection Address Register3
address_offset : 0x950 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ERR_DETECT_ADDR_3 : Detect and display address at the time of ECC error (1 bit or more) occurrence.
bits : 0 - 31 (32 bit)
access : read
ECC Error (1 bit or more) Detection Data Register3
address_offset : 0x954 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ERR_DETECT_DATA_3 : Detect data at the time of ECC error (1bit or more) occurrence, and display the value before correction.
bits : 0 - 31 (32 bit)
access : read
ECC Error (1 bit or more) Detection ECC Data Register3
address_offset : 0x958 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ERR_DETECT_SYND_3 : Detect ECC data at the time of ECC error (1bit or more) occurrence, and display the value before correction.
bits : 0 - 6 (7 bit)
access : read
__reserve0 : 0 is always read out.
bits : 7 - 38 (32 bit)
access : read
ECC Error (1 bit or more) Target Bit Register3
address_offset : 0x95C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ERR_DETECT_EBIT_3 : Detect and display the target bit at the time of ECC error (1 bit or more) occurrence. (4th stage FIFO)
bits : 0 - 6 (7 bit)
access : read
__reserve0 : 0 is always read out.
bits : 7 - 38 (32 bit)
access : read
CAN0 New Data 1 Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ND1 : New Data flags of Rx Buffers 0 to 31 (bp0 to 31)
bits : 0 - 31 (32 bit)
access : read-write
CAN0 New Data 2 Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ND2 : New Data flags of Rx Buffers 32 to 63 (bp0 to 31)
bits : 0 - 31 (32 bit)
access : read-write
CAN0 Rx FIFO 0 Co0figuratio0 Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
F0SA : Start address of Rx FIFO 0 in Message RAM (*1)
bits : 0 - 15 (16 bit)
access : read-write
F0S : Rx FIFO 0 Size
bits : 16 - 38 (23 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 23 - 46 (24 bit)
access : read
F0WM : Rx FIFO 0 Watermark
bits : 24 - 54 (31 bit)
access : read-write
F0OM : FIFO 0 Operation Mode
bits : 31 - 62 (32 bit)
access : read-write
CAN0 Rx FIFO 0 Status Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
F0FL : Rx FIFO 0 Fill Level
bits : 0 - 6 (7 bit)
access : read
__reserve0 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read
F0GI : Rx FIFO 0 Get Index
bits : 8 - 21 (14 bit)
access : read
__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read
F0PI : Rx FIFO 0 Put Index
bits : 16 - 37 (22 bit)
access : read
__reserve2 : 0 is always read out.
bits : 22 - 45 (24 bit)
access : read
F0F : Rx FIFO 0 Full
bits : 24 - 48 (25 bit)
access : read
RF0L : Rx FIFO 0 Message Lost (*1)(*2)
bits : 25 - 50 (26 bit)
access : read
__reserve3 : 0 is always read out.
bits : 26 - 57 (32 bit)
access : read
CAN0 Rx FIFO 0 Ack0owledge Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
F0AI : Rx FIFO 0 Acknowledge Index (*1)
bits : 0 - 5 (6 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 6 - 37 (32 bit)
access : read
CAN0 Rx Buffer Co0figuratio0 Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RBSA : Start address of Rx Buffers in Message RAM (*1)(*2)
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
CAN0 Rx FIFO 1 Co0figuratio0 Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
F1SA : Start address of Rx FIFO 1 in Message RAM (*1)
bits : 0 - 15 (16 bit)
access : read-write
F1S : Rx FIFO 1 Size
bits : 16 - 38 (23 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 23 - 46 (24 bit)
access : read
F1WM : Rx FIFO 1 Watermark
bits : 24 - 54 (31 bit)
access : read-write
F1OM : Rx FIFO 1 Operation Mode
bits : 31 - 62 (32 bit)
access : read-write
CAN0 Rx FIFO 1 Status Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
F1FL : Rx FIFO 1 Fill Level
bits : 0 - 6 (7 bit)
access : read
__reserve0 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read
F1GI : Rx FIFO 1 Get Index
bits : 8 - 21 (14 bit)
access : read
__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read
F1PI : Rx FIFO 1 Put Index
bits : 16 - 37 (22 bit)
access : read
__reserve2 : 0 is always read out.
bits : 22 - 45 (24 bit)
access : read
F1F : Rx FIFO 1 Full
bits : 24 - 48 (25 bit)
access : read
RF1L : Rx FIFO 1 Message Lost (*1)(*2)
bits : 25 - 50 (26 bit)
access : read
__reserve3 : 0 is always read out.
bits : 26 - 55 (30 bit)
access : read
DMS : Debug Message Status
bits : 30 - 61 (32 bit)
access : read
CAN0 Rx FIFO 1 Ack0owledge Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
F1AI : Rx FIFO 1 Acknowledge Index
bits : 0 - 5 (6 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 6 - 37 (32 bit)
access : read
CAN0 Rx Buffer/ FIFO Eleme0t Size Co0figuratio0 Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
F0DS : Rx FIFO 0 Data Field Size (*1)
bits : 0 - 2 (3 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 3 - 6 (4 bit)
access : read
F1DS : Rx FIFO 1 Data Field Size (*1)
bits : 4 - 10 (7 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read
RBDS : Rx Buffer Data Field Size (*1)
bits : 8 - 18 (11 bit)
access : read-write
__reserve2 : 0 is always read out.
bits : 11 - 42 (32 bit)
access : read
CAN0 Data Bit Timi0g and Prescaler Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DSJW : Data (Re)Synchronization Jump Width
bits : 0 - 3 (4 bit)
access : read-write
DTSEG2 : Data time segment after sample point
bits : 4 - 11 (8 bit)
access : read-write
DTSEG1 : Data time segment before sample point
bits : 8 - 20 (13 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 13 - 28 (16 bit)
access : read
DBRP : Data Bit Rate Prescaler (*1)
bits : 16 - 36 (21 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 21 - 43 (23 bit)
access : read
TDC : Transmitter Delay Compensation
bits : 23 - 46 (24 bit)
access : read-write
__reserve2 : 0 is always read out.
bits : 24 - 55 (32 bit)
access : read
CAN0 Tx Buffer Co0figuratio0 Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TBSA : Start address of Tx Buffers in Message RAM (*2)(*3)
bits : 0 - 15 (16 bit)
access : read-write
NDTB : Number of Dedicated Tx Buffers (*1)
bits : 16 - 37 (22 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 22 - 45 (24 bit)
access : read
TFQS : Tx FIFO/Queue Size (*1)
bits : 24 - 53 (30 bit)
access : read-write
TFQM : Tx FIFO/Queue Mode
bits : 30 - 60 (31 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 31 - 62 (32 bit)
access : read
CAN0 Tx FIFO/Queue Status Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TFFL : Tx FIFO Free Level
bits : 0 - 5 (6 bit)
access : read
__reserve0 : 0 is always read out.
bits : 6 - 13 (8 bit)
access : read
TFGI : Tx FIFO Get Index (*1)
bits : 8 - 20 (13 bit)
access : read
__reserve1 : 0 is always read out.
bits : 13 - 28 (16 bit)
access : read
TFQPI : Tx FIFO/Queue Put Index
bits : 16 - 36 (21 bit)
access : read
TFQF : Tx FIFO/Queue Full
bits : 21 - 42 (22 bit)
access : read
__reserve2 : 0 is always read out.
bits : 22 - 53 (32 bit)
access : read
CAN0 Tx Buffer Eleme0t Size Co0figuratio0 Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TBDS : Tx Buffer Data Field Size (*1)
bits : 0 - 2 (3 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 3 - 34 (32 bit)
access : read
CAN0 Tx Buffer Request Pe0di0g Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TRP : Transmission Request Pending
bits : 0 - 31 (32 bit)
access : read
CAN0 Tx Buffer Add Request Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
AR : Add Request
bits : 0 - 31 (32 bit)
access : read-write
CAN0 Tx Buffer Ca0cellatio0 Request Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CR : Cancellation Request
bits : 0 - 31 (32 bit)
access : read-write
CAN0 Tx Buffer Tra0smissio0 Occurred Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TO : Transmission Occurred
bits : 0 - 31 (32 bit)
access : read
CAN0 Tx Buffer Ca0cellatio0 Fi0ished Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CF : Transmit Buffer Cancellation Finished
bits : 0 - 31 (32 bit)
access : read
CAN0 Tx Buffer Tra0smissio0 I0terrupt E0able Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TIE : Tx Buffer Transmission Interrupt Enable
bits : 0 - 31 (32 bit)
access : read-write
CAN0 Tx Buffer Ca0cellatio0 Fi0ished I0terrupt E0able Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CFIE : Tx Buffer Cancellation Finished Interrupt Enable
bits : 0 - 31 (32 bit)
access : read-write
CAN0 Tx Eve0t FIFO Co0figuratio0 Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EFSA : Start address of Tx Event FIFO in Message RAM (*1)
bits : 0 - 15 (16 bit)
access : read-write
EFS : Event FIFO Size
bits : 16 - 37 (22 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 22 - 45 (24 bit)
access : read
EFWM : Event FIFO Watermark
bits : 24 - 53 (30 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 30 - 61 (32 bit)
access : read
CAN0 Tx Eve0t FIFO Status Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EFFL : Event FIFO Fill Level
bits : 0 - 5 (6 bit)
access : read
__reserve0 : 0 is always read out.
bits : 6 - 13 (8 bit)
access : read
EFGI : Event FIFO Get Index
bits : 8 - 20 (13 bit)
access : read
__reserve1 : 0 is always read out.
bits : 13 - 28 (16 bit)
access : read
EFPI : Event FIFO Put Index
bits : 16 - 36 (21 bit)
access : read
__reserve2 : 0 is always read out.
bits : 21 - 44 (24 bit)
access : read
EFF : Event FIFO Full
bits : 24 - 48 (25 bit)
access : read
TEFL : Tx Event FIFO Element Lost (*1)
bits : 25 - 50 (26 bit)
access : read
__reserve3 : 0 is always read out.
bits : 26 - 57 (32 bit)
access : read
CAN0 Tx Eve0t FIFO Ack0owledge Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EFAI : Event FIFO Acknowledge Index
bits : 0 - 4 (5 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 5 - 36 (32 bit)
access : read
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