\n

DMAC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1F0C byte (0x0)
mem_usage : registers
protection :

Registers

DMA0SRC

DMA0EXDST

DMA4SRC

DMA8SRC

DMA8DST

DMA8CNT

DMA8EXSRC

DMA8EXDST

DMA8EXCNT

DMA8RLCNT

DMA8CTR

DMA8SFTRQ

DMA8STAT

DMA8STATW

DMA4DST

DMA9SRC

DMA9DST

DMA9CNT

DMA9EXSRC

DMA9EXDST

DMA9EXCNT

DMA9RLCNT

DMA9CTR

DMA9SFTRQ

DMA9STAT

DMA9STATW

DMA4CNT

DMA10SRC

DMA10DST

DMA10CNT

DMA10EXSRC

DMA10EXDST

DMA10EXCNT

DMA10RLCNT

DMA10CTR

DMA10SFTRQ

DMA10STAT

DMA10STATW

DMA4EXSRC

DMA11SRC

DMA11DST

DMA11CNT

DMA11EXSRC

DMA11EXDST

DMA11EXCNT

DMA11RLCNT

DMA11CTR

DMA11SFTRQ

DMA11STAT

DMA11STATW

DMA4EXDST

DMA12SRC

DMA12DST

DMA12CNT

DMA12EXSRC

DMA12EXDST

DMA12EXCNT

DMA12RLCNT

DMA12CTR

DMA12SFTRQ

DMA12STAT

DMA12STATW

DMA4EXCNT

DMA13SRC

DMA13DST

DMA13CNT

DMA13EXSRC

DMA13EXDST

DMA13EXCNT

DMA13RLCNT

DMA13CTR

DMA13SFTRQ

DMA13STAT

DMA13STATW

DMA4RLCNT

DMA14SRC

DMA14DST

DMA14CNT

DMA14EXSRC

DMA14EXDST

DMA14EXCNT

DMA14RLCNT

DMA14CTR

DMA14SFTRQ

DMA14STAT

DMA14STATW

DMA4CTR

DMA15SRC

DMA15DST

DMA15CNT

DMA15EXSRC

DMA15EXDST

DMA15EXCNT

DMA15RLCNT

DMA15CTR

DMA15SFTRQ

DMA15STAT

DMA15STATW

DMA4SFTRQ

DMA4STAT

DMA4STATW

DMA0EXCNT

DMA5SRC

DMA5DST

DMA5CNT

DMA5EXSRC

DMA5EXDST

DMA5EXCNT

DMA5RLCNT

DMA5CTR

DMA5SFTRQ

DMA5STAT

DMA5STATW

DMA0RLCNT

DMA6SRC

DMA6DST

DMA6CNT

DMA6EXSRC

DMA6EXDST

DMA6EXCNT

DMA6RLCNT

DMA6CTR

DMA6SFTRQ

DMA6STAT

DMA6STATW

DMA0CTR

DMA7SRC

DMA7DST

DMA7CNT

DMA7EXSRC

DMA7EXDST

DMA7EXCNT

DMA7RLCNT

DMA7CTR

DMA7SFTRQ

DMA7STAT

DMA7STATW

DMAC1NMI

DMAC1NMIW

DMAC1NMIEN

DMA0SFTRQ

DMA0STAT

DMA0STATW

DMA0DST

DMA1SRC

DMA1DST

DMA1CNT

DMA1EXSRC

DMA1EXDST

DMA1EXCNT

DMA1RLCNT

DMA1CTR

DMA1SFTRQ

DMA1STAT

DMA1STATW

DMA0CNT

DMA2SRC

DMA2DST

DMA2CNT

DMA2EXSRC

DMA2EXDST

DMA2EXCNT

DMA2RLCNT

DMA2CTR

DMA2SFTRQ

DMA2STAT

DMA2STATW

DMA0EXSRC

DMA3SRC

DMA3DST

DMA3CNT

DMA3EXSRC

DMA3EXDST

DMA3EXCNT

DMA3RLCNT

DMA3CTR

DMA3SFTRQ

DMA3STAT

DMA3STATW

DMAC0NMI

DMAC0NMIW

DMAC0NMIEN


DMA0SRC

DMA0 Source Address Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA0SRC DMA0SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC

SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write


DMA0EXDST

DMA0 Executio0 Desti0atio0 Address Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA0EXDST DMA0EXDST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXDST

EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA4SRC

DMA4 Source Address Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA4SRC DMA4SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC

SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write


DMA8SRC

DMA8 Source Address Register
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA8SRC DMA8SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC

SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write


DMA8DST

DMA8 Desti8atio8 Address Register
address_offset : 0x1004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA8DST DMA8DST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DST

DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write


DMA8CNT

DMA8 Tra8sfer Word Cou8t Register
address_offset : 0x1008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA8CNT DMA8CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT __reserve0

CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA8EXSRC

DMA8 Executio8 Source Address Register
address_offset : 0x100C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA8EXSRC DMA8EXSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXSRC

EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA8EXDST

DMA8 Executio8 Desti8atio8 Address Register
address_offset : 0x1010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA8EXDST DMA8EXDST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXDST

EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA8EXCNT

Executio8 Tra8sfer Word Cou8t Register
address_offset : 0x1014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA8EXCNT DMA8EXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXCNT __reserve0

EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA8RLCNT

DMA8 Reload Cou8ter
address_offset : 0x1018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA8RLCNT DMA8RLCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLDCNT __reserve0 SRCRLD DSTRLD

RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read

SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write

DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write


DMA8CTR

DMA Co8trol Register
address_offset : 0x101C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA8CTR DMA8CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FACTOR __reserve0 SIZE SRCMD __reserve1 DSTMD __reserve2 DMAEN

FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read

SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write

SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read

DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read

DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write


DMA8SFTRQ

DMA8 Software Request Register
address_offset : 0x1020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA8SFTRQ DMA8SFTRQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFTRQ __reserve0

SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


DMA8STAT

DMA Status Read Register
address_offset : 0x1024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA8STAT DMA8STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ REQERR OVFERR SYSERR __reserve0

DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read

REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read

OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read

SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read

__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA8STATW

DMA Status Clear Register
address_offset : 0x1028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA8STATW DMA8STATW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 REQERR OVFERR SYSERR __reserve1

__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read

REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write

OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write

SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write

__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA4DST

DMA4 Desti4atio4 Address Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA4DST DMA4DST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DST

DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write


DMA9SRC

DMA9 Source Address Register
address_offset : 0x1040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA9SRC DMA9SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC

SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write


DMA9DST

DMA9 Desti9atio9 Address Register
address_offset : 0x1044 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA9DST DMA9DST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DST

DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write


DMA9CNT

DMA9 Tra9sfer Word Cou9t Register
address_offset : 0x1048 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA9CNT DMA9CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT __reserve0

CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA9EXSRC

DMA9 Executio9 Source Address Register
address_offset : 0x104C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA9EXSRC DMA9EXSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXSRC

EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA9EXDST

DMA9 Executio9 Desti9atio9 Address Register
address_offset : 0x1050 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA9EXDST DMA9EXDST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXDST

EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA9EXCNT

Executio9 Tra9sfer Word Cou9t Register
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA9EXCNT DMA9EXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXCNT __reserve0

EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA9RLCNT

DMA9 Reload Cou9ter
address_offset : 0x1058 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA9RLCNT DMA9RLCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLDCNT __reserve0 SRCRLD DSTRLD

RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read

SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write

DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write


DMA9CTR

DMA Co9trol Register
address_offset : 0x105C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA9CTR DMA9CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FACTOR __reserve0 SIZE SRCMD __reserve1 DSTMD __reserve2 DMAEN

FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read

SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write

SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read

DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read

DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write


DMA9SFTRQ

DMA9 Software Request Register
address_offset : 0x1060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA9SFTRQ DMA9SFTRQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFTRQ __reserve0

SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


DMA9STAT

DMA Status Read Register
address_offset : 0x1064 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA9STAT DMA9STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ REQERR OVFERR SYSERR __reserve0

DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read

REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read

OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read

SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read

__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA9STATW

DMA Status Clear Register
address_offset : 0x1068 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA9STATW DMA9STATW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 REQERR OVFERR SYSERR __reserve1

__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read

REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write

OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write

SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write

__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA4CNT

DMA4 Tra4sfer Word Cou4t Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA4CNT DMA4CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT __reserve0

CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA10SRC

DMA10 Source Address Register
address_offset : 0x1080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA10SRC DMA10SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC

SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write


DMA10DST

DMA10 Desti10atio10 Address Register
address_offset : 0x1084 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA10DST DMA10DST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DST

DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write


DMA10CNT

DMA10 Tra10sfer Word Cou10t Register
address_offset : 0x1088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA10CNT DMA10CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT __reserve0

CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA10EXSRC

DMA10 Executio10 Source Address Register
address_offset : 0x108C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA10EXSRC DMA10EXSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXSRC

EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA10EXDST

DMA10 Executio10 Desti10atio10 Address Register
address_offset : 0x1090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA10EXDST DMA10EXDST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXDST

EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA10EXCNT

Executio10 Tra10sfer Word Cou10t Register
address_offset : 0x1094 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA10EXCNT DMA10EXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXCNT __reserve0

EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA10RLCNT

DMA10 Reload Cou10ter
address_offset : 0x1098 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA10RLCNT DMA10RLCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLDCNT __reserve0 SRCRLD DSTRLD

RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read

SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write

DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write


DMA10CTR

DMA Co10trol Register
address_offset : 0x109C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA10CTR DMA10CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FACTOR __reserve0 SIZE SRCMD __reserve1 DSTMD __reserve2 DMAEN

FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read

SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write

SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read

DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read

DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write


DMA10SFTRQ

DMA10 Software Request Register
address_offset : 0x10A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA10SFTRQ DMA10SFTRQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFTRQ __reserve0

SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


DMA10STAT

DMA Status Read Register
address_offset : 0x10A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA10STAT DMA10STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ REQERR OVFERR SYSERR __reserve0

DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read

REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read

OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read

SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read

__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA10STATW

DMA Status Clear Register
address_offset : 0x10A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA10STATW DMA10STATW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 REQERR OVFERR SYSERR __reserve1

__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read

REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write

OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write

SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write

__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA4EXSRC

DMA4 Executio4 Source Address Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA4EXSRC DMA4EXSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXSRC

EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA11SRC

DMA11 Source Address Register
address_offset : 0x10C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA11SRC DMA11SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC

SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write


DMA11DST

DMA11 Desti11atio11 Address Register
address_offset : 0x10C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA11DST DMA11DST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DST

DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write


DMA11CNT

DMA11 Tra11sfer Word Cou11t Register
address_offset : 0x10C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA11CNT DMA11CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT __reserve0

CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA11EXSRC

DMA11 Executio11 Source Address Register
address_offset : 0x10CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA11EXSRC DMA11EXSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXSRC

EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA11EXDST

DMA11 Executio11 Desti11atio11 Address Register
address_offset : 0x10D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA11EXDST DMA11EXDST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXDST

EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA11EXCNT

Executio11 Tra11sfer Word Cou11t Register
address_offset : 0x10D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA11EXCNT DMA11EXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXCNT __reserve0

EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA11RLCNT

DMA11 Reload Cou11ter
address_offset : 0x10D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA11RLCNT DMA11RLCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLDCNT __reserve0 SRCRLD DSTRLD

RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read

SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write

DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write


DMA11CTR

DMA Co11trol Register
address_offset : 0x10DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA11CTR DMA11CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FACTOR __reserve0 SIZE SRCMD __reserve1 DSTMD __reserve2 DMAEN

FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read

SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write

SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read

DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read

DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write


DMA11SFTRQ

DMA11 Software Request Register
address_offset : 0x10E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA11SFTRQ DMA11SFTRQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFTRQ __reserve0

SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


DMA11STAT

DMA Status Read Register
address_offset : 0x10E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA11STAT DMA11STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ REQERR OVFERR SYSERR __reserve0

DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read

REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read

OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read

SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read

__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA11STATW

DMA Status Clear Register
address_offset : 0x10E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA11STATW DMA11STATW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 REQERR OVFERR SYSERR __reserve1

__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read

REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write

OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write

SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write

__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA4EXDST

DMA4 Executio4 Desti4atio4 Address Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA4EXDST DMA4EXDST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXDST

EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA12SRC

DMA12 Source Address Register
address_offset : 0x1100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA12SRC DMA12SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC

SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write


DMA12DST

DMA12 Desti12atio12 Address Register
address_offset : 0x1104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA12DST DMA12DST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DST

DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write


DMA12CNT

DMA12 Tra12sfer Word Cou12t Register
address_offset : 0x1108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA12CNT DMA12CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT __reserve0

CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA12EXSRC

DMA12 Executio12 Source Address Register
address_offset : 0x110C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA12EXSRC DMA12EXSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXSRC

EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA12EXDST

DMA12 Executio12 Desti12atio12 Address Register
address_offset : 0x1110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA12EXDST DMA12EXDST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXDST

EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA12EXCNT

Executio12 Tra12sfer Word Cou12t Register
address_offset : 0x1114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA12EXCNT DMA12EXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXCNT __reserve0

EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA12RLCNT

DMA12 Reload Cou12ter
address_offset : 0x1118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA12RLCNT DMA12RLCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLDCNT __reserve0 SRCRLD DSTRLD

RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read

SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write

DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write


DMA12CTR

DMA Co12trol Register
address_offset : 0x111C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA12CTR DMA12CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FACTOR __reserve0 SIZE SRCMD __reserve1 DSTMD __reserve2 DMAEN

FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read

SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write

SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read

DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read

DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write


DMA12SFTRQ

DMA12 Software Request Register
address_offset : 0x1120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA12SFTRQ DMA12SFTRQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFTRQ __reserve0

SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


DMA12STAT

DMA Status Read Register
address_offset : 0x1124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA12STAT DMA12STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ REQERR OVFERR SYSERR __reserve0

DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read

REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read

OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read

SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read

__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA12STATW

DMA Status Clear Register
address_offset : 0x1128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA12STATW DMA12STATW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 REQERR OVFERR SYSERR __reserve1

__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read

REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write

OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write

SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write

__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA4EXCNT

Executio4 Tra4sfer Word Cou4t Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA4EXCNT DMA4EXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXCNT __reserve0

EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA13SRC

DMA13 Source Address Register
address_offset : 0x1140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA13SRC DMA13SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC

SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write


DMA13DST

DMA13 Desti13atio13 Address Register
address_offset : 0x1144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA13DST DMA13DST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DST

DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write


DMA13CNT

DMA13 Tra13sfer Word Cou13t Register
address_offset : 0x1148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA13CNT DMA13CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT __reserve0

CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA13EXSRC

DMA13 Executio13 Source Address Register
address_offset : 0x114C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA13EXSRC DMA13EXSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXSRC

EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA13EXDST

DMA13 Executio13 Desti13atio13 Address Register
address_offset : 0x1150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA13EXDST DMA13EXDST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXDST

EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA13EXCNT

Executio13 Tra13sfer Word Cou13t Register
address_offset : 0x1154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA13EXCNT DMA13EXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXCNT __reserve0

EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA13RLCNT

DMA13 Reload Cou13ter
address_offset : 0x1158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA13RLCNT DMA13RLCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLDCNT __reserve0 SRCRLD DSTRLD

RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read

SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write

DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write


DMA13CTR

DMA Co13trol Register
address_offset : 0x115C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA13CTR DMA13CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FACTOR __reserve0 SIZE SRCMD __reserve1 DSTMD __reserve2 DMAEN

FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read

SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write

SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read

DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read

DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write


DMA13SFTRQ

DMA13 Software Request Register
address_offset : 0x1160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA13SFTRQ DMA13SFTRQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFTRQ __reserve0

SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


DMA13STAT

DMA Status Read Register
address_offset : 0x1164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA13STAT DMA13STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ REQERR OVFERR SYSERR __reserve0

DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read

REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read

OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read

SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read

__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA13STATW

DMA Status Clear Register
address_offset : 0x1168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA13STATW DMA13STATW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 REQERR OVFERR SYSERR __reserve1

__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read

REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write

OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write

SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write

__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA4RLCNT

DMA4 Reload Cou4ter
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA4RLCNT DMA4RLCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLDCNT __reserve0 SRCRLD DSTRLD

RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read

SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write

DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write


DMA14SRC

DMA14 Source Address Register
address_offset : 0x1180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA14SRC DMA14SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC

SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write


DMA14DST

DMA14 Desti14atio14 Address Register
address_offset : 0x1184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA14DST DMA14DST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DST

DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write


DMA14CNT

DMA14 Tra14sfer Word Cou14t Register
address_offset : 0x1188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA14CNT DMA14CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT __reserve0

CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA14EXSRC

DMA14 Executio14 Source Address Register
address_offset : 0x118C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA14EXSRC DMA14EXSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXSRC

EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA14EXDST

DMA14 Executio14 Desti14atio14 Address Register
address_offset : 0x1190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA14EXDST DMA14EXDST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXDST

EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA14EXCNT

Executio14 Tra14sfer Word Cou14t Register
address_offset : 0x1194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA14EXCNT DMA14EXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXCNT __reserve0

EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA14RLCNT

DMA14 Reload Cou14ter
address_offset : 0x1198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA14RLCNT DMA14RLCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLDCNT __reserve0 SRCRLD DSTRLD

RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read

SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write

DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write


DMA14CTR

DMA Co14trol Register
address_offset : 0x119C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA14CTR DMA14CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FACTOR __reserve0 SIZE SRCMD __reserve1 DSTMD __reserve2 DMAEN

FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read

SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write

SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read

DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read

DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write


DMA14SFTRQ

DMA14 Software Request Register
address_offset : 0x11A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA14SFTRQ DMA14SFTRQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFTRQ __reserve0

SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


DMA14STAT

DMA Status Read Register
address_offset : 0x11A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA14STAT DMA14STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ REQERR OVFERR SYSERR __reserve0

DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read

REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read

OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read

SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read

__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA14STATW

DMA Status Clear Register
address_offset : 0x11A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA14STATW DMA14STATW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 REQERR OVFERR SYSERR __reserve1

__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read

REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write

OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write

SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write

__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA4CTR

DMA Co4trol Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA4CTR DMA4CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FACTOR __reserve0 SIZE SRCMD __reserve1 DSTMD __reserve2 DMAEN

FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read

SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write

SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read

DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read

DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write


DMA15SRC

DMA15 Source Address Register
address_offset : 0x11C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA15SRC DMA15SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC

SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write


DMA15DST

DMA15 Desti15atio15 Address Register
address_offset : 0x11C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA15DST DMA15DST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DST

DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write


DMA15CNT

DMA15 Tra15sfer Word Cou15t Register
address_offset : 0x11C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA15CNT DMA15CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT __reserve0

CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA15EXSRC

DMA15 Executio15 Source Address Register
address_offset : 0x11CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA15EXSRC DMA15EXSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXSRC

EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA15EXDST

DMA15 Executio15 Desti15atio15 Address Register
address_offset : 0x11D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA15EXDST DMA15EXDST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXDST

EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA15EXCNT

Executio15 Tra15sfer Word Cou15t Register
address_offset : 0x11D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA15EXCNT DMA15EXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXCNT __reserve0

EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA15RLCNT

DMA15 Reload Cou15ter
address_offset : 0x11D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA15RLCNT DMA15RLCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLDCNT __reserve0 SRCRLD DSTRLD

RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read

SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write

DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write


DMA15CTR

DMA Co15trol Register
address_offset : 0x11DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA15CTR DMA15CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FACTOR __reserve0 SIZE SRCMD __reserve1 DSTMD __reserve2 DMAEN

FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read

SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write

SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read

DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read

DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write


DMA15SFTRQ

DMA15 Software Request Register
address_offset : 0x11E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA15SFTRQ DMA15SFTRQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFTRQ __reserve0

SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


DMA15STAT

DMA Status Read Register
address_offset : 0x11E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA15STAT DMA15STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ REQERR OVFERR SYSERR __reserve0

DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read

REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read

OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read

SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read

__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA15STATW

DMA Status Clear Register
address_offset : 0x11E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA15STATW DMA15STATW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 REQERR OVFERR SYSERR __reserve1

__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read

REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write

OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write

SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write

__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA4SFTRQ

DMA4 Software Request Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA4SFTRQ DMA4SFTRQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFTRQ __reserve0

SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


DMA4STAT

DMA Status Read Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA4STAT DMA4STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ REQERR OVFERR SYSERR __reserve0

DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read

REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read

OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read

SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read

__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA4STATW

DMA Status Clear Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA4STATW DMA4STATW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 REQERR OVFERR SYSERR __reserve1

__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read

REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write

OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write

SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write

__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA0EXCNT

Executio0 Tra0sfer Word Cou0t Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA0EXCNT DMA0EXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXCNT __reserve0

EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA5SRC

DMA5 Source Address Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA5SRC DMA5SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC

SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write


DMA5DST

DMA5 Desti5atio5 Address Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA5DST DMA5DST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DST

DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write


DMA5CNT

DMA5 Tra5sfer Word Cou5t Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA5CNT DMA5CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT __reserve0

CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA5EXSRC

DMA5 Executio5 Source Address Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA5EXSRC DMA5EXSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXSRC

EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA5EXDST

DMA5 Executio5 Desti5atio5 Address Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA5EXDST DMA5EXDST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXDST

EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA5EXCNT

Executio5 Tra5sfer Word Cou5t Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA5EXCNT DMA5EXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXCNT __reserve0

EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA5RLCNT

DMA5 Reload Cou5ter
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA5RLCNT DMA5RLCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLDCNT __reserve0 SRCRLD DSTRLD

RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read

SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write

DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write


DMA5CTR

DMA Co5trol Register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA5CTR DMA5CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FACTOR __reserve0 SIZE SRCMD __reserve1 DSTMD __reserve2 DMAEN

FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read

SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write

SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read

DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read

DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write


DMA5SFTRQ

DMA5 Software Request Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA5SFTRQ DMA5SFTRQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFTRQ __reserve0

SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


DMA5STAT

DMA Status Read Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA5STAT DMA5STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ REQERR OVFERR SYSERR __reserve0

DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read

REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read

OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read

SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read

__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA5STATW

DMA Status Clear Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA5STATW DMA5STATW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 REQERR OVFERR SYSERR __reserve1

__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read

REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write

OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write

SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write

__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA0RLCNT

DMA0 Reload Cou0ter
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA0RLCNT DMA0RLCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLDCNT __reserve0 SRCRLD DSTRLD

RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read

SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write

DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write


DMA6SRC

DMA6 Source Address Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA6SRC DMA6SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC

SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write


DMA6DST

DMA6 Desti6atio6 Address Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA6DST DMA6DST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DST

DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write


DMA6CNT

DMA6 Tra6sfer Word Cou6t Register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA6CNT DMA6CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT __reserve0

CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA6EXSRC

DMA6 Executio6 Source Address Register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA6EXSRC DMA6EXSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXSRC

EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA6EXDST

DMA6 Executio6 Desti6atio6 Address Register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA6EXDST DMA6EXDST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXDST

EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA6EXCNT

Executio6 Tra6sfer Word Cou6t Register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA6EXCNT DMA6EXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXCNT __reserve0

EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA6RLCNT

DMA6 Reload Cou6ter
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA6RLCNT DMA6RLCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLDCNT __reserve0 SRCRLD DSTRLD

RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read

SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write

DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write


DMA6CTR

DMA Co6trol Register
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA6CTR DMA6CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FACTOR __reserve0 SIZE SRCMD __reserve1 DSTMD __reserve2 DMAEN

FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read

SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write

SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read

DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read

DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write


DMA6SFTRQ

DMA6 Software Request Register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA6SFTRQ DMA6SFTRQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFTRQ __reserve0

SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


DMA6STAT

DMA Status Read Register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA6STAT DMA6STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ REQERR OVFERR SYSERR __reserve0

DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read

REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read

OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read

SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read

__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA6STATW

DMA Status Clear Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA6STATW DMA6STATW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 REQERR OVFERR SYSERR __reserve1

__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read

REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write

OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write

SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write

__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA0CTR

DMA Co0trol Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA0CTR DMA0CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FACTOR __reserve0 SIZE SRCMD __reserve1 DSTMD __reserve2 DMAEN

FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read

SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write

SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read

DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read

DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write


DMA7SRC

DMA7 Source Address Register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA7SRC DMA7SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC

SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write


DMA7DST

DMA7 Desti7atio7 Address Register
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA7DST DMA7DST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DST

DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write


DMA7CNT

DMA7 Tra7sfer Word Cou7t Register
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA7CNT DMA7CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT __reserve0

CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA7EXSRC

DMA7 Executio7 Source Address Register
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA7EXSRC DMA7EXSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXSRC

EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA7EXDST

DMA7 Executio7 Desti7atio7 Address Register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA7EXDST DMA7EXDST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXDST

EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA7EXCNT

Executio7 Tra7sfer Word Cou7t Register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA7EXCNT DMA7EXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXCNT __reserve0

EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA7RLCNT

DMA7 Reload Cou7ter
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA7RLCNT DMA7RLCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLDCNT __reserve0 SRCRLD DSTRLD

RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read

SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write

DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write


DMA7CTR

DMA Co7trol Register
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA7CTR DMA7CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FACTOR __reserve0 SIZE SRCMD __reserve1 DSTMD __reserve2 DMAEN

FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read

SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write

SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read

DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read

DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write


DMA7SFTRQ

DMA7 Software Request Register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA7SFTRQ DMA7SFTRQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFTRQ __reserve0

SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


DMA7STAT

DMA Status Read Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA7STAT DMA7STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ REQERR OVFERR SYSERR __reserve0

DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read

REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read

OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read

SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read

__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA7STATW

DMA Status Clear Register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA7STATW DMA7STATW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 REQERR OVFERR SYSERR __reserve1

__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read

REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write

OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write

SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write

__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMAC1NMI

DMA1NMI Status Read Register
address_offset : 0x1F00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMAC1NMI DMAC1NMI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NMI __reserve0

NMI : NMI detection bit (module m)
bits : 0 - 0 (1 bit)
access : read

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


DMAC1NMIW

DMA1NMI Status Clear Register
address_offset : 0x1F04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMAC1NMIW DMAC1NMIW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NMIW __reserve0

NMIW : Clear the NMI detection bit (module m)
bits : 0 - 0 (1 bit)
access : write

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


DMAC1NMIEN

DMA1NMI Enable Register
address_offset : 0x1F08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMAC1NMIEN DMAC1NMIEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NMIEN __reserve0

NMIEN : DMA transfer discontinuity (module m) when NMI is detected
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


DMA0SFTRQ

DMA0 Software Request Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA0SFTRQ DMA0SFTRQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFTRQ __reserve0

SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


DMA0STAT

DMA Status Read Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA0STAT DMA0STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ REQERR OVFERR SYSERR __reserve0

DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read

REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read

OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read

SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read

__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA0STATW

DMA Status Clear Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA0STATW DMA0STATW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 REQERR OVFERR SYSERR __reserve1

__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read

REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write

OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write

SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write

__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA0DST

DMA0 Desti0atio0 Address Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA0DST DMA0DST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DST

DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write


DMA1SRC

DMA1 Source Address Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA1SRC DMA1SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC

SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write


DMA1DST

DMA1 Desti1atio1 Address Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA1DST DMA1DST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DST

DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write


DMA1CNT

DMA1 Tra1sfer Word Cou1t Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA1CNT DMA1CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT __reserve0

CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA1EXSRC

DMA1 Executio1 Source Address Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA1EXSRC DMA1EXSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXSRC

EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA1EXDST

DMA1 Executio1 Desti1atio1 Address Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA1EXDST DMA1EXDST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXDST

EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA1EXCNT

Executio1 Tra1sfer Word Cou1t Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA1EXCNT DMA1EXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXCNT __reserve0

EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA1RLCNT

DMA1 Reload Cou1ter
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA1RLCNT DMA1RLCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLDCNT __reserve0 SRCRLD DSTRLD

RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read

SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write

DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write


DMA1CTR

DMA Co1trol Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA1CTR DMA1CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FACTOR __reserve0 SIZE SRCMD __reserve1 DSTMD __reserve2 DMAEN

FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read

SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write

SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read

DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read

DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write


DMA1SFTRQ

DMA1 Software Request Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA1SFTRQ DMA1SFTRQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFTRQ __reserve0

SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


DMA1STAT

DMA Status Read Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA1STAT DMA1STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ REQERR OVFERR SYSERR __reserve0

DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read

REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read

OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read

SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read

__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA1STATW

DMA Status Clear Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA1STATW DMA1STATW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 REQERR OVFERR SYSERR __reserve1

__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read

REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write

OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write

SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write

__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA0CNT

DMA0 Tra0sfer Word Cou0t Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA0CNT DMA0CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT __reserve0

CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA2SRC

DMA2 Source Address Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA2SRC DMA2SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC

SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write


DMA2DST

DMA2 Desti2atio2 Address Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA2DST DMA2DST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DST

DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write


DMA2CNT

DMA2 Tra2sfer Word Cou2t Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA2CNT DMA2CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT __reserve0

CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA2EXSRC

DMA2 Executio2 Source Address Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA2EXSRC DMA2EXSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXSRC

EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA2EXDST

DMA2 Executio2 Desti2atio2 Address Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA2EXDST DMA2EXDST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXDST

EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA2EXCNT

Executio2 Tra2sfer Word Cou2t Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA2EXCNT DMA2EXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXCNT __reserve0

EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA2RLCNT

DMA2 Reload Cou2ter
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA2RLCNT DMA2RLCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLDCNT __reserve0 SRCRLD DSTRLD

RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read

SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write

DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write


DMA2CTR

DMA Co2trol Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA2CTR DMA2CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FACTOR __reserve0 SIZE SRCMD __reserve1 DSTMD __reserve2 DMAEN

FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read

SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write

SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read

DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read

DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write


DMA2SFTRQ

DMA2 Software Request Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA2SFTRQ DMA2SFTRQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFTRQ __reserve0

SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


DMA2STAT

DMA Status Read Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA2STAT DMA2STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ REQERR OVFERR SYSERR __reserve0

DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read

REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read

OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read

SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read

__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA2STATW

DMA Status Clear Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA2STATW DMA2STATW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 REQERR OVFERR SYSERR __reserve1

__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read

REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write

OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write

SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write

__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA0EXSRC

DMA0 Executio0 Source Address Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA0EXSRC DMA0EXSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXSRC

EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA3SRC

DMA3 Source Address Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA3SRC DMA3SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC

SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write


DMA3DST

DMA3 Desti3atio3 Address Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA3DST DMA3DST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DST

DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write


DMA3CNT

DMA3 Tra3sfer Word Cou3t Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA3CNT DMA3CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT __reserve0

CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA3EXSRC

DMA3 Executio3 Source Address Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA3EXSRC DMA3EXSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXSRC

EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA3EXDST

DMA3 Executio3 Desti3atio3 Address Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA3EXDST DMA3EXDST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXDST

EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write


DMA3EXCNT

Executio3 Tra3sfer Word Cou3t Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA3EXCNT DMA3EXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXCNT __reserve0

EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


DMA3RLCNT

DMA3 Reload Cou3ter
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA3RLCNT DMA3RLCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLDCNT __reserve0 SRCRLD DSTRLD

RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read

SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write

DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write


DMA3CTR

DMA Co3trol Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA3CTR DMA3CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FACTOR __reserve0 SIZE SRCMD __reserve1 DSTMD __reserve2 DMAEN

FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read

SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write

SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read

DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read

DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write


DMA3SFTRQ

DMA3 Software Request Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA3SFTRQ DMA3SFTRQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFTRQ __reserve0

SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


DMA3STAT

DMA Status Read Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA3STAT DMA3STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ REQERR OVFERR SYSERR __reserve0

DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read

REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read

OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read

SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read

__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMA3STATW

DMA Status Clear Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMA3STATW DMA3STATW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 REQERR OVFERR SYSERR __reserve1

__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read

REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write

OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write

SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write

__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read


DMAC0NMI

DMA0NMI Status Read Register
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMAC0NMI DMAC0NMI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NMI __reserve0

NMI : NMI detection bit (module m)
bits : 0 - 0 (1 bit)
access : read

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


DMAC0NMIW

DMA0NMI Status Clear Register
address_offset : 0xF04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMAC0NMIW DMAC0NMIW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NMIW __reserve0

NMIW : Clear the NMI detection bit (module m)
bits : 0 - 0 (1 bit)
access : write

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


DMAC0NMIEN

DMA0NMI Enable Register
address_offset : 0xF08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DMAC0NMIEN DMAC0NMIEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NMIEN __reserve0

NMIEN : DMA transfer discontinuity (module m) when NMI is detected
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.