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SYTM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2018 byte (0x0)
mem_usage : registers
protection :

Registers

CHIPCKCTR

CHIPPLLCTR1

CHIPRSTCTR

CHIPRSTFLG

CHIPRSTCLR

CHIPPLLCTR2

CHIPCKSTAT

CHIPDSLEEPMD

CHIPPERICKEN0

CHIPCTLPPBL

CHIPPERICKEN1

CHIPPERICKEN2

CHIPCKSEL

CHIPTRCCKCTR

CHIPCPUCKCTR

CHIPCKWAIT


CHIPCKCTR

Clock Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CHIPCKCTR CHIPCKCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HXOEN __reserve1 KEY_CODE

__reserve0 : 1 is always read out.
bits : 0 - 0 (1 bit)
access : read

HXOEN : External high-speed oscillation (HXO) enable
bits : 1 - 2 (2 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read

KEY_CODE : Write enable code
bits : 16 - 47 (32 bit)
access : write


CHIPPLLCTR1

PLL Control Register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CHIPPLLCTR1 CHIPPLLCTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLEN PLL30M __reserve0 KEY_CODE

PLLEN : PLL function enable
bits : 0 - 0 (1 bit)
access : read-write

PLL30M : PLL clock mode
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read

KEY_CODE : Write enable code
bits : 16 - 47 (32 bit)
access : write


CHIPRSTCTR

Reset Control Register
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CHIPRSTCTR CHIPRSTCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSTREQ RRSTREQ __reserve0 KEY_CODE

RSTREQ : System software reset request
bits : 0 - 0 (1 bit)
access : read-write

RRSTREQ : Reserved-at-debug reset request
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read

KEY_CODE : Write enable code
bits : 16 - 47 (32 bit)
access : write


CHIPRSTFLG

Reset Flag Register
address_offset : 0x1010 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

CHIPRSTFLG CHIPRSTFLG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PORF EXTRSTF CSFTRSTF SSFTRSTF WDTRSTF CMONRSTF LOCRSTF RRSTF

PORF : Power-on reset (POR) flag
bits : 0 - 0 (1 bit)
access : read

EXTRSTF : Pin reset flag
bits : 1 - 2 (2 bit)
access : read

CSFTRSTF : CPU software reset flag
bits : 2 - 4 (3 bit)
access : read

SSFTRSTF : System software reset flag
bits : 3 - 6 (4 bit)
access : read

WDTRSTF : WDT error detection reset flag
bits : 4 - 8 (5 bit)
access : read

CMONRSTF : Clock error detection reset flag
bits : 5 - 10 (6 bit)
access : read

LOCRSTF : CPU LOCKUP reset flag
bits : 6 - 12 (7 bit)
access : read

RRSTF : Reserved-at-debug reset flag
bits : 7 - 14 (8 bit)
access : read


CHIPRSTCLR

Reset Flag Clear Register
address_offset : 0x1014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CHIPRSTCLR CHIPRSTCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORFCL EXTRFCL CSFTRFCL SSFTRFCL WDTRFCL CMONRFCL LOCRFCL RRFCL __reserve0 KEY_CODE

PORFCL : Clear CHIPRSTFLG.PORF by writing
bits : 0 - 0 (1 bit)
access : write

EXTRFCL : Clear CHIPRSTFLG.EXTRSTF by writing
bits : 1 - 2 (2 bit)
access : write

CSFTRFCL : Clear CHIPRSTFLG.CSFTRSTF by writing
bits : 2 - 4 (3 bit)
access : write

SSFTRFCL : Clear CHIPRSTFLG.SSFTRSTF by writing
bits : 3 - 6 (4 bit)
access : write

WDTRFCL : Clear CHIPRSTFLG.WDTRSTF by writing
bits : 4 - 8 (5 bit)
access : write

CMONRFCL : Clear CHIPRSTFLG.CMONRSTF by writing
bits : 5 - 10 (6 bit)
access : write

LOCRFCL : Clear CHIPRSTFLG.LOCRSTF by writing
bits : 6 - 12 (7 bit)
access : write

RRFCL : Clear CHIPRSTFLG.RRSTF by writing
bits : 7 - 14 (8 bit)
access : write

__reserve0 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read

KEY_CODE : Write enable code
bits : 16 - 47 (32 bit)
access : write


CHIPPLLCTR2

PLL Control Register 2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CHIPPLLCTR2 CHIPPLLCTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLMUL PLLODIV __reserve0 PLLIDIV __reserve1 KEY_CODE

PLLMUL : PLL multiplier value setting
bits : 0 - 5 (6 bit)
access : read-write

PLLODIV : PLL output clock division ratio setting
bits : 6 - 12 (7 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read

PLLIDIV : PLL input clock division ratio setting
bits : 8 - 17 (10 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 10 - 25 (16 bit)
access : read

KEY_CODE : Write enable code
bits : 16 - 47 (32 bit)
access : write


CHIPCKSTAT

Clock Status Register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

CHIPCKSTAT CHIPCKSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HRCOK HXOOK PLLOK __reserve0 HRCEN HXOEN PLLEN __reserve1 BASEST __reserve2

HRCOK : Internal oscillation (HRC) stabilization status
bits : 0 - 0 (1 bit)
access : read

HXOOK : External oscillation (HXO) stabilization status
bits : 1 - 2 (2 bit)
access : read

PLLOK : PLL stabilization status
bits : 2 - 4 (3 bit)
access : read

__reserve0 : 0 is always read out.
bits : 3 - 6 (4 bit)
access : read

HRCEN : Internal oscillation (HRC) enable status
bits : 4 - 8 (5 bit)
access : read

HXOEN : External oscillation (HXO) enable status
bits : 5 - 10 (6 bit)
access : read

PLLEN : PLL function enable status
bits : 6 - 12 (7 bit)
access : read

__reserve1 : 0 is always read out.
bits : 7 - 14 (8 bit)
access : read

BASEST : BASECLK operation status
bits : 8 - 18 (11 bit)
access : read

__reserve2 : 0 is always read out.
bits : 11 - 26 (16 bit)
access : read


CHIPDSLEEPMD

DEEPSLEEP Mode Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CHIPDSLEEPMD CHIPDSLEEPMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __reserve0 HXOEN PLLEN __reserve1 BCKEN __reserve2 KEY_CODE

__reserve0 : 1 is always read out.
bits : 0 - 0 (1 bit)
access : read

HXOEN : External oscillation (HXO) enable for DEEPSLEEP
bits : 1 - 2 (2 bit)
access : read-write

PLLEN : PLL enable for DEEPSLEEP
bits : 2 - 4 (3 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 3 - 9 (7 bit)
access : read

BCKEN : BASECLK enable for DEEPSLEEP
bits : 7 - 14 (8 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read

KEY_CODE : Write enable code
bits : 16 - 47 (32 bit)
access : write


CHIPPERICKEN0

Peripheral Clock Enable Register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CHIPPERICKEN0 CHIPPERICKEN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PECKEN0 PECKEN1 PECKEN2 PECKEN3 PECKEN4 PECKEN5 PECKEN6 PECKEN7 PECKEN8 PECKEN9 PECKEN10 PECKEN11 __reserve0 PECKEN13 __reserve1 __reserve2 KEY_CODE

PECKEN0 : Clock supply to GPWM0
bits : 0 - 0 (1 bit)
access : read-write

PECKEN1 : Clock supply to GPWM1
bits : 1 - 2 (2 bit)
access : read-write

PECKEN2 : Clock supply to GPWM2
bits : 2 - 4 (3 bit)
access : read-write

PECKEN3 : Clock supply to GPWM3
bits : 3 - 6 (4 bit)
access : read-write

PECKEN4 : Clock supply to GPWM4
bits : 4 - 8 (5 bit)
access : read-write

PECKEN5 : Clock supply to GPWM5
bits : 5 - 10 (6 bit)
access : read-write

PECKEN6 : Clock supply to GPWM6
bits : 6 - 12 (7 bit)
access : read-write

PECKEN7 : Clock supply to GPWM7
bits : 7 - 14 (8 bit)
access : read-write

PECKEN8 : Clock supply to GPWM8
bits : 8 - 16 (9 bit)
access : read-write

PECKEN9 : Clock supply to GPWM9
bits : 9 - 18 (10 bit)
access : read-write

PECKEN10 : Clock supply to GPWMA
bits : 10 - 20 (11 bit)
access : read-write

PECKEN11 : Clock supply to GPWMB
bits : 11 - 22 (12 bit)
access : read-write

__reserve0 : This bit must be set to 0 .
bits : 12 - 24 (13 bit)
access : read-write

PECKEN13 : Clock supply to DMA controller
bits : 13 - 26 (14 bit)
access : read-write

__reserve1 : This bit must be set to 0 .
bits : 14 - 28 (15 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 15 - 30 (16 bit)
access : read

KEY_CODE : Write enable code
bits : 16 - 47 (32 bit)
access : write


CHIPCTLPPBL

PPB Write Control Register
address_offset : 0x2010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CHIPCTLPPBL CHIPCTLPPBL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ITCMCR DTCMCR AHBPCR VTOR __reserve0 KEY_CODE

ITCMCR : ITCMCR write control
bits : 0 - 0 (1 bit)
access : read-write

DTCMCR : DTCMCR write control
bits : 1 - 2 (2 bit)
access : read-write

AHBPCR : AHBPCR write control
bits : 2 - 4 (3 bit)
access : read-write

VTOR : VTOR write control
bits : 3 - 6 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read

KEY_CODE : Write enable code
bits : 16 - 47 (32 bit)
access : write


CHIPPERICKEN1

Peripheral Clock Enable Register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CHIPPERICKEN1 CHIPPERICKEN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PECKEN0 PECKEN1 PECKEN2 PECKEN3 PECKEN4 PECKEN5 PECKEN6 PECKEN7 PECKEN8 PECKEN9 PECKEN10 PECKEN11 PECKEN12 __reserve0 KEY_CODE

PECKEN0 : Clock supply to Timer 0, 1
bits : 0 - 0 (1 bit)
access : read-write

PECKEN1 : Clock supply to Timer 2, 3
bits : 1 - 2 (2 bit)
access : read-write

PECKEN2 : Clock supply to Timer 4, 5
bits : 2 - 4 (3 bit)
access : read-write

PECKEN3 : Clock supply to Timer 6, 7
bits : 3 - 6 (4 bit)
access : read-write

PECKEN4 : Clock supply to Timer 8, 9
bits : 4 - 8 (5 bit)
access : read-write

PECKEN5 : Clock supply to Timer 10, 11
bits : 5 - 10 (6 bit)
access : read-write

PECKEN6 : Clock supply to Timer 12, 13
bits : 6 - 12 (7 bit)
access : read-write

PECKEN7 : Clock supply to Timer 20
bits : 7 - 14 (8 bit)
access : read-write

PECKEN8 : Clock supply to Timer 21
bits : 8 - 16 (9 bit)
access : read-write

PECKEN9 : Clock supply to Timer 22
bits : 9 - 18 (10 bit)
access : read-write

PECKEN10 : Clock supply to Timer 23
bits : 10 - 20 (11 bit)
access : read-write

PECKEN11 : Clock supply to Timer 24
bits : 11 - 22 (12 bit)
access : read-write

PECKEN12 : Clock supply to Timer 25
bits : 12 - 24 (13 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 13 - 28 (16 bit)
access : read

KEY_CODE : Write enable code
bits : 16 - 47 (32 bit)
access : write


CHIPPERICKEN2

Peripheral Clock Enable Register 2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CHIPPERICKEN2 CHIPPERICKEN2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PECKEN0 PECKEN1 PECKEN2 PECKEN3 PECKEN4 PECKEN5 PECKEN6 PECKEN7 PECKEN8 PECKEN9 PECKEN10 PECKEN11 __reserve0 __reserve1 PECKEN14 __reserve2 KEY_CODE

PECKEN0 : Clock supply to A/D converter0
bits : 0 - 0 (1 bit)
access : read-write

PECKEN1 : Clock supply to A/D converter1
bits : 1 - 2 (2 bit)
access : read-write

PECKEN2 : Clock supply to A/D converter2
bits : 2 - 4 (3 bit)
access : read-write

PECKEN3 : Clock supply to MFA
bits : 3 - 6 (4 bit)
access : read-write

PECKEN4 : Clock supply to Serial Interface 0
bits : 4 - 8 (5 bit)
access : read-write

PECKEN5 : Clock supply to Serial Interface 1
bits : 5 - 10 (6 bit)
access : read-write

PECKEN6 : Clock supply to Serial Interface 2
bits : 6 - 12 (7 bit)
access : read-write

PECKEN7 : Clock supply to Serial Interface 3
bits : 7 - 14 (8 bit)
access : read-write

PECKEN8 : Clock supply to Serial Interface 4
bits : 8 - 16 (9 bit)
access : read-write

PECKEN9 : Clock supply to Serial Interface 5
bits : 9 - 18 (10 bit)
access : read-write

PECKEN10 : Clock supply to Serial Interface 6
bits : 10 - 20 (11 bit)
access : read-write

PECKEN11 : Clock supply to Serial Interface 7
bits : 11 - 22 (12 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 12 - 24 (13 bit)
access : read

__reserve1 : This bit must be set to 0 .
bits : 13 - 26 (14 bit)
access : read-write

PECKEN14 : Clock supply to SMBus controller 1
bits : 14 - 28 (15 bit)
access : read-write

__reserve2 : This bit must be set to 0 .
bits : 15 - 30 (16 bit)
access : read-write

KEY_CODE : Write enable code
bits : 16 - 47 (32 bit)
access : write


CHIPCKSEL

Clock Selection Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CHIPCKSEL CHIPCKSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASESEL __reserve0 KEY_CODE

BASESEL : Clock source selection for basic clock (BASECLK)
bits : 0 - 1 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read

KEY_CODE : Write enable code
bits : 16 - 47 (32 bit)
access : write


CHIPTRCCKCTR

Trace Clock Control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CHIPTRCCKCTR CHIPTRCCKCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCKDIV __reserve0 TCKDLY __reserve1 KEY_CODE

TCKDIV : Setting of trace clock division ratio for CPUCLK
bits : 0 - 4 (5 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 5 - 12 (8 bit)
access : read

TCKDLY : Trace data delay control
bits : 8 - 16 (9 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 9 - 24 (16 bit)
access : read

KEY_CODE : Write enable code
bits : 16 - 47 (32 bit)
access : write


CHIPCPUCKCTR

CPU Clock Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CHIPCPUCKCTR CHIPCPUCKCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPUCKDIV __reserve0 IOCKDIV __reserve1 KEY_CODE

CPUCKDIV : Setting of CPUCLK division ratio for BASECLK
bits : 0 - 1 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 5 (4 bit)
access : read

IOCKDIV : Setting of IOCLK division ratio for CPUCLK
bits : 4 - 9 (6 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 6 - 21 (16 bit)
access : read

KEY_CODE : Write enable code
bits : 16 - 47 (32 bit)
access : write


CHIPCKWAIT

Clock Oscillation Stabilization Wait Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CHIPCKWAIT CHIPCKWAIT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HXOWAIT __reserve0 KEY_CODE

HXOWAIT : HXO oscillation stabilization wait cycle setting
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read

KEY_CODE : Write enable code
bits : 16 - 47 (32 bit)
access : write



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