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MAP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x60 byte (0x0)
mem_usage : registers
protection :

Registers

TCMDECCCNT

TCMD0SBEA

TCMD1SBEA

TCMDSBEDET

TCMDSBECLR

TCMD0MBEA

TCMD1MBEA

TCMDMBEDET

TCMDMBECLR

TCMIECCCNT

TCMIWAIT

TCMICBEN

TCMDWAIT

TCMISBEA

TCMISBEDET

TCMISBECLR

TCMIMBEA

TCMIMBEDET

TCMIMBECLR

TCMDCBEN


TCMDECCCNT

D0TCM/D1TCM ECC Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TCMDECCCNT TCMDECCCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECCMOD __reserve0 KEY_CODE

ECCMOD : ECC enable [D0TCM, D1TCM]
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read

KEY_CODE : When TCMDECCCNT.KEY_CODE is set to 0x3CA5 , TCMDECCCNT is updating.
bits : 16 - 47 (32 bit)
access : read-write


TCMD0SBEA

D0TCM 1-bit Error Address Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TCMD0SBEA TCMD0SBEA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBEADD

SBEADD : The 1-bit error address [D0TCM]
bits : 0 - 31 (32 bit)
access : read


TCMD1SBEA

D1TCM 1-bit Error Address Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TCMD1SBEA TCMD1SBEA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBEADD

SBEADD : The 1-bit error address [D1TCM]
bits : 0 - 31 (32 bit)
access : read


TCMDSBEDET

D0TCM/D1TCM 1-bit Error Detection Register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

TCMDSBEDET TCMDSBEDET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0SBE __reserve0 D0MASTER D1SBE __reserve1 D1MASTER

D0SBE : 1-bit error detection bit [D0TCM]
bits : 0 - 0 (1 bit)
access : read

__reserve0 : 0 is always read out.
bits : 1 - 4 (4 bit)
access : read

D0MASTER : Memory access at 1-bit error [D0TCM]
bits : 4 - 11 (8 bit)
access : read

D1SBE : 1-bit error detection bit [D1TCM]
bits : 8 - 16 (9 bit)
access : read

__reserve1 : 0 is always read out.
bits : 9 - 20 (12 bit)
access : read

D1MASTER : Memory access at 1-bit error[D1TCM]
bits : 12 - 27 (16 bit)
access : read


TCMDSBECLR

D0TCM/D1TCM 1-bit Error Detection Clear Register
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

TCMDSBECLR TCMDSBECLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 D0SBECLR D1SBECLR __reserve0

D0SBECLR : Clear the 1-bit error detection [D0TCM]
bits : 0 - 0 (1 bit)
access : read-write

D1SBECLR : Clear the 1-bit error detection [D1TCM]
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 9 (8 bit)
access : read


TCMD0MBEA

D0TCM 2-bit Error Address Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TCMD0MBEA TCMD0MBEA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBEADD

MBEADD : The 2-bit error or hard error address [D0TCM]
bits : 0 - 31 (32 bit)
access : read


TCMD1MBEA

D1TCM 2-bit Error Address Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TCMD1MBEA TCMD1MBEA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBEADD

MBEADD : The 2-bit error or hard error address [D1TCM]
bits : 0 - 31 (32 bit)
access : read


TCMDMBEDET

D0TCM/D1TCM 2-bit Error Detection Register
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

TCMDMBEDET TCMDMBEDET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0MBE D0HDE __reserve0 D0MASTER D1MBE D1HDE __reserve1 D1MASTER

D0MBE : 2-bit error detection bit [D0TCM]
bits : 0 - 0 (1 bit)
access : read

D0HDE : Hard error detection bit [D0TCM]
bits : 1 - 2 (2 bit)
access : read

__reserve0 : 0 is always read out.
bits : 2 - 5 (4 bit)
access : read

D0MASTER : Memory access at 2-bit error [D0TCM]
bits : 4 - 11 (8 bit)
access : read

D1MBE : 2-bit error detection bit [D1TCM]
bits : 8 - 16 (9 bit)
access : read

D1HDE : Hard error detection bit [D1TCM]
bits : 9 - 18 (10 bit)
access : read

__reserve1 : 0 is always read out.
bits : 10 - 21 (12 bit)
access : read

D1MASTER : Memory access at 2-bit error[D1TCM]
bits : 12 - 27 (16 bit)
access : read


TCMDMBECLR

D0TCM/D1TCM 2-bit Error Detection Clear Register
address_offset : 0x2C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

TCMDMBECLR TCMDMBECLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 D0MBECLR D1MBECLR __reserve0 __reserve1

D0MBECLR : Clear the 2-bit error and hard error detection [D0TCM]
bits : 0 - 0 (1 bit)
access : read-write

D1MBECLR : Clear the 2-bit error and hard error detection [D1TCM]
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 4 (3 bit)
access : read

__reserve1 : 0 is always read out.
bits : 3 - 10 (8 bit)
access : read


TCMIECCCNT

ITCM ECC Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TCMIECCCNT TCMIECCCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECCMOD __reserve0 KEY_CODE

ECCMOD : ECC enable [ITCM]
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read

KEY_CODE : When TCMIECCCNT.KEY_CODE is set to 0xA5C3 , TCMIECCCNT is updating.
bits : 16 - 47 (32 bit)
access : read-write


TCMIWAIT

ITCM Wait Setting Register
address_offset : 0x34 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

TCMIWAIT TCMIWAIT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WAIT __reserve0

WAIT : Wait setting [ITCM]
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 8 (8 bit)
access : read


TCMICBEN

ITCM Check Bit Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TCMICBEN TCMICBEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CBEN __reserve0 KEY_CODE

CBEN : Check bit read/write enable [ITCM]
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 16 (16 bit)
access : read

KEY_CODE : When TCMICBEN.KEY_CODE is set to 0xA5C3 , TCMICBEN is updating.
bits : 16 - 47 (32 bit)
access : read-write


TCMDWAIT

D0TCM/D1TCM Wait Setting Register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

TCMDWAIT TCMDWAIT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WAIT __reserve0

WAIT : Wait setting [D0TCM, D1TCM]
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 8 (8 bit)
access : read


TCMISBEA

ITCM 1-bit Error Address Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TCMISBEA TCMISBEA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBEADD

SBEADD : The 1bit error address [ITCM]
bits : 0 - 31 (32 bit)
access : read


TCMISBEDET

ITCM 1-bit Error Detection Register
address_offset : 0x48 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

TCMISBEDET TCMISBEDET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SBE __reserve0 MASTER

SBE : 1-bit error detection bit [ITCM]
bits : 0 - 0 (1 bit)
access : read

__reserve0 : 0 is always read out.
bits : 1 - 4 (4 bit)
access : read

MASTER : Memory access at 1-bit error [ITCM]
bits : 4 - 11 (8 bit)
access : read


TCMISBECLR

ITCM 1-bit Error Detection Clear Register
address_offset : 0x4C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

TCMISBECLR TCMISBECLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SBECLR __reserve0

SBECLR : Clear the 1-bit error detection [ITCM]
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 8 (8 bit)
access : read


TCMIMBEA

ITCM 2-bit Error Address Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TCMIMBEA TCMIMBEA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBEADD

MBEADD : The 2-bit error or hard error address [ITCM]
bits : 0 - 31 (32 bit)
access : read


TCMIMBEDET

ITCM 2-bit Error Detection Register
address_offset : 0x58 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

TCMIMBEDET TCMIMBEDET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MBE HDE __reserve0 MASTER

MBE : 2-bit error detection bit [ITCM]
bits : 0 - 0 (1 bit)
access : read

HDE : Hard error detection bit [ITCM]
bits : 1 - 2 (2 bit)
access : read

__reserve0 : 0 is always read out.
bits : 2 - 5 (4 bit)
access : read

MASTER : Memory access at 2-bit error [ITCM]
bits : 4 - 11 (8 bit)
access : read


TCMIMBECLR

ITCM 2-bit Error Detection Clear Register
address_offset : 0x5C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

TCMIMBECLR TCMIMBECLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MBECLR __reserve0

MBECLR : Clear the 2-bit error and hard error detection [ITCM]
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 8 (8 bit)
access : read


TCMDCBEN

D0TCM/D1TCM Check Bit Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

TCMDCBEN TCMDCBEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0CBEN D1CBEN __reserve0 KEY_CODE

D0CBEN : Check bit read/write enable [D0TCM]
bits : 0 - 0 (1 bit)
access : read-write

D1CBEN : Check bit read/write enable [D1TCM]
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 17 (16 bit)
access : read

KEY_CODE : When TCMDCBEN.KEY_CODE is set to 0x3CA5 , TCMDCBEN is updating.
bits : 16 - 47 (32 bit)
access : read-write



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