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FL

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xE4 byte (0x0)
mem_usage : registers
protection :

Registers

FIFEWEN

FIWDATA0

FIWDATA1

FISPROSTR

FISPROEND

FIHPRO0STRI

FIHPRO0ENDI

FIHPRO1STRI

FIHPRO1ENDI

FIHPRO0STRD

FIHPRO0ENDD

FIHPRO1STRD

FIHPRO1ENDD

FIFWCNT

FIFMON

FIFIIECNT

FIFISBEA

FIFISBDET

FIFISBCLR

FIFIMBEA

FIFIMBDET

FIFIMBCLR

FIFIWAIT

FIDBGDETI

FIDBGCLRI

FIFDIECNT

FIFDSBEA

FIFDSBDET

FIPEADR

FIFDSBCLR

FIFDMBEA

FIFDMBDET

FIFDMBCLR

FIFDWAIT

FIDBGDETD

FIDBGCLRD

FINSWAPREG


FIFEWEN

Rewriting Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIFEWEN FIFEWEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FEWEN KEY_CODE __reserve0

FEWEN : Setup enable/disable the flash memory to be rewritten
bits : 0 - 7 (8 bit)
access : read-write

KEY_CODE : Register Key
bits : 8 - 23 (16 bit)
access : write

__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


FIWDATA0

Writing Data Register 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIWDATA0 FIWDATA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA0

WDATA0 : Set the data to be written to the flash memory. This is the lower 4 bytes of the data to be rewritten (8 bytes).
bits : 0 - 31 (32 bit)
access : read-write


FIWDATA1

Writing Data Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIWDATA1 FIWDATA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA1

WDATA1 : Set the data to be written to the flash memory. This is the upper 4 bytes of the data to be rewritten (8 bytes).
bits : 0 - 31 (32 bit)
access : read-write


FISPROSTR

SW Protect Start Address
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FISPROSTR FISPROSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPROSTR

SPROSTR : SW protect start address
bits : 0 - 31 (32 bit)
access : read-write


FISPROEND

SW Protect End Address
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FISPROEND FISPROEND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPROEND

SPROEND : SW protect end address
bits : 0 - 31 (32 bit)
access : read-write


FIHPRO0STRI

I-Flash HW Protect 0 Start Address
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIHPRO0STRI FIHPRO0STRI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HPRO0STRI

HPRO0STRI : I-Flash HW protect 0 start address
bits : 0 - 31 (32 bit)
access : read


FIHPRO0ENDI

I-Flash HW Protect 0 End Address
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIHPRO0ENDI FIHPRO0ENDI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HPRO0ENDI

HPRO0ENDI : I-Flash HW protect 0 end address
bits : 0 - 31 (32 bit)
access : read


FIHPRO1STRI

I-Flash HW Protect 1 Start Address
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIHPRO1STRI FIHPRO1STRI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HPRO1STRI

HPRO1STRI : I-Flash HW protect 1 start address
bits : 0 - 31 (32 bit)
access : read


FIHPRO1ENDI

I-Flash HW Protect 1 End Address
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIHPRO1ENDI FIHPRO1ENDI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HPRO1ENDI

HPRO1ENDI : I-Flash HW protect 1 end address
bits : 0 - 31 (32 bit)
access : read


FIHPRO0STRD

D-Flash HW Protect 0 Start Address
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIHPRO0STRD FIHPRO0STRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HPRO0STRD

HPRO0STRD : D-Flash HW protect 0 start address
bits : 0 - 31 (32 bit)
access : read


FIHPRO0ENDD

D-Flash HW Protect 0 End Address
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIHPRO0ENDD FIHPRO0ENDD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HPRO0ENDD

HPRO0ENDD : D-Flash HW protect 0 end address
bits : 0 - 31 (32 bit)
access : read


FIHPRO1STRD

D-Flash HW Protect 1 Start Address
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIHPRO1STRD FIHPRO1STRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HPRO1STRD

HPRO1STRD : D-Flash HW protect 1 start address
bits : 0 - 31 (32 bit)
access : read


FIHPRO1ENDD

D-Flash HW Protect 1 End Address
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIHPRO1ENDD FIHPRO1ENDD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HPRO1ENDD

HPRO1ENDD : D-Flash HW protect 1 end address
bits : 0 - 31 (32 bit)
access : read


FIFWCNT

Rewriting Start Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIFWCNT FIFWCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START ERASEMD __reserve0

START : Start Program/Erase function
bits : 0 - 0 (1 bit)
access : read-write

ERASEMD : Select Program/Erase function
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 33 (32 bit)
access : read


FIFMON

Rewriting Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIFMON FIFMON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WBUSY __reserve0 __reserve1 NBRANK OUTADR SPRO HPROI0 HPROI1 HPROD0 HPROD1 __reserve2 __reserve3

WBUSY : Rewriting execution flag
bits : 0 - 0 (1 bit)
access : read

__reserve0 : Undefined value will be read
bits : 1 - 3 (3 bit)
access : read

__reserve1 : 0 is always read out.
bits : 3 - 10 (8 bit)
access : read

NBRANK : Writing blank error flag
bits : 8 - 16 (9 bit)
access : read

OUTADR : Rewriting address error flag
bits : 9 - 18 (10 bit)
access : read

SPRO : Rewriting SW protect error flag
bits : 10 - 20 (11 bit)
access : read

HPROI0 : I-Flash HW protect 0 error flag
bits : 11 - 22 (12 bit)
access : read

HPROI1 : I-Flash HW protect 1 error flag
bits : 12 - 24 (13 bit)
access : read

HPROD0 : D-Flash HW protect 0 error flag
bits : 13 - 26 (14 bit)
access : read

HPROD1 : D-Flash HW protect 1 error flag
bits : 14 - 28 (15 bit)
access : read

__reserve2 : 0 is always read out.
bits : 15 - 30 (16 bit)
access : read

__reserve3 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


FIFIIECNT

I-Flash ECC Control Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIFIIECNT FIFIIECNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECCMOD __reserve0 __reserve1 KEY_CODE __reserve2

ECCMOD : I-Flash ECC enable
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : This bit must be set to 0 .
bits : 1 - 2 (2 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 2 - 9 (8 bit)
access : read

KEY_CODE : Register Key
bits : 8 - 23 (16 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


FIFISBEA

I-Flash 1-bit Error Address
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIFISBEA FIFISBEA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBEA

SBEA : I-Flash ECC 1-bit error interrupt target address
bits : 0 - 31 (32 bit)
access : read


FIFISBDET

I-Flash 1-bit Error Detection Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIFISBDET FIFISBDET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBDET __reserve0 SBMASTER __reserve1

SBDET : I-Flash ECC 1-bit error interrupt target address
bits : 0 - 0 (1 bit)
access : read

__reserve0 : 0 is always read out.
bits : 1 - 8 (8 bit)
access : read

SBMASTER : I-Flash ECC 1-bit error interrupt generation master information
bits : 8 - 19 (12 bit)
access : read

__reserve1 : 0 is always read out.
bits : 12 - 43 (32 bit)
access : read


FIFISBCLR

I-Flash 1-bit Error Interrupt Clear Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIFISBCLR FIFISBCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBECLRI __reserve0

SBECLRI : [Write]
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


FIFIMBEA

I-Flash 2-bit or more Error Address
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIFIMBEA FIFIMBEA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBEA

MBEA : I-Flash ECC 2-bit error interrupt target address
bits : 0 - 31 (32 bit)
access : read


FIFIMBDET

I-Flash 2-bit or more Error Detection Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIFIMBDET FIFIMBDET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBDET __reserve0 MBMASTER __reserve1

MBDET : I-Flash ECC 2-bit error interrupt target address
bits : 0 - 0 (1 bit)
access : read

__reserve0 : 0 is always read out.
bits : 1 - 8 (8 bit)
access : read

MBMASTER : I-Flash ECC 2-bit error interrupt generation master information
bits : 8 - 19 (12 bit)
access : read

__reserve1 : 0 is always read out.
bits : 12 - 43 (32 bit)
access : read


FIFIMBCLR

I-Flash 2-bit or more Error Interrupt Clear Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIFIMBCLR FIFIMBCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBECLRI __reserve0

MBECLRI : [Write]
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


FIFIWAIT

I-Flash Access Wait Control Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIFIWAIT FIFIWAIT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITREG __reserve0 KEY_CODE __reserve1

WAITREG : I-Flash Read access wait setting
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

KEY_CODE : Register Key
bits : 8 - 23 (16 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


FIDBGDETI

I-Flash Debug Access Error Detection Register
address_offset : 0xA8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

FIDBGDETI FIDBGDETI read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DBGSDET DBGMDET __reserve0

DBGSDET : I-Flash 1-bit error detection at debugger access
bits : 0 - 0 (1 bit)
access : read

DBGMDET : I-Flash 2-bit or more error detection at debugger access
bits : 1 - 2 (2 bit)
access : read

__reserve0 : 0 is always read out.
bits : 2 - 9 (8 bit)
access : read


FIDBGCLRI

I-Flash Debug Access Error Detection Clear Register
address_offset : 0xAC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

FIDBGCLRI FIDBGCLRI read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DBGSCLR DBGMCLR __reserve0

DBGSCLR : I-Flash 1-bit error detection at debugger access clear
bits : 0 - 0 (1 bit)
access : read-write

DBGMCLR : I-Flash 2-bit or more error detection at debugger access clear
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 9 (8 bit)
access : read


FIFDIECNT

D-Flash ECC Control Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIFDIECNT FIFDIECNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECCMOD __reserve0 __reserve1 KEY_CODE __reserve2

ECCMOD : D-Flash ECC enable
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : This bit must be set to 0 .
bits : 1 - 2 (2 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 2 - 9 (8 bit)
access : read

KEY_CODE : Register Key
bits : 8 - 23 (16 bit)
access : read-write

__reserve2 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


FIFDSBEA

D-Flash 1-bit Error Address
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIFDSBEA FIFDSBEA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBEA

SBEA : D-Flash ECC 1-bit error interrupt target address
bits : 0 - 31 (32 bit)
access : read


FIFDSBDET

D-Flash 1-bit Error Detection Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIFDSBDET FIFDSBDET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBDET __reserve0 SBMASTER __reserve1

SBDET : D-Flash ECC 1-bit error interrupt target address
bits : 0 - 0 (1 bit)
access : read

__reserve0 : 0 is always read out.
bits : 1 - 8 (8 bit)
access : read

SBMASTER : D-Flash ECC 1-bit error interrupt generation master information
bits : 8 - 19 (12 bit)
access : read

__reserve1 : 0 is always read out.
bits : 12 - 43 (32 bit)
access : read


FIPEADR

Rewriting Destination Address Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIPEADR FIPEADR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PEADR

PEADR : Rewriting (write/erase) address
bits : 0 - 31 (32 bit)
access : read-write


FIFDSBCLR

D-Flash 1-bit Error Interrupt Clear Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIFDSBCLR FIFDSBCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBECLRI __reserve0

SBECLRI : [Write]
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


FIFDMBEA

D-Flash 2-bit or more Error Address
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIFDMBEA FIFDMBEA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBEA

MBEA : D-Flash ECC 2-bit error interrupt target address
bits : 0 - 31 (32 bit)
access : read


FIFDMBDET

D-Flash 2-bit or more Error Detection Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIFDMBDET FIFDMBDET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBDET __reserve0 MBMASTER __reserve1

MBDET : D-Flash ECC 2-bit error interrupt target address
bits : 0 - 0 (1 bit)
access : read

__reserve0 : 0 is always read out.
bits : 1 - 8 (8 bit)
access : read

MBMASTER : D-Flash ECC 2-bit error interrupt generation master information
bits : 8 - 19 (12 bit)
access : read

__reserve1 : 0 is always read out.
bits : 12 - 43 (32 bit)
access : read


FIFDMBCLR

D-Flash 2-bit or more Error Interrupt Clear Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIFDMBCLR FIFDMBCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBECLRI __reserve0

MBECLRI : [Write]
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read


FIFDWAIT

D-Flash Access Wait Control Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FIFDWAIT FIFDWAIT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITREG __reserve0 KEY_CODE __reserve1

WAITREG : D-Flash Read access wait setting
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

KEY_CODE : Register Key
bits : 8 - 23 (16 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read


FIDBGDETD

D-Flash Debug Access Error Detection Register
address_offset : 0xD8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

FIDBGDETD FIDBGDETD read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DBGSDET DBGMDET __reserve0

DBGSDET : D-Flash 1-bit error detection at debugger access
bits : 0 - 0 (1 bit)
access : read

DBGMDET : D-Flash 2-bit or more error detection at debugger access
bits : 1 - 2 (2 bit)
access : read

__reserve0 : 0 is always read out.
bits : 2 - 9 (8 bit)
access : read


FIDBGCLRD

D-Flash Debug Access Error Detection Clear Register
address_offset : 0xDC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

FIDBGCLRD FIDBGCLRD read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DBGSCLR DBGMCLR __reserve0

DBGSCLR : D-Flash 1-bit error detection at debugger access clear
bits : 0 - 0 (1 bit)
access : read-write

DBGMCLR : D-Flash 2-bit or more error detection at debugger access clear
bits : 1 - 2 (2 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 2 - 9 (8 bit)
access : read


FINSWAPREG

Swap Switching Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FINSWAPREG FINSWAPREG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NSWAPON __reserve0 KEY_CODE __reserve1

NSWAPON : Boot sector swap setting
bits : 0 - 0 (1 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 1 - 8 (8 bit)
access : read

KEY_CODE : Register Key
bits : 8 - 23 (16 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read



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