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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2B4 byte (0x0)
mem_usage : registers
protection :

Registers

ADC0CTR0

ADC0ST

ADC1CTR0

ADC1CTR1A

ADC1CTR1B

ADC1ST

ADC1CTREGA

ADC1CTREGB

ADC1CHSEL00

ADC1CHSEL01

ADC1CHSEL02

ADC1CHSEL03

ADC1CHSEL04

ADC1CHSEL05

ADC1CHSEL06

ADC1CHSEL07

ADC1CHSEL08

ADC1CHSEL09

ADC1CHSEL10

ADC1CHSEL11

ADC1CHSEL12

ADC1CHSEL13

ADC1CHSEL14

ADC1CHSEL15

ADC0CTREGA

ADC1CHSELB0

ADC1CHSELB1

ADC1CHSELB2

ADC1CHSELB3

ADC1ERCA

ADC1ERCB

ADC1LOWA

ADC1UPA

ADC1LOWB

ADC1UPB

ADC1BUF00

ADC1BUF01

ADC1BUF02

ADC1BUF03

ADC1BUF04

ADC1BUF05

ADC1BUF06

ADC1BUF07

ADC0CTREGB

ADC1BUF08

ADC1BUF09

ADC1BUF10

ADC1BUF11

ADC1BUF12

ADC1BUF13

ADC1BUF14

ADC1BUF15

ADC1BUFB0

ADC1BUFB1

ADC1BUFB2

ADC1BUFB3

ADC1CHECK

ADC0CHSEL00

ADC2CTR0

ADC2CTR1A

ADC2CTR1B

ADC2ST

ADC2CTREGA

ADC2CTREGB

ADC0CHSEL01

ADC2CHSEL00

ADC2CHSEL01

ADC2CHSEL02

ADC2CHSEL03

ADC2CHSEL04

ADC2CHSEL05

ADC2CHSEL06

ADC2CHSEL07

ADC2CHSEL08

ADC2CHSEL09

ADC2CHSEL10

ADC2CHSEL11

ADC2CHSEL12

ADC2CHSEL13

ADC2CHSEL14

ADC2CHSEL15

ADC0CHSEL02

ADC2CHSELB0

ADC2CHSELB1

ADC2CHSELB2

ADC2CHSELB3

ADC2ERCA

ADC2ERCB

ADC2LOWA

ADC2UPA

ADC2LOWB

ADC2UPB

ADC0CHSEL03

ADC2BUF00

ADC2BUF01

ADC2BUF02

ADC2BUF03

ADC2BUF04

ADC2BUF05

ADC2BUF06

ADC2BUF07

ADC0CHSEL04

ADC2BUF08

ADC2BUF09

ADC2BUF10

ADC2BUF11

ADC2BUF12

ADC2BUF13

ADC2BUF14

ADC2BUF15

ADC0CHSEL05

ADC2BUFB0

ADC2BUFB1

ADC2BUFB2

ADC2BUFB3

ADC2CHECK

ADC0CHSEL06

ADC0CHSEL07

ADC0CHSEL08

ADC0CHSEL09

ADC0CHSEL10

ADC0CHSEL11

ADC0CHSEL12

ADC0CHSEL13

ADC0CHSEL14

ADC0CHSEL15

ADC0CTR1A

ADC0CHSELB0

ADC0CHSELB1

ADC0CHSELB2

ADC0CHSELB3

ADC0ERCA

ADC0ERCB

ADC0LOWA

ADC0UPA

ADC0LOWB

ADC0UPB

ADC0BUF00

ADC0BUF01

ADC0BUF02

ADC0BUF03

ADC0BUF04

ADC0BUF05

ADC0BUF06

ADC0BUF07

ADC0CTR1B

ADC0BUF08

ADC0BUF09

ADC0BUF10

ADC0BUF11

ADC0BUF12

ADC0BUF13

ADC0BUF14

ADC0BUF15

ADC0BUFB0

ADC0BUFB1

ADC0BUFB2

ADC0BUFB3

ADC0CHECK


ADC0CTR0

A/D0 Co0versio0 Co0trol Register 0
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0CTR0 ADC0CTR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ON CK __reserve0

ON : A/Dn operation mode
bits : 0 - 0 (1 bit)
access : read-write

CK : ADCK select
bits : 1 - 4 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read


ADC0ST

A/D0 Co0versio0 Start Trigger Selectio0 Register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0ST ADC0ST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AST __reserve0 BST __reserve1

AST : Start trigger A for A/Dn conversion
bits : 0 - 4 (5 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 5 - 12 (8 bit)
access : read

BST : Start trigger B for A/Dn conversion
bits : 8 - 20 (13 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 13 - 28 (16 bit)
access : read


ADC1CTR0

A/D1 Co1versio1 Co1trol Register 0
address_offset : 0x100 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1CTR0 ADC1CTR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ON CK __reserve0

ON : A/Dn operation mode
bits : 0 - 0 (1 bit)
access : read-write

CK : ADCK select
bits : 1 - 4 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read


ADC1CTR1A

A/D1 Co1versio1 Co1trol Register 1A
address_offset : 0x104 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1CTR1A ADC1CTR1A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AEN ATRG AMD __reserve0 AECH __reserve1

AEN : A/D conversion start
bits : 0 - 0 (1 bit)
access : read-write

ATRG : A/D conversion start by using trigger A
bits : 1 - 2 (2 bit)
access : read-write

AMD : A/D conversion mode select
bits : 2 - 4 (3 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 3 - 6 (4 bit)
access : read

AECH : Conversion end channel setting
bits : 4 - 11 (8 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read


ADC1CTR1B

A/D1 Co1versio1 Co1trol Register 1B
address_offset : 0x108 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1CTR1B ADC1CTR1B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BEN BTRG BMD __reserve0 BECH __reserve1

BEN : A/D conversion start
bits : 0 - 0 (1 bit)
access : read-write

BTRG : A/D conversion start by using trigger B
bits : 1 - 2 (2 bit)
access : read-write

BMD : A/D conversion mode select
bits : 2 - 4 (3 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 3 - 6 (4 bit)
access : read

BECH : Conversion end channel setting
bits : 4 - 9 (6 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 6 - 21 (16 bit)
access : read


ADC1ST

A/D1 Co1versio1 Start Trigger Selectio1 Register
address_offset : 0x110 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1ST ADC1ST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AST __reserve0 BST __reserve1

AST : Start trigger A for A/Dn conversion
bits : 0 - 4 (5 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 5 - 12 (8 bit)
access : read

BST : Start trigger B for A/Dn conversion
bits : 8 - 20 (13 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 13 - 28 (16 bit)
access : read


ADC1CTREGA

A/D1 Co1versio1 Start Trigger A Cou1t Register
address_offset : 0x114 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

ADC1CTREGA ADC1CTREGA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACNT ACNTI

ACNT : The number for reducing start trigger A (at the second or later A/D conversion)
bits : 0 - 3 (4 bit)
access : read-write

ACNTI : The number for reducing start trigger A (at the first A/D conversion)
bits : 4 - 11 (8 bit)
access : read-write


ADC1CTREGB

A/D1 Co1versio1 Start Trigger B Cou1t Register
address_offset : 0x118 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

ADC1CTREGB ADC1CTREGB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BCNT BCNTI

BCNT : The number for reducing start trigger B (at the second or later A/D conversion)
bits : 0 - 3 (4 bit)
access : read-write

BCNTI : The number for reducing start trigger B (at the first A/D conversion)
bits : 4 - 11 (8 bit)
access : read-write


ADC1CHSEL00

A/D1 Conversion Channel 00 Selection Register
address_offset : 0x120 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1CHSEL00 ADC1CHSEL00 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC1CHSEL01

A/D1 Conversion Channel 01 Selection Register
address_offset : 0x122 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1CHSEL01 ADC1CHSEL01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC1CHSEL02

A/D1 Conversion Channel 02 Selection Register
address_offset : 0x124 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1CHSEL02 ADC1CHSEL02 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC1CHSEL03

A/D1 Conversion Channel 03 Selection Register
address_offset : 0x126 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1CHSEL03 ADC1CHSEL03 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC1CHSEL04

A/D1 Conversion Channel 04 Selection Register
address_offset : 0x128 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1CHSEL04 ADC1CHSEL04 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC1CHSEL05

A/D1 Conversion Channel 05 Selection Register
address_offset : 0x12A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1CHSEL05 ADC1CHSEL05 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC1CHSEL06

A/D1 Conversion Channel 06 Selection Register
address_offset : 0x12C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1CHSEL06 ADC1CHSEL06 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC1CHSEL07

A/D1 Conversion Channel 07 Selection Register
address_offset : 0x12E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1CHSEL07 ADC1CHSEL07 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC1CHSEL08

A/D1 Conversion Channel 08 Selection Register
address_offset : 0x130 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1CHSEL08 ADC1CHSEL08 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC1CHSEL09

A/D1 Conversion Channel 09 Selection Register
address_offset : 0x132 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1CHSEL09 ADC1CHSEL09 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC1CHSEL10

A/D1 Conversion Channel 10 Selection Register
address_offset : 0x134 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1CHSEL10 ADC1CHSEL10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC1CHSEL11

A/D1 Conversion Channel 11 Selection Register
address_offset : 0x136 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1CHSEL11 ADC1CHSEL11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC1CHSEL12

A/D1 Conversion Channel 12 Selection Register
address_offset : 0x138 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1CHSEL12 ADC1CHSEL12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC1CHSEL13

A/D1 Conversion Channel 13 Selection Register
address_offset : 0x13A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1CHSEL13 ADC1CHSEL13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC1CHSEL14

A/D1 Conversion Channel 14 Selection Register
address_offset : 0x13C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1CHSEL14 ADC1CHSEL14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC1CHSEL15

A/D1 Conversion Channel 15 Selection Register
address_offset : 0x13E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1CHSEL15 ADC1CHSEL15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC0CTREGA

A/D0 Co0versio0 Start Trigger A Cou0t Register
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

ADC0CTREGA ADC0CTREGA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACNT ACNTI

ACNT : The number for reducing start trigger A (at the second or later A/D conversion)
bits : 0 - 3 (4 bit)
access : read-write

ACNTI : The number for reducing start trigger A (at the first A/D conversion)
bits : 4 - 11 (8 bit)
access : read-write


ADC1CHSELB0

A/D1 Conversion Channel B0 Selection Register
address_offset : 0x140 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1CHSELB0 ADC1CHSELB0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCHSEL __reserve0 BSHC __reserve1

BCHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

BSHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC1CHSELB1

A/D1 Conversion Channel B1 Selection Register
address_offset : 0x142 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1CHSELB1 ADC1CHSELB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCHSEL __reserve0 BSHC __reserve1

BCHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

BSHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC1CHSELB2

A/D1 Conversion Channel B2 Selection Register
address_offset : 0x144 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1CHSELB2 ADC1CHSELB2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCHSEL __reserve0 BSHC __reserve1

BCHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

BSHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC1CHSELB3

A/D1 Conversion Channel B3 Selection Register
address_offset : 0x146 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1CHSELB3 ADC1CHSELB3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCHSEL __reserve0 BSHC __reserve1

BCHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

BSHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC1ERCA

A/D1 Co1versio1 Error Detectio1 Cha11el Setti1g Register A
address_offset : 0x148 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1ERCA ADC1ERCA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERCACH0 ERCACH1 ERCACH2 ERCACH3 ERCACH4 ERCACH5 ERCACH6 ERCACH7 ERCACH8 ERCACH9 ERCACH10 ERCACH11 ERCACH12 ERCACH13 ERCACH14 ERCACH15

ERCACH0 : Error detection setting (the channel selected by setting ANnCHSEL00).
bits : 0 - 0 (1 bit)
access : read-write

ERCACH1 : Error detection setting (the channel selected by setting ANnCHSEL01).
bits : 1 - 2 (2 bit)
access : read-write

ERCACH2 : Error detection setting (the channel selected by setting ANnCHSEL02).
bits : 2 - 4 (3 bit)
access : read-write

ERCACH3 : Error detection setting (the channel selected by setting ANnCHSEL03).
bits : 3 - 6 (4 bit)
access : read-write

ERCACH4 : Error detection setting (the channel selected by setting ANnCHSEL04).
bits : 4 - 8 (5 bit)
access : read-write

ERCACH5 : Error detection setting (the channel selected by setting ANnCHSEL05).
bits : 5 - 10 (6 bit)
access : read-write

ERCACH6 : Error detection setting (the channel selected by setting ANnCHSEL06).
bits : 6 - 12 (7 bit)
access : read-write

ERCACH7 : Error detection setting (the channel selected by setting ANnCHSEL07).
bits : 7 - 14 (8 bit)
access : read-write

ERCACH8 : Error detection setting (the channel selected by setting ANnCHSEL08).
bits : 8 - 16 (9 bit)
access : read-write

ERCACH9 : Error detection setting (the channel selected by setting ANnCHSEL09).
bits : 9 - 18 (10 bit)
access : read-write

ERCACH10 : Error detection setting (the channel selected by setting ANnCHSEL10).
bits : 10 - 20 (11 bit)
access : read-write

ERCACH11 : Error detection setting (the channel selected by setting ANnCHSEL11).
bits : 11 - 22 (12 bit)
access : read-write

ERCACH12 : Error detection setting (the channel selected by setting ANnCHSEL12).
bits : 12 - 24 (13 bit)
access : read-write

ERCACH13 : Error detection setting (the channel selected by setting ANnCHSEL13).
bits : 13 - 26 (14 bit)
access : read-write

ERCACH14 : Error detection setting (the channel selected by setting ANnCHSEL14).
bits : 14 - 28 (15 bit)
access : read-write

ERCACH15 : Error detection setting (the channel selected by setting ANnCHSEL15).
bits : 15 - 30 (16 bit)
access : read-write


ADC1ERCB

A/D1 Co1versio1 Error Detectio1 Cha11el Setti1g Register B
address_offset : 0x14C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1ERCB ADC1ERCB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERCBCH0 ERCBCH1 ERCBCH2 ERCBCH3 __reserve0

ERCBCH0 : Error detection setting (the channel selected by setting ANnCHSELB0).
bits : 0 - 0 (1 bit)
access : read-write

ERCBCH1 : Error detection setting (the channel selected by setting ANnCHSELB1).
bits : 1 - 2 (2 bit)
access : read-write

ERCBCH2 : Error detection setting (the channel selected by setting ANnCHSELB2).
bits : 2 - 4 (3 bit)
access : read-write

ERCBCH3 : Error detection setting (the channel selected by setting ANnCHSELB3).
bits : 3 - 6 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read


ADC1LOWA

A/D1 Co1versio1 Error Detectio1 Lower Limit Setti1g Register A
address_offset : 0x150 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1LOWA ADC1LOWA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOWA __reserve0

LOWA : Set the lower limit of A/Dn conversion result (trigger A)
bits : 0 - 11 (12 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC1UPA

A/D1 Co1versio1 Error Detectio1 Upper Limit Setti1g Register A
address_offset : 0x154 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1UPA ADC1UPA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPA __reserve0

UPA : Set the upper limit of A/Dn conversion result (trigger A)
bits : 0 - 11 (12 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC1LOWB

A/D1 Co1versio1 Error Detectio1 Lower Limit Setti1g Register B
address_offset : 0x158 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1LOWB ADC1LOWB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOWB __reserve0

LOWB : Set the lower limit of A/Dn conversion result (trigger B)
bits : 0 - 11 (12 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC1UPB

A/D1 Co1versio1 Error Detectio1 Upper Limit Setti1g Register B
address_offset : 0x15C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1UPB ADC1UPB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPB __reserve0

UPB : Set the upper limit of A/Dn conversion result (trigger B)
bits : 0 - 11 (12 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC1BUF00

A/D1 Conversion Data Buffer 00 Register
address_offset : 0x160 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1BUF00 ADC1BUF00 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC1CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC1BUF01

A/D1 Conversion Data Buffer 01 Register
address_offset : 0x164 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1BUF01 ADC1BUF01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC1CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC1BUF02

A/D1 Conversion Data Buffer 02 Register
address_offset : 0x168 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1BUF02 ADC1BUF02 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC1CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC1BUF03

A/D1 Conversion Data Buffer 03 Register
address_offset : 0x16C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1BUF03 ADC1BUF03 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC1CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC1BUF04

A/D1 Conversion Data Buffer 04 Register
address_offset : 0x170 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1BUF04 ADC1BUF04 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC1CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC1BUF05

A/D1 Conversion Data Buffer 05 Register
address_offset : 0x174 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1BUF05 ADC1BUF05 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC1CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC1BUF06

A/D1 Conversion Data Buffer 06 Register
address_offset : 0x178 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1BUF06 ADC1BUF06 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC1CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC1BUF07

A/D1 Conversion Data Buffer 07 Register
address_offset : 0x17C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1BUF07 ADC1BUF07 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC1CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0CTREGB

A/D0 Co0versio0 Start Trigger B Cou0t Register
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

ADC0CTREGB ADC0CTREGB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BCNT BCNTI

BCNT : The number for reducing start trigger B (at the second or later A/D conversion)
bits : 0 - 3 (4 bit)
access : read-write

BCNTI : The number for reducing start trigger B (at the first A/D conversion)
bits : 4 - 11 (8 bit)
access : read-write


ADC1BUF08

A/D1 Conversion Data Buffer 08 Register
address_offset : 0x180 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1BUF08 ADC1BUF08 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC1CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC1BUF09

A/D1 Conversion Data Buffer 09 Register
address_offset : 0x184 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1BUF09 ADC1BUF09 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC1CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC1BUF10

A/D1 Conversion Data Buffer 10 Register
address_offset : 0x188 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1BUF10 ADC1BUF10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC1CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC1BUF11

A/D1 Conversion Data Buffer 11 Register
address_offset : 0x18C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1BUF11 ADC1BUF11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC1CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC1BUF12

A/D1 Conversion Data Buffer 12 Register
address_offset : 0x190 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1BUF12 ADC1BUF12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC1CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC1BUF13

A/D1 Conversion Data Buffer 13 Register
address_offset : 0x194 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1BUF13 ADC1BUF13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC1CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC1BUF14

A/D1 Conversion Data Buffer 14 Register
address_offset : 0x198 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1BUF14 ADC1BUF14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC1CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC1BUF15

A/D1 Conversion Data Buffer 15 Register
address_offset : 0x19C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1BUF15 ADC1BUF15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC1CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC1BUFB0

A/D1 Conversion Data Buffer B0 Register
address_offset : 0x1A0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1BUFB0 ADC1BUFB0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFB __reserve0

BUFB : A/D conversion results of the channel selected by setting ADC1CHSELBm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC1BUFB1

A/D1 Conversion Data Buffer B1 Register
address_offset : 0x1A4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1BUFB1 ADC1BUFB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFB __reserve0

BUFB : A/D conversion results of the channel selected by setting ADC1CHSELBm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC1BUFB2

A/D1 Conversion Data Buffer B2 Register
address_offset : 0x1A8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1BUFB2 ADC1BUFB2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFB __reserve0

BUFB : A/D conversion results of the channel selected by setting ADC1CHSELBm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC1BUFB3

A/D1 Conversion Data Buffer B3 Register
address_offset : 0x1AC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC1BUFB3 ADC1BUFB3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFB __reserve0

BUFB : A/D conversion results of the channel selected by setting ADC1CHSELBm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC1CHECK

A/D1 Fault Check Co1trol Register
address_offset : 0x1B0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

ADC1CHECK ADC1CHECK read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHKEN CHKSEL __reserve0

CHKEN : Fault diagnosis function select
bits : 0 - 0 (1 bit)
access : read-write

CHKSEL : Conversion Potential select
bits : 1 - 3 (3 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 3 - 10 (8 bit)
access : read


ADC0CHSEL00

A/D0 Conversion Channel 00 Selection Register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0CHSEL00 ADC0CHSEL00 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC2CTR0

A/D2 Co2versio2 Co2trol Register 0
address_offset : 0x200 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2CTR0 ADC2CTR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ON CK __reserve0

ON : A/Dn operation mode
bits : 0 - 0 (1 bit)
access : read-write

CK : ADCK select
bits : 1 - 4 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read


ADC2CTR1A

A/D2 Co2versio2 Co2trol Register 1A
address_offset : 0x204 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2CTR1A ADC2CTR1A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AEN ATRG AMD __reserve0 AECH __reserve1

AEN : A/D conversion start
bits : 0 - 0 (1 bit)
access : read-write

ATRG : A/D conversion start by using trigger A
bits : 1 - 2 (2 bit)
access : read-write

AMD : A/D conversion mode select
bits : 2 - 4 (3 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 3 - 6 (4 bit)
access : read

AECH : Conversion end channel setting
bits : 4 - 11 (8 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read


ADC2CTR1B

A/D2 Co2versio2 Co2trol Register 1B
address_offset : 0x208 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2CTR1B ADC2CTR1B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BEN BTRG BMD __reserve0 BECH __reserve1

BEN : A/D conversion start
bits : 0 - 0 (1 bit)
access : read-write

BTRG : A/D conversion start by using trigger B
bits : 1 - 2 (2 bit)
access : read-write

BMD : A/D conversion mode select
bits : 2 - 4 (3 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 3 - 6 (4 bit)
access : read

BECH : Conversion end channel setting
bits : 4 - 9 (6 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 6 - 21 (16 bit)
access : read


ADC2ST

A/D2 Co2versio2 Start Trigger Selectio2 Register
address_offset : 0x210 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2ST ADC2ST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AST __reserve0 BST __reserve1

AST : Start trigger A for A/Dn conversion
bits : 0 - 4 (5 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 5 - 12 (8 bit)
access : read

BST : Start trigger B for A/Dn conversion
bits : 8 - 20 (13 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 13 - 28 (16 bit)
access : read


ADC2CTREGA

A/D2 Co2versio2 Start Trigger A Cou2t Register
address_offset : 0x214 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

ADC2CTREGA ADC2CTREGA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACNT ACNTI

ACNT : The number for reducing start trigger A (at the second or later A/D conversion)
bits : 0 - 3 (4 bit)
access : read-write

ACNTI : The number for reducing start trigger A (at the first A/D conversion)
bits : 4 - 11 (8 bit)
access : read-write


ADC2CTREGB

A/D2 Co2versio2 Start Trigger B Cou2t Register
address_offset : 0x218 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

ADC2CTREGB ADC2CTREGB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BCNT BCNTI

BCNT : The number for reducing start trigger B (at the second or later A/D conversion)
bits : 0 - 3 (4 bit)
access : read-write

BCNTI : The number for reducing start trigger B (at the first A/D conversion)
bits : 4 - 11 (8 bit)
access : read-write


ADC0CHSEL01

A/D0 Conversion Channel 01 Selection Register
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0CHSEL01 ADC0CHSEL01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC2CHSEL00

A/D2 Conversion Channel 00 Selection Register
address_offset : 0x220 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2CHSEL00 ADC2CHSEL00 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC2CHSEL01

A/D2 Conversion Channel 01 Selection Register
address_offset : 0x222 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2CHSEL01 ADC2CHSEL01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC2CHSEL02

A/D2 Conversion Channel 02 Selection Register
address_offset : 0x224 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2CHSEL02 ADC2CHSEL02 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC2CHSEL03

A/D2 Conversion Channel 03 Selection Register
address_offset : 0x226 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2CHSEL03 ADC2CHSEL03 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC2CHSEL04

A/D2 Conversion Channel 04 Selection Register
address_offset : 0x228 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2CHSEL04 ADC2CHSEL04 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC2CHSEL05

A/D2 Conversion Channel 05 Selection Register
address_offset : 0x22A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2CHSEL05 ADC2CHSEL05 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC2CHSEL06

A/D2 Conversion Channel 06 Selection Register
address_offset : 0x22C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2CHSEL06 ADC2CHSEL06 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC2CHSEL07

A/D2 Conversion Channel 07 Selection Register
address_offset : 0x22E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2CHSEL07 ADC2CHSEL07 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC2CHSEL08

A/D2 Conversion Channel 08 Selection Register
address_offset : 0x230 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2CHSEL08 ADC2CHSEL08 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC2CHSEL09

A/D2 Conversion Channel 09 Selection Register
address_offset : 0x232 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2CHSEL09 ADC2CHSEL09 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC2CHSEL10

A/D2 Conversion Channel 10 Selection Register
address_offset : 0x234 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2CHSEL10 ADC2CHSEL10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC2CHSEL11

A/D2 Conversion Channel 11 Selection Register
address_offset : 0x236 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2CHSEL11 ADC2CHSEL11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC2CHSEL12

A/D2 Conversion Channel 12 Selection Register
address_offset : 0x238 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2CHSEL12 ADC2CHSEL12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC2CHSEL13

A/D2 Conversion Channel 13 Selection Register
address_offset : 0x23A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2CHSEL13 ADC2CHSEL13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC2CHSEL14

A/D2 Conversion Channel 14 Selection Register
address_offset : 0x23C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2CHSEL14 ADC2CHSEL14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC2CHSEL15

A/D2 Conversion Channel 15 Selection Register
address_offset : 0x23E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2CHSEL15 ADC2CHSEL15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC0CHSEL02

A/D0 Conversion Channel 02 Selection Register
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0CHSEL02 ADC0CHSEL02 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC2CHSELB0

A/D2 Conversion Channel B0 Selection Register
address_offset : 0x240 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2CHSELB0 ADC2CHSELB0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCHSEL __reserve0 BSHC __reserve1

BCHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

BSHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC2CHSELB1

A/D2 Conversion Channel B1 Selection Register
address_offset : 0x242 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2CHSELB1 ADC2CHSELB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCHSEL __reserve0 BSHC __reserve1

BCHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

BSHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC2CHSELB2

A/D2 Conversion Channel B2 Selection Register
address_offset : 0x244 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2CHSELB2 ADC2CHSELB2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCHSEL __reserve0 BSHC __reserve1

BCHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

BSHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC2CHSELB3

A/D2 Conversion Channel B3 Selection Register
address_offset : 0x246 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2CHSELB3 ADC2CHSELB3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCHSEL __reserve0 BSHC __reserve1

BCHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

BSHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC2ERCA

A/D2 Co2versio2 Error Detectio2 Cha22el Setti2g Register A
address_offset : 0x248 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2ERCA ADC2ERCA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERCACH0 ERCACH1 ERCACH2 ERCACH3 ERCACH4 ERCACH5 ERCACH6 ERCACH7 ERCACH8 ERCACH9 ERCACH10 ERCACH11 ERCACH12 ERCACH13 ERCACH14 ERCACH15

ERCACH0 : Error detection setting (the channel selected by setting ANnCHSEL00).
bits : 0 - 0 (1 bit)
access : read-write

ERCACH1 : Error detection setting (the channel selected by setting ANnCHSEL01).
bits : 1 - 2 (2 bit)
access : read-write

ERCACH2 : Error detection setting (the channel selected by setting ANnCHSEL02).
bits : 2 - 4 (3 bit)
access : read-write

ERCACH3 : Error detection setting (the channel selected by setting ANnCHSEL03).
bits : 3 - 6 (4 bit)
access : read-write

ERCACH4 : Error detection setting (the channel selected by setting ANnCHSEL04).
bits : 4 - 8 (5 bit)
access : read-write

ERCACH5 : Error detection setting (the channel selected by setting ANnCHSEL05).
bits : 5 - 10 (6 bit)
access : read-write

ERCACH6 : Error detection setting (the channel selected by setting ANnCHSEL06).
bits : 6 - 12 (7 bit)
access : read-write

ERCACH7 : Error detection setting (the channel selected by setting ANnCHSEL07).
bits : 7 - 14 (8 bit)
access : read-write

ERCACH8 : Error detection setting (the channel selected by setting ANnCHSEL08).
bits : 8 - 16 (9 bit)
access : read-write

ERCACH9 : Error detection setting (the channel selected by setting ANnCHSEL09).
bits : 9 - 18 (10 bit)
access : read-write

ERCACH10 : Error detection setting (the channel selected by setting ANnCHSEL10).
bits : 10 - 20 (11 bit)
access : read-write

ERCACH11 : Error detection setting (the channel selected by setting ANnCHSEL11).
bits : 11 - 22 (12 bit)
access : read-write

ERCACH12 : Error detection setting (the channel selected by setting ANnCHSEL12).
bits : 12 - 24 (13 bit)
access : read-write

ERCACH13 : Error detection setting (the channel selected by setting ANnCHSEL13).
bits : 13 - 26 (14 bit)
access : read-write

ERCACH14 : Error detection setting (the channel selected by setting ANnCHSEL14).
bits : 14 - 28 (15 bit)
access : read-write

ERCACH15 : Error detection setting (the channel selected by setting ANnCHSEL15).
bits : 15 - 30 (16 bit)
access : read-write


ADC2ERCB

A/D2 Co2versio2 Error Detectio2 Cha22el Setti2g Register B
address_offset : 0x24C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2ERCB ADC2ERCB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERCBCH0 ERCBCH1 ERCBCH2 ERCBCH3 __reserve0

ERCBCH0 : Error detection setting (the channel selected by setting ANnCHSELB0).
bits : 0 - 0 (1 bit)
access : read-write

ERCBCH1 : Error detection setting (the channel selected by setting ANnCHSELB1).
bits : 1 - 2 (2 bit)
access : read-write

ERCBCH2 : Error detection setting (the channel selected by setting ANnCHSELB2).
bits : 2 - 4 (3 bit)
access : read-write

ERCBCH3 : Error detection setting (the channel selected by setting ANnCHSELB3).
bits : 3 - 6 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read


ADC2LOWA

A/D2 Co2versio2 Error Detectio2 Lower Limit Setti2g Register A
address_offset : 0x250 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2LOWA ADC2LOWA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOWA __reserve0

LOWA : Set the lower limit of A/Dn conversion result (trigger A)
bits : 0 - 11 (12 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC2UPA

A/D2 Co2versio2 Error Detectio2 Upper Limit Setti2g Register A
address_offset : 0x254 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2UPA ADC2UPA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPA __reserve0

UPA : Set the upper limit of A/Dn conversion result (trigger A)
bits : 0 - 11 (12 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC2LOWB

A/D2 Co2versio2 Error Detectio2 Lower Limit Setti2g Register B
address_offset : 0x258 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2LOWB ADC2LOWB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOWB __reserve0

LOWB : Set the lower limit of A/Dn conversion result (trigger B)
bits : 0 - 11 (12 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC2UPB

A/D2 Co2versio2 Error Detectio2 Upper Limit Setti2g Register B
address_offset : 0x25C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2UPB ADC2UPB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPB __reserve0

UPB : Set the upper limit of A/Dn conversion result (trigger B)
bits : 0 - 11 (12 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0CHSEL03

A/D0 Conversion Channel 03 Selection Register
address_offset : 0x26 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0CHSEL03 ADC0CHSEL03 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC2BUF00

A/D2 Conversion Data Buffer 00 Register
address_offset : 0x260 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2BUF00 ADC2BUF00 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC2CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC2BUF01

A/D2 Conversion Data Buffer 01 Register
address_offset : 0x264 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2BUF01 ADC2BUF01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC2CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC2BUF02

A/D2 Conversion Data Buffer 02 Register
address_offset : 0x268 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2BUF02 ADC2BUF02 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC2CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC2BUF03

A/D2 Conversion Data Buffer 03 Register
address_offset : 0x26C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2BUF03 ADC2BUF03 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC2CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC2BUF04

A/D2 Conversion Data Buffer 04 Register
address_offset : 0x270 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2BUF04 ADC2BUF04 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC2CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC2BUF05

A/D2 Conversion Data Buffer 05 Register
address_offset : 0x274 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2BUF05 ADC2BUF05 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC2CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC2BUF06

A/D2 Conversion Data Buffer 06 Register
address_offset : 0x278 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2BUF06 ADC2BUF06 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC2CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC2BUF07

A/D2 Conversion Data Buffer 07 Register
address_offset : 0x27C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2BUF07 ADC2BUF07 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC2CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0CHSEL04

A/D0 Conversion Channel 04 Selection Register
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0CHSEL04 ADC0CHSEL04 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC2BUF08

A/D2 Conversion Data Buffer 08 Register
address_offset : 0x280 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2BUF08 ADC2BUF08 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC2CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC2BUF09

A/D2 Conversion Data Buffer 09 Register
address_offset : 0x284 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2BUF09 ADC2BUF09 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC2CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC2BUF10

A/D2 Conversion Data Buffer 10 Register
address_offset : 0x288 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2BUF10 ADC2BUF10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC2CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC2BUF11

A/D2 Conversion Data Buffer 11 Register
address_offset : 0x28C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2BUF11 ADC2BUF11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC2CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC2BUF12

A/D2 Conversion Data Buffer 12 Register
address_offset : 0x290 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2BUF12 ADC2BUF12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC2CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC2BUF13

A/D2 Conversion Data Buffer 13 Register
address_offset : 0x294 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2BUF13 ADC2BUF13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC2CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC2BUF14

A/D2 Conversion Data Buffer 14 Register
address_offset : 0x298 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2BUF14 ADC2BUF14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC2CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC2BUF15

A/D2 Conversion Data Buffer 15 Register
address_offset : 0x29C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2BUF15 ADC2BUF15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC2CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0CHSEL05

A/D0 Conversion Channel 05 Selection Register
address_offset : 0x2A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0CHSEL05 ADC0CHSEL05 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC2BUFB0

A/D2 Conversion Data Buffer B0 Register
address_offset : 0x2A0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2BUFB0 ADC2BUFB0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFB __reserve0

BUFB : A/D conversion results of the channel selected by setting ADC2CHSELBm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC2BUFB1

A/D2 Conversion Data Buffer B1 Register
address_offset : 0x2A4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2BUFB1 ADC2BUFB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFB __reserve0

BUFB : A/D conversion results of the channel selected by setting ADC2CHSELBm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC2BUFB2

A/D2 Conversion Data Buffer B2 Register
address_offset : 0x2A8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2BUFB2 ADC2BUFB2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFB __reserve0

BUFB : A/D conversion results of the channel selected by setting ADC2CHSELBm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC2BUFB3

A/D2 Conversion Data Buffer B3 Register
address_offset : 0x2AC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC2BUFB3 ADC2BUFB3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFB __reserve0

BUFB : A/D conversion results of the channel selected by setting ADC2CHSELBm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC2CHECK

A/D2 Fault Check Co2trol Register
address_offset : 0x2B0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

ADC2CHECK ADC2CHECK read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHKEN CHKSEL __reserve0

CHKEN : Fault diagnosis function select
bits : 0 - 0 (1 bit)
access : read-write

CHKSEL : Conversion Potential select
bits : 1 - 3 (3 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 3 - 10 (8 bit)
access : read


ADC0CHSEL06

A/D0 Conversion Channel 06 Selection Register
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0CHSEL06 ADC0CHSEL06 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC0CHSEL07

A/D0 Conversion Channel 07 Selection Register
address_offset : 0x2E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0CHSEL07 ADC0CHSEL07 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC0CHSEL08

A/D0 Conversion Channel 08 Selection Register
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0CHSEL08 ADC0CHSEL08 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC0CHSEL09

A/D0 Conversion Channel 09 Selection Register
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0CHSEL09 ADC0CHSEL09 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC0CHSEL10

A/D0 Conversion Channel 10 Selection Register
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0CHSEL10 ADC0CHSEL10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC0CHSEL11

A/D0 Conversion Channel 11 Selection Register
address_offset : 0x36 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0CHSEL11 ADC0CHSEL11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC0CHSEL12

A/D0 Conversion Channel 12 Selection Register
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0CHSEL12 ADC0CHSEL12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC0CHSEL13

A/D0 Conversion Channel 13 Selection Register
address_offset : 0x3A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0CHSEL13 ADC0CHSEL13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC0CHSEL14

A/D0 Conversion Channel 14 Selection Register
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0CHSEL14 ADC0CHSEL14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC0CHSEL15

A/D0 Conversion Channel 15 Selection Register
address_offset : 0x3E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0CHSEL15 ADC0CHSEL15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACHSEL __reserve0 ASHC __reserve1

ACHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

ASHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC0CTR1A

A/D0 Co0versio0 Co0trol Register 1A
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0CTR1A ADC0CTR1A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AEN ATRG AMD __reserve0 AECH __reserve1

AEN : A/D conversion start
bits : 0 - 0 (1 bit)
access : read-write

ATRG : A/D conversion start by using trigger A
bits : 1 - 2 (2 bit)
access : read-write

AMD : A/D conversion mode select
bits : 2 - 4 (3 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 3 - 6 (4 bit)
access : read

AECH : Conversion end channel setting
bits : 4 - 11 (8 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 8 - 23 (16 bit)
access : read


ADC0CHSELB0

A/D0 Conversion Channel B0 Selection Register
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0CHSELB0 ADC0CHSELB0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCHSEL __reserve0 BSHC __reserve1

BCHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

BSHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC0CHSELB1

A/D0 Conversion Channel B1 Selection Register
address_offset : 0x42 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0CHSELB1 ADC0CHSELB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCHSEL __reserve0 BSHC __reserve1

BCHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

BSHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC0CHSELB2

A/D0 Conversion Channel B2 Selection Register
address_offset : 0x44 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0CHSELB2 ADC0CHSELB2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCHSEL __reserve0 BSHC __reserve1

BCHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

BSHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC0CHSELB3

A/D0 Conversion Channel B3 Selection Register
address_offset : 0x46 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0CHSELB3 ADC0CHSELB3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCHSEL __reserve0 BSHC __reserve1

BCHSEL : Conversion channel select
bits : 0 - 3 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 11 (8 bit)
access : read

BSHC : Sampling/Hold cycles
bits : 8 - 21 (14 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 14 - 29 (16 bit)
access : read


ADC0ERCA

A/D0 Co0versio0 Error Detectio0 Cha00el Setti0g Register A
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0ERCA ADC0ERCA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERCACH0 ERCACH1 ERCACH2 ERCACH3 ERCACH4 ERCACH5 ERCACH6 ERCACH7 ERCACH8 ERCACH9 ERCACH10 ERCACH11 ERCACH12 ERCACH13 ERCACH14 ERCACH15

ERCACH0 : Error detection setting (the channel selected by setting ANnCHSEL00).
bits : 0 - 0 (1 bit)
access : read-write

ERCACH1 : Error detection setting (the channel selected by setting ANnCHSEL01).
bits : 1 - 2 (2 bit)
access : read-write

ERCACH2 : Error detection setting (the channel selected by setting ANnCHSEL02).
bits : 2 - 4 (3 bit)
access : read-write

ERCACH3 : Error detection setting (the channel selected by setting ANnCHSEL03).
bits : 3 - 6 (4 bit)
access : read-write

ERCACH4 : Error detection setting (the channel selected by setting ANnCHSEL04).
bits : 4 - 8 (5 bit)
access : read-write

ERCACH5 : Error detection setting (the channel selected by setting ANnCHSEL05).
bits : 5 - 10 (6 bit)
access : read-write

ERCACH6 : Error detection setting (the channel selected by setting ANnCHSEL06).
bits : 6 - 12 (7 bit)
access : read-write

ERCACH7 : Error detection setting (the channel selected by setting ANnCHSEL07).
bits : 7 - 14 (8 bit)
access : read-write

ERCACH8 : Error detection setting (the channel selected by setting ANnCHSEL08).
bits : 8 - 16 (9 bit)
access : read-write

ERCACH9 : Error detection setting (the channel selected by setting ANnCHSEL09).
bits : 9 - 18 (10 bit)
access : read-write

ERCACH10 : Error detection setting (the channel selected by setting ANnCHSEL10).
bits : 10 - 20 (11 bit)
access : read-write

ERCACH11 : Error detection setting (the channel selected by setting ANnCHSEL11).
bits : 11 - 22 (12 bit)
access : read-write

ERCACH12 : Error detection setting (the channel selected by setting ANnCHSEL12).
bits : 12 - 24 (13 bit)
access : read-write

ERCACH13 : Error detection setting (the channel selected by setting ANnCHSEL13).
bits : 13 - 26 (14 bit)
access : read-write

ERCACH14 : Error detection setting (the channel selected by setting ANnCHSEL14).
bits : 14 - 28 (15 bit)
access : read-write

ERCACH15 : Error detection setting (the channel selected by setting ANnCHSEL15).
bits : 15 - 30 (16 bit)
access : read-write


ADC0ERCB

A/D0 Co0versio0 Error Detectio0 Cha00el Setti0g Register B
address_offset : 0x4C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0ERCB ADC0ERCB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERCBCH0 ERCBCH1 ERCBCH2 ERCBCH3 __reserve0

ERCBCH0 : Error detection setting (the channel selected by setting ANnCHSELB0).
bits : 0 - 0 (1 bit)
access : read-write

ERCBCH1 : Error detection setting (the channel selected by setting ANnCHSELB1).
bits : 1 - 2 (2 bit)
access : read-write

ERCBCH2 : Error detection setting (the channel selected by setting ANnCHSELB2).
bits : 2 - 4 (3 bit)
access : read-write

ERCBCH3 : Error detection setting (the channel selected by setting ANnCHSELB3).
bits : 3 - 6 (4 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 4 - 19 (16 bit)
access : read


ADC0LOWA

A/D0 Co0versio0 Error Detectio0 Lower Limit Setti0g Register A
address_offset : 0x50 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0LOWA ADC0LOWA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOWA __reserve0

LOWA : Set the lower limit of A/Dn conversion result (trigger A)
bits : 0 - 11 (12 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0UPA

A/D0 Co0versio0 Error Detectio0 Upper Limit Setti0g Register A
address_offset : 0x54 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0UPA ADC0UPA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPA __reserve0

UPA : Set the upper limit of A/Dn conversion result (trigger A)
bits : 0 - 11 (12 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0LOWB

A/D0 Co0versio0 Error Detectio0 Lower Limit Setti0g Register B
address_offset : 0x58 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0LOWB ADC0LOWB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOWB __reserve0

LOWB : Set the lower limit of A/Dn conversion result (trigger B)
bits : 0 - 11 (12 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0UPB

A/D0 Co0versio0 Error Detectio0 Upper Limit Setti0g Register B
address_offset : 0x5C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0UPB ADC0UPB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPB __reserve0

UPB : Set the upper limit of A/Dn conversion result (trigger B)
bits : 0 - 11 (12 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0BUF00

A/D0 Conversion Data Buffer 00 Register
address_offset : 0x60 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0BUF00 ADC0BUF00 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC0CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0BUF01

A/D0 Conversion Data Buffer 01 Register
address_offset : 0x64 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0BUF01 ADC0BUF01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC0CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0BUF02

A/D0 Conversion Data Buffer 02 Register
address_offset : 0x68 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0BUF02 ADC0BUF02 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC0CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0BUF03

A/D0 Conversion Data Buffer 03 Register
address_offset : 0x6C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0BUF03 ADC0BUF03 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC0CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0BUF04

A/D0 Conversion Data Buffer 04 Register
address_offset : 0x70 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0BUF04 ADC0BUF04 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC0CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0BUF05

A/D0 Conversion Data Buffer 05 Register
address_offset : 0x74 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0BUF05 ADC0BUF05 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC0CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0BUF06

A/D0 Conversion Data Buffer 06 Register
address_offset : 0x78 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0BUF06 ADC0BUF06 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC0CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0BUF07

A/D0 Conversion Data Buffer 07 Register
address_offset : 0x7C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0BUF07 ADC0BUF07 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC0CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0CTR1B

A/D0 Co0versio0 Co0trol Register 1B
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0CTR1B ADC0CTR1B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BEN BTRG BMD __reserve0 BECH __reserve1

BEN : A/D conversion start
bits : 0 - 0 (1 bit)
access : read-write

BTRG : A/D conversion start by using trigger B
bits : 1 - 2 (2 bit)
access : read-write

BMD : A/D conversion mode select
bits : 2 - 4 (3 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 3 - 6 (4 bit)
access : read

BECH : Conversion end channel setting
bits : 4 - 9 (6 bit)
access : read-write

__reserve1 : 0 is always read out.
bits : 6 - 21 (16 bit)
access : read


ADC0BUF08

A/D0 Conversion Data Buffer 08 Register
address_offset : 0x80 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0BUF08 ADC0BUF08 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC0CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0BUF09

A/D0 Conversion Data Buffer 09 Register
address_offset : 0x84 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0BUF09 ADC0BUF09 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC0CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0BUF10

A/D0 Conversion Data Buffer 10 Register
address_offset : 0x88 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0BUF10 ADC0BUF10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC0CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0BUF11

A/D0 Conversion Data Buffer 11 Register
address_offset : 0x8C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0BUF11 ADC0BUF11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC0CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0BUF12

A/D0 Conversion Data Buffer 12 Register
address_offset : 0x90 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0BUF12 ADC0BUF12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC0CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0BUF13

A/D0 Conversion Data Buffer 13 Register
address_offset : 0x94 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0BUF13 ADC0BUF13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC0CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0BUF14

A/D0 Conversion Data Buffer 14 Register
address_offset : 0x98 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0BUF14 ADC0BUF14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC0CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0BUF15

A/D0 Conversion Data Buffer 15 Register
address_offset : 0x9C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0BUF15 ADC0BUF15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF __reserve0

BUF : A/D conversion results of the channel selected by setting ADC0CHSELm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0BUFB0

A/D0 Conversion Data Buffer B0 Register
address_offset : 0xA0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0BUFB0 ADC0BUFB0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFB __reserve0

BUFB : A/D conversion results of the channel selected by setting ADC0CHSELBm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0BUFB1

A/D0 Conversion Data Buffer B1 Register
address_offset : 0xA4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0BUFB1 ADC0BUFB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFB __reserve0

BUFB : A/D conversion results of the channel selected by setting ADC0CHSELBm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0BUFB2

A/D0 Conversion Data Buffer B2 Register
address_offset : 0xA8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0BUFB2 ADC0BUFB2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFB __reserve0

BUFB : A/D conversion results of the channel selected by setting ADC0CHSELBm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0BUFB3

A/D0 Conversion Data Buffer B3 Register
address_offset : 0xAC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0

ADC0BUFB3 ADC0BUFB3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFB __reserve0

BUFB : A/D conversion results of the channel selected by setting ADC0CHSELBm.
bits : 0 - 11 (12 bit)
access : read

__reserve0 : 0 is always read out.
bits : 12 - 27 (16 bit)
access : read


ADC0CHECK

A/D0 Fault Check Co0trol Register
address_offset : 0xB0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0

ADC0CHECK ADC0CHECK read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHKEN CHKSEL __reserve0

CHKEN : Fault diagnosis function select
bits : 0 - 0 (1 bit)
access : read-write

CHKSEL : Conversion Potential select
bits : 1 - 3 (3 bit)
access : read-write

__reserve0 : 0 is always read out.
bits : 3 - 10 (8 bit)
access : read



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