\n
address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection :
SMBus Receptio1 Data Buffer
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
RXBUF : Reception data is read out.
bits : 0 - 7 (8 bit)
access : read
SMBus Status Register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
RWS_SLV : Read/ Write mode determination at Slave communication
bits : 0 - 0 (1 bit)
access : read
ADROK : Slave address matching detection (*1)
bits : 1 - 2 (2 bit)
access : read-write
NACK : NACK detection (*1)
bits : 2 - 4 (3 bit)
access : read-write
TRANS_BUSY : Communication busy state detection
bits : 3 - 6 (4 bit)
access : read
BUS_BUSY : Bus busy state detection
bits : 4 - 8 (5 bit)
access : read
ABT_LST : Arbitration lost detection (*1)
bits : 5 - 10 (6 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 6 - 13 (8 bit)
access : read
SMBus I1terrupt Co1trol Register
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
ACKDONE_IE : Enable ACK communication completion interrupt factor
bits : 0 - 0 (1 bit)
access : read-write
BYTEDONE_IE : Enable Byte data communication completion interrupt factor (*1)
bits : 1 - 2 (2 bit)
access : read-write
STOP_IE : Enable Stop condition interrupt factor
bits : 2 - 4 (3 bit)
access : read-write
START_IE : Enable Start condition detection interrupt factor
bits : 3 - 6 (4 bit)
access : read-write
ADRNG_IE : Enable Slave address mismatch interrupt factor
bits : 4 - 8 (5 bit)
access : read-write
TOUT_IE : Enable Time-out interrupt factor
bits : 5 - 10 (6 bit)
access : read-write
WKUP_IE : Enable WAKEUP interrupt factor
bits : 6 - 12 (7 bit)
access : read-write
__reserve0 : This bit must be set to 0 .
bits : 7 - 14 (8 bit)
access : read-write
SMBus I1terrupt Status Register
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
ACKDONE : ACK communication completion detection (*1)
bits : 0 - 0 (1 bit)
access : read-write
BYTEDONE : Byte data communication completion detection (*1)
bits : 1 - 2 (2 bit)
access : read-write
STOP : Stop condition detection (*1)
bits : 2 - 4 (3 bit)
access : read-write
START : Start condition detection (*1)
bits : 3 - 6 (4 bit)
access : read-write
ADRNG : Slave address mismatch detection (*1)
bits : 4 - 8 (5 bit)
access : read-write
TOUT : SMBus Time-out detection
bits : 5 - 11 (7 bit)
access : read
LPW : SMBus stop detection
bits : 7 - 14 (8 bit)
access : read
SMBus Tra1sfer Clock Setti1g Register
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
SCL_SET : Refer to [Clock Specification, Chapter SMBus Interface] of LSI User's manual for the setting value of this register and the setting of transfer clock frequency.
bits : 0 - 12 (13 bit)
access : read-write
__reserve0 : 0 is always read out
bits : 13 - 28 (16 bit)
access : read
SMBus Slave Address Setti1g Register
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read
SLV_ADR : Set the slave address.
bits : 1 - 8 (8 bit)
access : read-write
SMBus Packet Error Code Storage Register
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
PEC : The calculation result of packet error code is read out.
bits : 0 - 7 (8 bit)
access : read
SMBus Tra1smissio1 Data Buffer
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
TXBUF : Set the transmission data.
bits : 0 - 7 (8 bit)
access : read-write
SMBus Co1trol Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
PEC_CLR : Clear the packet error code(*3)
bits : 0 - 0 (1 bit)
access : read-write
PEC_ON : Packet error check calculation control (*3)
bits : 1 - 2 (2 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 2 - 7 (6 bit)
access : read
__reserve1 : This bit must be set to 0 . (*1)
bits : 6 - 12 (7 bit)
access : read-write
__reserve2 : This bit must be set to 1 when SMBus interface using. (*1)
bits : 7 - 14 (8 bit)
access : read-write
EXT_ON : TLOW:MEXT / TLOW:SEXT detection enable (*1)
bits : 8 - 16 (9 bit)
access : read-write
TOUT_ON : Clock Low-level period (TTIMEOUT) detection enable (*1)
bits : 9 - 18 (10 bit)
access : read-write
SCLH_SEL : Clock High-level period detection time (*1)
bits : 10 - 21 (12 bit)
access : read-write
SCLH_ON : Clock High-level period (THIGH) detection enable (*1)
bits : 12 - 24 (13 bit)
access : read-write
LPW_LMTSEL : SMBus stop detection period (*1)
bits : 13 - 26 (14 bit)
access : read-write
LPW_ON : SMBus stop detection enable (*1)
bits : 14 - 28 (15 bit)
access : read-write
__reserve3 : This bit must be set to 0 . (*1)
bits : 15 - 30 (16 bit)
access : read-write
ACKOK : ACK communication completion setting (*2)
bits : 16 - 32 (17 bit)
access : read-write
BYTEOK : Byte data communication completion setting (*2)
bits : 17 - 34 (18 bit)
access : read-write
TRANS_END : Communication end setting
bits : 18 - 36 (19 bit)
access : read-write
ACK_SET : Transmission ACK bit selection
bits : 19 - 38 (20 bit)
access : read-write
RWS_MST : Read/Write mode selection at Master
bits : 20 - 40 (21 bit)
access : read-write
STOP_EN : Stop condition selection
bits : 21 - 42 (22 bit)
access : read-write
START_EN : Start condition selection
bits : 22 - 44 (23 bit)
access : read-write
MST : Master/Slave selection (*1)
bits : 23 - 46 (24 bit)
access : read-write
__reserve4 : 0 is always read out.
bits : 24 - 55 (32 bit)
access : read
SMBus Reset Register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
BRST : SMBus block reset control
bits : 0 - 0 (1 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 1 - 6 (6 bit)
access : read
__reserve1 : -
bits : 6 - 12 (7 bit)
access : read
__reserve2 : -
bits : 7 - 14 (8 bit)
access : read
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