\n
address_offset : 0x0 Bytes (0x0)
size : 0x1F0C byte (0x0)
mem_usage : registers
protection :
DMA0 Source Address Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write
DMA0 Executio0 Desti0atio0 Address Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write
DMA4 Source Address Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write
DMA8 Source Address Register
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write
DMA8 Desti8atio8 Address Register
address_offset : 0x1004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write
DMA8 Tra8sfer Word Cou8t Register
address_offset : 0x1008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA8 Executio8 Source Address Register
address_offset : 0x100C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write
DMA8 Executio8 Desti8atio8 Address Register
address_offset : 0x1010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write
Executio8 Tra8sfer Word Cou8t Register
address_offset : 0x1014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA8 Reload Cou8ter
address_offset : 0x1018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read
SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write
DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write
DMA Co8trol Register
address_offset : 0x101C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read
SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write
SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read
DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write
__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read
DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write
DMA8 Software Request Register
address_offset : 0x1020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write
__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read
DMA Status Read Register
address_offset : 0x1024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read
REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read
OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read
SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read
__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA Status Clear Register
address_offset : 0x1028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read
REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write
OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write
SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write
__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA4 Desti4atio4 Address Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write
DMA9 Source Address Register
address_offset : 0x1040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write
DMA9 Desti9atio9 Address Register
address_offset : 0x1044 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write
DMA9 Tra9sfer Word Cou9t Register
address_offset : 0x1048 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA9 Executio9 Source Address Register
address_offset : 0x104C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write
DMA9 Executio9 Desti9atio9 Address Register
address_offset : 0x1050 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write
Executio9 Tra9sfer Word Cou9t Register
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA9 Reload Cou9ter
address_offset : 0x1058 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read
SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write
DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write
DMA Co9trol Register
address_offset : 0x105C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read
SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write
SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read
DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write
__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read
DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write
DMA9 Software Request Register
address_offset : 0x1060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write
__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read
DMA Status Read Register
address_offset : 0x1064 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read
REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read
OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read
SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read
__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA Status Clear Register
address_offset : 0x1068 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read
REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write
OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write
SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write
__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA4 Tra4sfer Word Cou4t Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA10 Source Address Register
address_offset : 0x1080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write
DMA10 Desti10atio10 Address Register
address_offset : 0x1084 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write
DMA10 Tra10sfer Word Cou10t Register
address_offset : 0x1088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA10 Executio10 Source Address Register
address_offset : 0x108C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write
DMA10 Executio10 Desti10atio10 Address Register
address_offset : 0x1090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write
Executio10 Tra10sfer Word Cou10t Register
address_offset : 0x1094 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA10 Reload Cou10ter
address_offset : 0x1098 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read
SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write
DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write
DMA Co10trol Register
address_offset : 0x109C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read
SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write
SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read
DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write
__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read
DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write
DMA10 Software Request Register
address_offset : 0x10A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write
__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read
DMA Status Read Register
address_offset : 0x10A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read
REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read
OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read
SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read
__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA Status Clear Register
address_offset : 0x10A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read
REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write
OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write
SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write
__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA4 Executio4 Source Address Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write
DMA11 Source Address Register
address_offset : 0x10C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write
DMA11 Desti11atio11 Address Register
address_offset : 0x10C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write
DMA11 Tra11sfer Word Cou11t Register
address_offset : 0x10C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA11 Executio11 Source Address Register
address_offset : 0x10CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write
DMA11 Executio11 Desti11atio11 Address Register
address_offset : 0x10D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write
Executio11 Tra11sfer Word Cou11t Register
address_offset : 0x10D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA11 Reload Cou11ter
address_offset : 0x10D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read
SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write
DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write
DMA Co11trol Register
address_offset : 0x10DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read
SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write
SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read
DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write
__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read
DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write
DMA11 Software Request Register
address_offset : 0x10E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write
__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read
DMA Status Read Register
address_offset : 0x10E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read
REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read
OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read
SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read
__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA Status Clear Register
address_offset : 0x10E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read
REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write
OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write
SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write
__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA4 Executio4 Desti4atio4 Address Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write
DMA12 Source Address Register
address_offset : 0x1100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write
DMA12 Desti12atio12 Address Register
address_offset : 0x1104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write
DMA12 Tra12sfer Word Cou12t Register
address_offset : 0x1108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA12 Executio12 Source Address Register
address_offset : 0x110C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write
DMA12 Executio12 Desti12atio12 Address Register
address_offset : 0x1110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write
Executio12 Tra12sfer Word Cou12t Register
address_offset : 0x1114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA12 Reload Cou12ter
address_offset : 0x1118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read
SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write
DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write
DMA Co12trol Register
address_offset : 0x111C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read
SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write
SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read
DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write
__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read
DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write
DMA12 Software Request Register
address_offset : 0x1120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write
__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read
DMA Status Read Register
address_offset : 0x1124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read
REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read
OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read
SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read
__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA Status Clear Register
address_offset : 0x1128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read
REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write
OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write
SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write
__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
Executio4 Tra4sfer Word Cou4t Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA13 Source Address Register
address_offset : 0x1140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write
DMA13 Desti13atio13 Address Register
address_offset : 0x1144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write
DMA13 Tra13sfer Word Cou13t Register
address_offset : 0x1148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA13 Executio13 Source Address Register
address_offset : 0x114C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write
DMA13 Executio13 Desti13atio13 Address Register
address_offset : 0x1150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write
Executio13 Tra13sfer Word Cou13t Register
address_offset : 0x1154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA13 Reload Cou13ter
address_offset : 0x1158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read
SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write
DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write
DMA Co13trol Register
address_offset : 0x115C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read
SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write
SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read
DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write
__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read
DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write
DMA13 Software Request Register
address_offset : 0x1160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write
__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read
DMA Status Read Register
address_offset : 0x1164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read
REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read
OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read
SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read
__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA Status Clear Register
address_offset : 0x1168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read
REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write
OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write
SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write
__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA4 Reload Cou4ter
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read
SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write
DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write
DMA14 Source Address Register
address_offset : 0x1180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write
DMA14 Desti14atio14 Address Register
address_offset : 0x1184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write
DMA14 Tra14sfer Word Cou14t Register
address_offset : 0x1188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA14 Executio14 Source Address Register
address_offset : 0x118C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write
DMA14 Executio14 Desti14atio14 Address Register
address_offset : 0x1190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write
Executio14 Tra14sfer Word Cou14t Register
address_offset : 0x1194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA14 Reload Cou14ter
address_offset : 0x1198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read
SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write
DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write
DMA Co14trol Register
address_offset : 0x119C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read
SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write
SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read
DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write
__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read
DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write
DMA14 Software Request Register
address_offset : 0x11A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write
__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read
DMA Status Read Register
address_offset : 0x11A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read
REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read
OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read
SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read
__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA Status Clear Register
address_offset : 0x11A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read
REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write
OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write
SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write
__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA Co4trol Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read
SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write
SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read
DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write
__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read
DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write
DMA15 Source Address Register
address_offset : 0x11C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write
DMA15 Desti15atio15 Address Register
address_offset : 0x11C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write
DMA15 Tra15sfer Word Cou15t Register
address_offset : 0x11C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA15 Executio15 Source Address Register
address_offset : 0x11CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write
DMA15 Executio15 Desti15atio15 Address Register
address_offset : 0x11D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write
Executio15 Tra15sfer Word Cou15t Register
address_offset : 0x11D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA15 Reload Cou15ter
address_offset : 0x11D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read
SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write
DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write
DMA Co15trol Register
address_offset : 0x11DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read
SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write
SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read
DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write
__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read
DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write
DMA15 Software Request Register
address_offset : 0x11E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write
__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read
DMA Status Read Register
address_offset : 0x11E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read
REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read
OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read
SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read
__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA Status Clear Register
address_offset : 0x11E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read
REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write
OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write
SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write
__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA4 Software Request Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write
__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read
DMA Status Read Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read
REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read
OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read
SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read
__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA Status Clear Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read
REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write
OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write
SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write
__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
Executio0 Tra0sfer Word Cou0t Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA5 Source Address Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write
DMA5 Desti5atio5 Address Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write
DMA5 Tra5sfer Word Cou5t Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA5 Executio5 Source Address Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write
DMA5 Executio5 Desti5atio5 Address Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write
Executio5 Tra5sfer Word Cou5t Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA5 Reload Cou5ter
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read
SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write
DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write
DMA Co5trol Register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read
SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write
SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read
DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write
__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read
DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write
DMA5 Software Request Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write
__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read
DMA Status Read Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read
REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read
OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read
SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read
__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA Status Clear Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read
REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write
OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write
SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write
__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA0 Reload Cou0ter
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read
SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write
DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write
DMA6 Source Address Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write
DMA6 Desti6atio6 Address Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write
DMA6 Tra6sfer Word Cou6t Register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA6 Executio6 Source Address Register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write
DMA6 Executio6 Desti6atio6 Address Register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write
Executio6 Tra6sfer Word Cou6t Register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA6 Reload Cou6ter
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read
SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write
DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write
DMA Co6trol Register
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read
SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write
SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read
DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write
__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read
DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write
DMA6 Software Request Register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write
__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read
DMA Status Read Register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read
REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read
OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read
SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read
__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA Status Clear Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read
REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write
OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write
SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write
__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA Co0trol Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read
SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write
SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read
DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write
__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read
DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write
DMA7 Source Address Register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write
DMA7 Desti7atio7 Address Register
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write
DMA7 Tra7sfer Word Cou7t Register
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA7 Executio7 Source Address Register
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write
DMA7 Executio7 Desti7atio7 Address Register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write
Executio7 Tra7sfer Word Cou7t Register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA7 Reload Cou7ter
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read
SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write
DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write
DMA Co7trol Register
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read
SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write
SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read
DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write
__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read
DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write
DMA7 Software Request Register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write
__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read
DMA Status Read Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read
REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read
OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read
SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read
__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA Status Clear Register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read
REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write
OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write
SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write
__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA1NMI Status Read Register
address_offset : 0x1F00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
NMI : NMI detection bit (module m)
bits : 0 - 0 (1 bit)
access : read
__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read
DMA1NMI Status Clear Register
address_offset : 0x1F04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
NMIW : Clear the NMI detection bit (module m)
bits : 0 - 0 (1 bit)
access : write
__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read
DMA1NMI Enable Register
address_offset : 0x1F08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
NMIEN : DMA transfer discontinuity (module m) when NMI is detected
bits : 0 - 0 (1 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read
DMA0 Software Request Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write
__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read
DMA Status Read Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read
REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read
OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read
SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read
__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA Status Clear Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read
REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write
OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write
SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write
__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA0 Desti0atio0 Address Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write
DMA1 Source Address Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write
DMA1 Desti1atio1 Address Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write
DMA1 Tra1sfer Word Cou1t Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA1 Executio1 Source Address Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write
DMA1 Executio1 Desti1atio1 Address Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write
Executio1 Tra1sfer Word Cou1t Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA1 Reload Cou1ter
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read
SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write
DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write
DMA Co1trol Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read
SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write
SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read
DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write
__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read
DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write
DMA1 Software Request Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write
__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read
DMA Status Read Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read
REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read
OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read
SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read
__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA Status Clear Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read
REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write
OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write
SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write
__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA0 Tra0sfer Word Cou0t Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA2 Source Address Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write
DMA2 Desti2atio2 Address Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write
DMA2 Tra2sfer Word Cou2t Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA2 Executio2 Source Address Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write
DMA2 Executio2 Desti2atio2 Address Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write
Executio2 Tra2sfer Word Cou2t Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA2 Reload Cou2ter
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read
SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write
DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write
DMA Co2trol Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read
SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write
SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read
DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write
__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read
DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write
DMA2 Software Request Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write
__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read
DMA Status Read Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read
REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read
OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read
SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read
__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA Status Clear Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read
REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write
OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write
SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write
__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA0 Executio0 Source Address Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write
DMA3 Source Address Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRC : DMA transfer source address
bits : 0 - 31 (32 bit)
access : read-write
DMA3 Desti3atio3 Address Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DST : DMA transfer destination address
bits : 0 - 31 (32 bit)
access : read-write
DMA3 Tra3sfer Word Cou3t Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CNT : DMA transfer word count
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA3 Executio3 Source Address Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXSRC : During DMA transfer, the transfer source address is held.
bits : 0 - 31 (32 bit)
access : read-write
DMA3 Executio3 Desti3atio3 Address Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXDST : During DMA transfer, the transfer destination address is held.
bits : 0 - 31 (32 bit)
access : read-write
Executio3 Tra3sfer Word Cou3t Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EXCNT : During DMA transfer, the DMA transfer word count is held.
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 47 (32 bit)
access : read
DMA3 Reload Cou3ter
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RLDCNT : The number of times of reloading
bits : 0 - 15 (16 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 16 - 45 (30 bit)
access : read
SRCRLD : Load enable(during reload operation)
bits : 30 - 60 (31 bit)
access : read-write
DSTRLD : Load enable(during reload operation)
bits : 31 - 62 (32 bit)
access : read-write
DMA Co3trol Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FACTOR : DMA transfer request
bits : 0 - 6 (7 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 7 - 30 (24 bit)
access : read
SIZE : DMA transfer unit
bits : 24 - 49 (26 bit)
access : read-write
SRCMD : DMA transfer addressing mode on source address
bits : 26 - 52 (27 bit)
access : read-write
__reserve1 : 0 is always read out.
bits : 27 - 54 (28 bit)
access : read
DSTMD : DMA transfer addressing mode on destination address
bits : 28 - 56 (29 bit)
access : read-write
__reserve2 : 0 is always read out.
bits : 29 - 59 (31 bit)
access : read
DMAEN : DMA transfer enable
bits : 31 - 62 (32 bit)
access : read-write
DMA3 Software Request Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SFTRQ : DMA request by software
bits : 0 - 0 (1 bit)
access : write
__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read
DMA Status Read Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DMAREQ : DMA transfer status
bits : 0 - 0 (1 bit)
access : read
REQERR : Disabled DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : read
OVFERR : DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : read
SYSERR : System error bit
bits : 3 - 6 (4 bit)
access : read
__reserve0 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA Status Clear Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
__reserve0 : 0 is always read out.
bits : 0 - 0 (1 bit)
access : read
REQERR : Clear the DMA transfer request error bit
bits : 1 - 2 (2 bit)
access : write
OVFERR : Clear the DMA transfer request overflow bit
bits : 2 - 4 (3 bit)
access : write
SYSERR : Clear the system error bit
bits : 3 - 6 (4 bit)
access : write
__reserve1 : 0 is always read out.
bits : 4 - 35 (32 bit)
access : read
DMA0NMI Status Read Register
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
NMI : NMI detection bit (module m)
bits : 0 - 0 (1 bit)
access : read
__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read
DMA0NMI Status Clear Register
address_offset : 0xF04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
NMIW : Clear the NMI detection bit (module m)
bits : 0 - 0 (1 bit)
access : write
__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read
DMA0NMI Enable Register
address_offset : 0xF08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
NMIEN : DMA transfer discontinuity (module m) when NMI is detected
bits : 0 - 0 (1 bit)
access : read-write
__reserve0 : 0 is always read out.
bits : 1 - 32 (32 bit)
access : read
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