Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x18 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x40 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x54 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :
address_offset : 0x64 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :
address_offset : 0x74 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :
address_offset : 0xD0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xF0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x110 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x130 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x150 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x1F0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
Product Identifier Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IMG2 : Product Identifier
Data in MAP2 of information block are copied to this register after power on. MAP2 is used to store part number defined by Nuvoton.
bits : 0 - 31 (32 bit)
access : read-only
Register Lock Control Register
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYS_REGLCTL_REGLCTL : Register Lock Control Code (Write Only)
Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 59h , 16h , 88h to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
Protected Register Lock/Unlock Index (Read Only)
bits : 0 - 7 (8 bit)
access : write-only
Enumeration:
0 : 0
Protected registers are locked. Any write to the target register is ignored
1 : 1
Protected registers are unlocked
End of enumeration elements list.
Internal Oscillator Trim Register
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIM : 10 bit trim for oscillator,
bits : 0 - 9 (10 bit)
access : read-write
EN2MHZ : 1: High frequency mode (20-50 MHz)
0: Low Frequency mode of oscillator active (2 MHz).
bits : 15 - 15 (1 bit)
access : read-write
10KHz Oscillator and Bias Trim Register
address_offset : 0x114 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSC10K_TRIM : 23bit trim for 10 KHz oscillator.
bits : 0 - 22 (23 bit)
access : read-write
TM_REG : Analog test modes
bits : 24 - 27 (4 bit)
access : read-write
TRM_CLK : Must be toggled to load a new OSC10K_TRIM
bits : 31 - 31 (1 bit)
access : read-write
Oscillator Frequency Adjustment Control Register
address_offset : 0x118 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIM : 16bit sign extended representation of 10bit trim.
SYS_OSC_TRIM[n] load from factory trim value after reset.
One of SYS_OSC_TRIM[n] will map to SYS_OSCTRIM base on OSCFSEL
bits : 0 - 15 (16 bit)
access : read-write
TC : Temperature compensation setting. Set by factory
bits : 16 - 20 (5 bit)
access : read-write
EN2MHZ : 1: High frequency mode (20-50 MHz)
0: Low Frequency mode of oscillator active (2 MHz).
bits : 31 - 31 (1 bit)
access : read-write
Oscillator Frequency Adjustment Control Register
address_offset : 0x11C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Oscillator Frequency Adjustment Control Register
address_offset : 0x120 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIRC Trim Control Register
address_offset : 0x130 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQSEL : Trim Frequency Selection
This field indicates the target frequency of internal high speed RC oscillator (HIRC) auto trim.
During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Disable HIRC auto trim function
#01 : 1
Enable HIRC auto trim function and trim HIRC to 48 MHz
#10 : 2
Disable HIRC auto trim function
#11 : 3
Enable HIRC auto trim function and trim HIRC to 49.152 MHz
End of enumeration elements list.
LOOPSEL : Trim Calculation Loop Selection
This field defines that trim value calculation is based on how many internal reference clocks.
Note1: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
Note2: If source clock from HXT , the internal reference clock is 32 KHz
If source clock from SOF , the internal reference clock is 1 KHz.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Trim value calculation is based on average difference in 4 clocks of reference clock
#01 : 1
Trim value calculation is based on average difference in 8 clocks of reference clock
#10 : 2
Trim value calculation is based on average difference in 16 clocks of reference clock
#11 : 3
Trim value calculation is based on average difference in 32 clocks of reference clock
End of enumeration elements list.
RETRYCNT : Trim Value Update Limitation Count
This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.
Once the HIRC locked, the internal trim value update counter will be reset.
If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Trim retry count limitation is 64 loops
#01 : 1
Trim retry count limitation is 128 loops
#10 : 2
Trim retry count limitation is 256 loops
#11 : 3
Trim retry count limitation is 512 loops
End of enumeration elements list.
CESTOPEN : Clock Error Stop Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The trim operation is keep going if clock is inaccuracy
#1 : 1
The trim operation is stopped if clock is inaccuracy
End of enumeration elements list.
REFCKSEL : Reference Clock Selection
Note: HIRC trim reference clock is 20K Hz in test mode
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
HIRC trim reference clock is from HXT (4~24.576 MHz)
#1 : 1
HIRC trim reference clock USB SOF (Start-Of-Frame) packet
End of enumeration elements list.
IGNORE : Ignore HIRC Unstable Period Selection
Note: For the current version of HIRC, its clock frequency will shift when trim bits change from 0 to 1 or 1 to 0. To solve this problem, RC_TRIM ignore the counting clock of unstable HIRC clock period to prevent trim bit Inaccuracies.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable function of ignoring the counting cycles in HIRC unstable period
#1 : 1
Disable function of ignoring the counting cycles in HIRC unstable period
End of enumeration elements list.
HIRC Trim Interrupt Enable Register
address_offset : 0x134 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFAILIEN : Trim Failure Interrupt Enable Bit
This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL (SYS_IRCTCTL [1:0]).
If this bit is high and TFAILIF (SYS_IRCTSTS [1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable TFAILIF (SYS_IRCTSTS [1]) status to trigger an interrupt to CPU
#1 : 1
Enable TFAILIF (SYS_IRCTSTS [1]) status to trigger an interrupt to CPU
End of enumeration elements list.
CLKEIEN : Clock Error Interrupt Enable Bit
This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.
If this bit is set to1, and CLKERRIF (SYS_IRCTSTS [2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable CLKERRIF (SYS_IRCTSTS [2]) status to trigger an interrupt to CPU
#1 : 1
Enable CLKERRIF (SYS_IRCTSTS [2]) status to trigger an interrupt to CPU
End of enumeration elements list.
HIRC Trim Interrupt Status Register
address_offset : 0x138 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQLOCK : HIRC Frequency Lock Status
This bit indicates the HIRC frequency is locked.
This is a status bit and doesn't trigger any interrupt
Write 1 to clear this to 0. This bit will be set automatically, if the frequecy is lock and the RC_TRIM is enabled.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The internal high-speed oscillator frequency doesn't lock at target frequency yet
#1 : 1
The internal high-speed oscillator frequency locked at target frequency
End of enumeration elements list.
TFAILIF : Trim Failure Interrupt Status
This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL (SYS_IRCTCTL [1:0]) will be cleared to 00 by hardware automatically.
If this bit is set and TFAILIEN (SYS_IRCTIEN [1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trim value update limitation count does not reach
#1 : 1
Trim value update limitation count reached and HIRC frequency still not locked
End of enumeration elements list.
CLKERRIF : Clock Error Interrupt Status
When the frequency of external high speed crystal oscillator (HXT) or internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy
Once this bit is set to 1, the auto trim operation stopped and FREQSEL (SYS_IRCTCL [1:0]) will be cleared to 00 by hardware automatically if CESTOPEN (SYS_IRCTCTL [8]) is set to 1.
If this bit is set and CLKEIEN (SYS_IRCTIEN [2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock frequency is accuracy
#1 : 1
Clock frequency is inaccuracy
End of enumeration elements list.
HIRC Trim Clock Reference Frequency Register
address_offset : 0x13C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTFREQ : HIRC Trim reference clock frequency value when reference clock from HXT
User can insert the HXT frequency on PCB to this register for internal trim. The insert frequency value is unit KHz.
For example:
Note1: The HXT frequency register should set correct value before HIRC auto trim enable.
Note2: It recommends the HXT should be multiple of 4MHz or 4.096MHz.
bits : 0 - 14 (15 bit)
access : read-write
Bandgap Trim Control Register
address_offset : 0x140 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIM : 4 bit trim for Bandgap.
bits : 0 - 3 (4 bit)
access : read-write
TM : Bandgap test modes
Bandgap output to IO(TBD) enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
Specified ID Register for Library and Customized Feature Checking
address_offset : 0x150 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UCID : UCID Value
This register provides specific read-only information for the UCID
bits : 0 - 31 (32 bit)
access : read-only
Brown-out Detector Control Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BODEN : Brown-Out Detector Threshold Voltage Selection Extension (Initialized and Protected Bit)
The default value is set by flash controller as inverse of user configuration CBODEN bit (config0 [20]).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-Out Detector function is disabled
#1 : 1
Brown-Out Detector function enabled
End of enumeration elements list.
BODRSTEN : Brown-Out Detector Reset or Interrupt Bit (Initialized and Protected Bit)
The default value is set by flash controller as inverse of user configuration CBORST bit (config0 [21]).
When the BOD is enabled and the interrupt is asserted, the interrupt will be kept till the BOD is disabled. The interrupt for CPU can be blocked either by disabling the interrupt in the NVIC or by disabling the interrupt source by disabling the BOD. BOD can then be re-enabled as required.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-Out Detector generate an interrupt
#1 : 1
Brown-Out Detector will reset chip
End of enumeration elements list.
BODLVL : Brown-Out Detector Threshold Voltage Selection (Initialized and Protected Bit)
bits : 2 - 5 (4 bit)
access : read-write
BODHYS : Brown-Out Detector Hysteresis (Initialized and Protected Bit)
The default value is set by flash controller user configuration CBOV [4] bit (config0 [26]).
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No hysteresis on BOD detection
#1 : 1
BOD hysteresis enabled
End of enumeration elements list.
BODOUT : Brown-Out Detector Output State
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out Detector status output is 0, the detected voltage is higher than BOD_VL setting
#1 : 1
Brown-out Detector status output is 1, the detected voltage is lower than BOD_VL setting
End of enumeration elements list.
BODINT : Brown-Out Dectector Interrupt
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#1 : 1
indicates BOD_INT is active. Write 1 to clear
End of enumeration elements list.
LVREN : Low Voltage Reset (LVR) Enable (Initialized and Protected Bit)
The LVR function resets the chip when the input power voltage is lower than LVR trip point. Default value is set by flash controller as inverse of CLVR config 0[27].
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable LVR function
#1 : 1
Enable LVR function
End of enumeration elements list.
LVRFILTER : Default value is 00.
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
#00 : 0
LVR output will be filtered by 1 HCLK
#01 : 1
LVR output will be filtered by 2 HCLK
#10 : 2
LVR output will be filtered by 8 HCLK
#11 : 3
LVR output will be filtered by 15 HCLK
End of enumeration elements list.
Power-On-reset Controller Register
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POROFF : Power-on Reset Enable Bit (Write Protected)
When power is applied to device, the POR circuit generates a reset signal to reset the entire chip function. Noise on the power may cause the POR to become active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.
Note1: This bit does write protected. Refer to the SYS_REGLCTL register.
Note2: This function will not work under DPD mode.
bits : 0 - 15 (16 bit)
access : read-write
FPGA Date Register
address_offset : 0x1F0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATE : FPGA Date register
This register provides the FPGA date
bits : 0 - 31 (32 bit)
access : read-only
FPGA Version Register
address_offset : 0x1F4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : FPGA Version register
This register provides the FPGA version
bits : 0 - 31 (32 bit)
access : read-only
GPIO PA Multiple Alternate Functions and Input Type Control Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA0MFP : PA.0 Multi-function Pin Selection
bits : 0 - 1 (2 bit)
access : read-write
PA1MFP : PA.1 Multi-function Pin Selection
bits : 2 - 3 (2 bit)
access : read-write
PA2MFP : PA.2 Multi-function Pin Selection
bits : 4 - 5 (2 bit)
access : read-write
PA3MFP : PA.3 Multi-function Pin Selection
bits : 6 - 7 (2 bit)
access : read-write
PA4MFP : PA.4 Multi-function Pin Selection
bits : 8 - 9 (2 bit)
access : read-write
PA5MFP : PA.5 Multi-function Pin Selection
bits : 10 - 11 (2 bit)
access : read-write
PA6MFP : PA.6 Multi-function Pin Selection
bits : 12 - 13 (2 bit)
access : read-write
PA7MFP : PA.7 Multi-function Pin Selection
bits : 14 - 15 (2 bit)
access : read-write
PA8MFP : PA.8 Multi-function Pin Selection
bits : 16 - 17 (2 bit)
access : read-write
PA9MFP : PA.9 Multi-function Pin Selection
bits : 18 - 19 (2 bit)
access : read-write
PA10MFP : PA.10 Multi-function Pin Selection
bits : 20 - 21 (2 bit)
access : read-write
PA11MFP : PA.11 Multi-function Pin Selection
bits : 22 - 23 (2 bit)
access : read-write
PA12MFP : PA.12 Multi-function Pin Selection
bits : 24 - 25 (2 bit)
access : read-write
PA13MFP : PA.13 Multi-function Pin Selection
bits : 26 - 27 (2 bit)
access : read-write
PA14MFP : PA.14 Multi-function Pin Selection
bits : 28 - 29 (2 bit)
access : read-write
PA15MFP : PA.15 Multi-function Pin Selection
bits : 30 - 31 (2 bit)
access : read-write
GPIO PB Multiple Alternate Functions and Input Type Control Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB0MFP : PB.0 Multi-function Pin Selection
bits : 0 - 1 (2 bit)
access : read-write
PB1MFP : PB.1 Multi-function Pin Selection
bits : 2 - 3 (2 bit)
access : read-write
GPIO PC Multiple Alternate Functions and Input Type Control Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC0MFP : PC.0 Multi-function Pin Selection
bits : 0 - 1 (2 bit)
access : read-write
PC1MFP : PC.1 Multi-function Pin Selection
bits : 2 - 3 (2 bit)
access : read-write
PC2MFP : PC.2 Multi-function Pin Selection
bits : 4 - 5 (2 bit)
access : read-write
PC3MFP : PC.3 Multi-function Pin Selection
bits : 6 - 7 (2 bit)
access : read-write
PC4MFP : PC.4 Multi-function Pin Selection
bits : 8 - 9 (2 bit)
access : read-write
PC5MFP : PC.5 Multi-function Pin Selection
bits : 10 - 11 (2 bit)
access : read-write
PC6MFP : PC.6 Multi-function Pin Selection
bits : 12 - 13 (2 bit)
access : read-write
PC7MFP : PC.7 Multi-function Pin Selection
bits : 14 - 15 (2 bit)
access : read-write
PC8MFP : PC.8 Multi-function Pin Selection
bits : 16 - 17 (2 bit)
access : read-write
PC9MFP : PC.9 Multi-function Pin Selection
bits : 18 - 19 (2 bit)
access : read-write
PC10MFP : PC.10 Multi-function Pin Selection
bits : 20 - 21 (2 bit)
access : read-write
PC11MFP : PC.11 Multi-function Pin Selection
bits : 22 - 23 (2 bit)
access : read-write
PC12MFP : PC.12 Multi-function Pin Selection
bits : 24 - 25 (2 bit)
access : read-write
PC13MFP : PC.13 Multi-function Pin Selection
bits : 26 - 27 (2 bit)
access : read-write
PC14MFP : PC.14 Multi-function Pin Selection
bits : 28 - 29 (2 bit)
access : read-write
PC15MFP : PC.15 Multi-function Pin Selection
bits : 30 - 31 (2 bit)
access : read-write
GPIO PD Multiple Alternate Functions and Input Type Control Register
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD0MFP : PD.0 Multi-function Pin Selection
bits : 0 - 1 (2 bit)
access : read-write
PD1MFP : PD.1 Multi-function Pin Selection
bits : 2 - 3 (2 bit)
access : read-write
PD2MFP : PD.2 Multi-function Pin Selection
bits : 4 - 5 (2 bit)
access : read-write
PD3MFP : PC.3 Multi-function Pin Selection
bits : 6 - 7 (2 bit)
access : read-write
PD4MFP : PC.4 Multi-function Pin Selection
bits : 8 - 9 (2 bit)
access : read-write
PD5MFP : PD.5 Multi-function Pin Selection
bits : 10 - 11 (2 bit)
access : read-write
PD6MFP : PD.6 Multi-function Pin Selection
bits : 12 - 13 (2 bit)
access : read-write
PD7MFP : PD.7 Multi-function Pin Selection
bits : 14 - 15 (2 bit)
access : read-write
PD8MFP : PD.8 Multi-function Pin Selection
bits : 16 - 17 (2 bit)
access : read-write
PD9MFP : PD.9 Multi-function Pin Selection
bits : 18 - 19 (2 bit)
access : read-write
PD10MFP : PD.10 Multi-function Pin Selection
bits : 20 - 21 (2 bit)
access : read-write
PD11MFP : PD.11 Multi-function Pin Selection
bits : 22 - 23 (2 bit)
access : read-write
PD12MFP : PD.12 Multi-function Pin Selection
bits : 24 - 25 (2 bit)
access : read-write
PD13MFP : PD.13 Multi-function Pin Selection
bits : 26 - 27 (2 bit)
access : read-write
PD14MFP : PD.14 Multi-function Pin Selection
bits : 28 - 29 (2 bit)
access : read-write
PD15MFP : PD.15 Multi-function Pin Selection
bits : 30 - 31 (2 bit)
access : read-write
System Reset Source Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORF : POR Reset Flag
The POR reset flag is set by the Reset Signal from the Power-on Reset (POR) Controller to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from POR
#1 : 1
Power-on Reset (POR) Controller had issued the reset signal to reset the system
End of enumeration elements list.
PINRF : nRESET Pin Reset Flag
The nRESET pin reset flag is set by the Reset Signal from the nRESET Pin to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from nRESET pin
#1 : 1
Pin nRESET had issued the reset signal to reset the system
End of enumeration elements list.
WDTRF : Reset Source From WDG
The WDTRF flag is set if pervious reset source originates from the Watch-Dog module.
Note: Write 1 to clear this bit to 0.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from Watch-Dog
#1 : 1
The Watch-Dog module issued the reset signal to reset the system
End of enumeration elements list.
LVRF : LVR Reset Flag
The LVR reset flag is set by the Reset Signal from the Low Voltage Reset Controller to indicate the previous reset source.
Note1: Write 1 to clear this bit to 0.
Note2: If power rising reach 1.6V under 20us when fast power on, the LVRF will not happen.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from LVR
#1 : 1
LVR controller had issued the reset signal to reset the system
End of enumeration elements list.
BODRF : BOD Reset Flag
The BOD reset flag is set by the Reset Signal from the Brown Out Reset Controller to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from BOD
#1 : 1
BOD controller had issued the reset signal to reset the system
End of enumeration elements list.
PMURSTF : Reset Source From PMU
The PMURSTF flag is set by the reset signal from the PMU module to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from PMU
#1 : 1
The PMU has issued the reset signal to reset the system
End of enumeration elements list.
PINWK : Wakeup from DPD From PIN
The device was woken from Deep Power Down by a low transition on the RESETn pin.
Note: Write 1 to this register to clear all wakeup flags.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No wakeup from RESETn pin
#1 : 1
The device was issued a wakeup from DPD by a RESETn pin trasition
End of enumeration elements list.
TIMWK : Wakeup from DPD From TIMER
The device was woken from Deep Power Down by count of 10 KHz timer.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No wakeup from TIMER
#1 : 1
The device was issued a wakeup from DPD by a TIMER event
End of enumeration elements list.
PORWK : Wakeup from DPD From POR
The device was woken from Deep Power Down by a Power On Reset.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
No wakeup from POR
#1 : 1
The device was issued a wakeup from DPD by a POR
End of enumeration elements list.
GPIO Input Type and Slew Rate Control
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPxSSGPxHS : This register controls whether the GPIO input buffer Schmitt trigger is enabled and whether high or low slew rate is selected for output driver.
bits : 0 - 13 (14 bit)
access : read-write
PA.15 ~ PA.0 Pull Resistance Control Register
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUEN0 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN1 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN2 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN3 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN4 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN5 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN6 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN7 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN8 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN9 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN10 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN11 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN12 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN13 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN14 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN15 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PA.15 ~ PA.0 Pull Resistance Select Control Register
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUHR0 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR1 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR2 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR3 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR4 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR5 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR6 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR7 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR8 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR9 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR10 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR11 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR12 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR13 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR14 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR15 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PA.15 ~ PA.0 Digital and Analog Input Buffer Control Register
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IEN :
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input buffer Enabled
#1 : 1
Input buffer disabled, and input signal always equals to 0
End of enumeration elements list.
PB.1 ~ PB.0 Pull Resistance Control Register
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUEN0 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN1 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PB.1 ~ PB.0 Pull Resistance Select Control Register
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUHR0 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR1 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PB.1 ~ PB.0 Digital Input Buffer Control Register
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IEN0 :
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input buffer Enabled
#1 : 1
Input buffer disabled, and input signal always equals to 0
End of enumeration elements list.
IEN1 :
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input buffer Enabled
#1 : 1
Input buffer disabled, and input signal always equals to 0
End of enumeration elements list.
PC.15 ~ PC.0 Pull Resistance Control Register
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUEN0 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN1 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN2 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN3 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN4 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN5 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN6 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN7 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN8 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN9 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN10 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN11 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN12 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN13 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN14 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN15 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PC.15 ~ PC.0 Pull Resistance Select Control Register
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUHR0 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR1 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR2 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR3 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR4 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR5 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR6 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR7 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR8 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR9 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR10 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR11 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR12 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR13 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR14 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR15 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PC.15 ~ PC.0 Digital Input Buffer Control Register
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IEN :
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input buffer Enabled
#1 : 1
Input buffer disabled, and input signal always equals to 0
End of enumeration elements list.
PD.15 ~ PD.0 Pull Resistance Control Register
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUEN0 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN1 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN2 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN3 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN4 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN5 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN6 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN7 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN8 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN9 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN10 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN11 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN12 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN13 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN14 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PUEN15 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up function Disable
#1 : 1
Pull-Up function Enable
End of enumeration elements list.
PD.15 ~ PD.0 Pull Resistance Select Control Register
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUHR0 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR1 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR2 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR3 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR4 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR5 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR6 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR7 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR8 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR9 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR10 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR11 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR12 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR13 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR14 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PUHR15 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-Up 100K resistance
#1 : 1
Pull-Up 1M resistance
End of enumeration elements list.
PD.15 ~ PD.0 Digital Input Buffer Control Register
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IEN :
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input buffer Enabled
#1 : 1
Input buffer disabled, and input signal always equals to 0
End of enumeration elements list.
IP Reset Control Resister0
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIPRST : CHIP One Shot Reset
Set this bit will reset the whole chip, this bit will automatically return to 0 after 2 clock cycles.
CHIPRST is same as POR reset, all the chip modules are reset and the chip configuration settings from flash are reloaded.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal
#1 : 1
Reset CHIP
End of enumeration elements list.
CPURST : CPU Kernel One Shot Reset
Setting this bit will reset the CPU kernel and Flash Memory Controller (FMC), this bit will automatically return to 0 after the 2 clock cycles
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal
#1 : 1
Reset CPU
End of enumeration elements list.
IP Reset Control Resister1
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIORST : GPIO Controller Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
Reset
End of enumeration elements list.
TMR0RST : Timer0 Controller Reset
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Reset
End of enumeration elements list.
TMR1RST : Timer1 Controller Reset
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Reset
End of enumeration elements list.
TMR2RST : Timer2 Controller Reset
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
Reset
End of enumeration elements list.
CPDRST : Companding Controller Reset
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
Reset
End of enumeration elements list.
PDMARST : PDMA Controller Reset
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
Reset
End of enumeration elements list.
I2C0RST : I2C0 Controller Reset
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
Reset
End of enumeration elements list.
I2C1RST : I2C1 Controller Reset
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
Reset
End of enumeration elements list.
SPI1RST : SPI1 Controller Reset
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Reset
End of enumeration elements list.
SPI0RST : SPI0 Controller Reset
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Reset
End of enumeration elements list.
I2SRST : I2S Controller Reset
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Reset
End of enumeration elements list.
UART0RST : UART0 Controller Reset
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Reset
End of enumeration elements list.
UART1RST : UART1 Controller Reset
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Reset
End of enumeration elements list.
BIQRST : BIQ Controller Reset
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Reset
End of enumeration elements list.
PWM0RST : PWM0 Controller Reset
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Reset
End of enumeration elements list.
PWM1RST : PWM1 Controller Reset
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Reset
End of enumeration elements list.
USBRST : USB Controller Reset
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Reset
End of enumeration elements list.
SARADCRST : SARADC Controller Reset
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Reset
End of enumeration elements list.
DACRST : DAC Controller Reset
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Reset
End of enumeration elements list.
SDADCRST : SDADC Controller Reset
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Reset
End of enumeration elements list.
ANARST : Analog Block Controller Reset
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Reset
End of enumeration elements list.
System SRAM BIST Test Control Register
address_offset : 0xD0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAMBIST : SRAM BIST Enable Bit (Write Protect)
This bit enables BIST test for SRAM.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
system SRAM BIST Disabled
#1 : 1
system SRAM BIST Enabled
End of enumeration elements list.
CACHEBIST : CACHE SRAM BIST Enable Bit (Write Protect)
This bit enables BIST test for CACHE SRAM.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
CACHE SRAM BIST Disabled
#1 : 1
CACHE SRAM BIST Enabled
End of enumeration elements list.
System SRAM BIST Test Status Register
address_offset : 0xD4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SRAMBISTEF : System SRAM BIST Fail Flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
system SRAM BIST test pass
#1 : 1
system SRAM BIST test fail
End of enumeration elements list.
CACHEBISTEF : CACHE SRAM BIST Fail Flag
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
CACHE SRAM BIST test pass
#1 : 1
CACHE SRAM BIST test fail
End of enumeration elements list.
SRAMBEND : System SRAM BIST Test Finish
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
system SRAM BIST active
#1 : 1
system SRAM BIST finish
End of enumeration elements list.
CACHEBEND : CACHE SRAM BIST Test Finish
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
CACHE SRAM BIST is active
#1 : 1
CACHE SRAM BIST finish
End of enumeration elements list.
MAP3 Data Image Register
address_offset : 0xF0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IMG3 : Data Image of MAP3
Data in MAP3 of information block are copied to this register after power on.
bits : 0 - 31 (32 bit)
access : read-only
Device ID Register
address_offset : 0xF4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DEVICEID : Device ID Data
This register provides specific read-only information for the Device ID
bits : 0 - 15 (16 bit)
access : read-only
MAP0 Data Image Register
address_offset : 0xF8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IMG0 : Data Image of MAP0
Data in MAP0 of information block are copied to this register after power on.
bits : 0 - 31 (32 bit)
access : read-only
MAP1 Data Image Register
address_offset : 0xFC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IMG1 : Data Image of MAP1
Data in MAP1 of information block are copied to this register after power on.
bits : 0 - 31 (32 bit)
access : read-only
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.