\n
address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xC Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x1C Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
CPUID Base Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REVISION : Revision
Reads as 0x0
bits : 0 - 3 (4 bit)
access : read-only
PARTNO : Part Number
Reads as 0xC20.
bits : 4 - 15 (12 bit)
access : read-only
PART : ARMv6-m Parts
Reads as 0xC for ARMv6-M parts
bits : 16 - 19 (4 bit)
access : read-only
IMPCODE : Implementer Code Assigned by ARM
bits : 24 - 31 (8 bit)
access : read-only
System Control Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLPONEXC : Sleep on Exception
When set to 1, the core can enter a sleep state on an exception return to Thread mode. This is the mode and exception level entered at reset, the base level of execution. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
bits : 1 - 1 (1 bit)
access : read-write
SLPDEEP : Controls Whether the Processor Uses Sleep or Deep Sleep As Its Low Power Mode
The SLPDEEP flag is also used in conjunction with CLK_PWRCTL register to enter deeper power-down states than purely core sleep states.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
sleep
#1 : 1
deep sleep
End of enumeration elements list.
SEVNONPN : Send Event on Pending Bit
When enabled, interrupt transitions from Inactive to Pending are included in the list of wakeup events for the WFE instruction.
When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.
The processor also wakes up on execution of an SEV instruction.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded
#1 : 1
enabled events and all interrupts, including disabled interrupts, can wake-up the processor
End of enumeration elements list.
System Handler Priority Register 2
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI11 : Priority of System Handler 11 - SVCall
0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
System Handler Priority Register 3
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI14 : Priority of System Handler 14 - PendSV
0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI15 : Priority of System Handler 15 - SYST
0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
Interrupt Control State Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTACT : Vector Active
0: Thread mode
Value > 1: the exception number for the current executing exception.
bits : 0 - 8 (9 bit)
access : read-write
VTPEND : Vector Pending
Indicates the exception number for the highest priority pending exception. The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. A value of zero indicates no pending exceptions.
bits : 12 - 20 (9 bit)
access : read-write
ISRPEND : ISR Pending
Indicates if an external configurable (NVIC generated) interrupt is pending.
bits : 22 - 22 (1 bit)
access : read-write
ISRPREEM : ISR Preemptive
If set, a pending exception will be serviced on exit from the debug halt state.
bits : 23 - 23 (1 bit)
access : read-write
PSTKICLR : Clear a Pending SYST
Write 1 to clear a pending SYST.
bits : 25 - 25 (1 bit)
access : read-write
PSTKISET : Set a Pending SYST
Reads back with current state (1 if Pending, 0 if not).
bits : 26 - 26 (1 bit)
access : read-write
PPSVICLR : Clear a Pending PendSV Interrupt
Write 1 to clear a pending PendSV interrupt.
bits : 27 - 27 (1 bit)
access : read-write
PPSVISET : Set a Pending PendSV Interrupt
This is normally used to request a context switch. Reads back with current state (1 if Pending, 0 if not).
bits : 28 - 28 (1 bit)
access : read-write
NMIPNSET : NMI Pending Set Control
Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. Reads back with current state (1 if Pending, 0 if not).
bits : 31 - 31 (1 bit)
access : read-write
Application Interrupt and Reset Control Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRACTVT : Clear All Active Vector
Clears all active state information for fixed and configurable exceptions.
The effect of writing a 1 to this bit if the processor is not halted in Debug, is UNPREDICTABLE.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
do not clear state information
#1 : 1
clear state information
End of enumeration elements list.
SRSTREQ : System Reset Request
Writing 1 to this bit asserts a signal to request a reset by the external system.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
do not request a reset
#1 : 1
request reset
End of enumeration elements list.
ENDIANES : Endianness
Read Only. Reads 0 indicating little endian machine.
bits : 15 - 15 (1 bit)
access : read-write
VTKEY : Vector Key
The value 0x05FA must be written to this register, otherwise
a write to register is UNPREDICTABLE.
bits : 16 - 31 (16 bit)
access : read-write
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