MAC_CTL (CTL)

MAC_ARYPTR1 (ARYPTR1)

MAC_ACCR1R0 (ACCR1R0)

MAC_ACCR2 (ACCR2)

MAC_ACCCLIP (ACCCLIP)

MAC_MODIFY (MODIFY)

MAC_SHIFTCTL (SHIFTCTL)

MAC_ARYPTR0 (ARYPTR0)

CNT : When this register was written, MAC operation will start to execute (CNT+ 1) times. Only LSByte of CNT is valid.
bits : 0 - 7 (8 bit)
access : read-write

BUSY : MAC operation flag 0: MAC operation completed 1: MAC is under operation.
bits : 8 - 8 (1 bit)
access : read-write

ARYPTR1 : Address pointer points to a short integer data in Array1[ ]. ARYPTR1 will be revised after every MAC operation depending on value of MODIFY1. The value of ARYPTR1 is bytewise and must be even byte aligned. LSB of ARYPTR1[0] will be treated as 0 always This pointer can point to RAM space or Flash ROM space, depends on bit 29.
bits : 0 - 15 (16 bit)
access : read-write

RAM_SEL : 0: ARYPTR1 points to FLASH Space 1: ARYPTR1 points to RAM Space As RAM is mapped at 0x2000_0000 user can simply load MAC_ARYPTR1 with a RAM or ROM address.
bits : 29 - 29 (1 bit)
access : read-write

R1R0 : Write operation to this register will update ACC[31:0] (i.e. ACC_R1R0), and ACC[39:32] will sign extention from ACC_R1R0[31] automatically. Read operation from this register will get data in ACC[31:0].
bits : 0 - 31 (32 bit)
access : read-write

R2 : Write operation to this register will update ACC[39:32] (i.e. ACC_R2[7:0]). Data in ACC_R2[31:8] will be ignored. Read operation from this register will get data in ACC[39:32] and show in ACC_R2[7:0], ACC_R2[31:8] is sign extension of bit ACC_R2[7] automatically .
bits : 0 - 31 (32 bit)
access : read-write

CLIP : Read operation of this register will get clipped data in MAC ACC[39:0] register but clipped with the range: 0x00-7fff-ffff ~ 0xff-8000-0000. The content of ACC[39:0] will not be changed.
bits : 0 - 31 (32 bit)
access : read-only

MODIFY0 : Post modify register of address pointer ARYPTR0 of short integer Array_0[ ]. ARYPTR0 will update and point to next #MODIFY0 short integer in Array0[ ] after every MAC operation. MODIFY0 range from -16 ~ +15 in 2's complement format.
bits : 0 - 4 (5 bit)
access : read-write

MODIFY1 : Post modify register of address pointer ARYPTR1 of short integer Array_1[ ]. ARYPTR1 will update and point to next #MODIFY1 short integer in Array1[ ] after every MAC operation. MODIFY1 range from -16 ~ +15 in 2's complement format.
bits : 8 - 12 (5 bit)
access : read-write

INT_EN : MAC Interrupt enable.
bits : 30 - 30 (1 bit)
access : read-write

MAC_INT : MAC Interrupt flag. Write 1 to clear
bits : 31 - 31 (1 bit)
access : read-write

SHIFTCNT : Shift the content of Accumulator ACCR2:ACCR1R0. 0000: No Shift 0001: Right shift 1 bits 0100: Right shift 4 bits 1001: Left shift 1 bit 1100: Left shift 4 bits Others: reserved Note: Right shift with Sign extension in MSB and L.S with 0 filled in LSB
bits : 0 - 3 (4 bit)
access : write-only

ARYPTR0 : Address pointer point to short integer data in Array0[ ]. ARYPTR0 will be revised after every MAC operation depend on MODIFY0. The value of ARYPTR0 is bytewise and must be even byte aligned. LSB ARYPTR0[0] will be treat as 0 always This pointer only points to RAM space.
bits : 0 - 14 (15 bit)
access : read-write