CLK_PWRCTL (PWRCTL)

CLK_CLKSEL0 (CLKSEL0)

CLK_CLKSEL1 (CLKSEL1)

CLK_CLKDIV0 (CLKDIV0)

CLK_CLKDIV1 (CLKDIV1)

CLK_STATUS (STATUS)

CLK_PFLAG (PFLAG)

CLK_CLKSEL2 (CLKSEL2)

CLK_XCLKCTL (XCLKCTL)

CLK_PLLCTL (PLLCTL)

CLK_PLLTEST (PLLTEST)

CLK_AHBCLK (AHBCLK)

CLK_APBCLK (APBCLK)

CLK_HXTFSEL (HXTFSEL)

CLK_DPDFLR (DPDFLR)

CLK_TESTCLK (TESTCLK)

FWKEN : STOP/DeepSleep mode fast wakeup enable control Note: Normal wake up will count 2 LIRC first, and then switch to original HCLK source. Fast wakeup will direct switch to original HCLK source without any LIRC counting.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HXTEN : External high speed Crystal Oscillator Control After reset, this bit is 0 .
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HIRCEN : Internal high speed RC Oscillator Control After reset, this bit is 1 .
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HXTGAIN : HXT Gain Control Bit This is a protected register. Please refer to open lock sequence to program it. Gain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled, crystal will consume more power than gain control off.
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HXTTBEN : HXT Crystal TURBO Mode (Write Protect) This is a protected register. Please refer to open lock sequence to program it.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IOFWK : All IO pin is enabled fast wakeup in STOP/DeepSleep mode. When this bit set 0'b, trigger IO will delay 3 LIRC and then trigger wakeup from STOP/DeepSleep mode. When this bit set 1'b, trigger IO will wakeup from STOP/DeepSleep mode immediately.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKRDDLY : Enable the Clock Ready Delay Counter When HXT enable, the clock control will delay certain clock cycles to wait clock stable. The delayed clock cycle is 4096 clock cycles when external high speed crystal oscillator (HXT) enable.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STOPEN : STOP mode bit. Set to '1' and issue WFI/WFE instruction to enter STOP mode.
bits : 9 - 9 (1 bit)
access : read-write

DPDEN : Deep Power Down (DPD) bit. Set to '1' and issue WFI/WFE instruction to enter DPD mode.
bits : 10 - 10 (1 bit)
access : read-write

LIRCEN : Internal 10kHz Oscillator Control After reset, this bit is 0 .
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VSET : Adjusts the digital supply voltage. Should be left as default.
bits : 13 - 15 (3 bit)
access : read-write

WKPINEN : Determines whether WAKEUP pin(PA15) is enabled in DPD mode.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WK10KEN : Determines whether OSC10K is enabled in DPD mode. Note: If WK10KEN is disabled, device cannot wake from DPD with SELWKTMR delay.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLASHEN : Determine whether FLASH memory enters deep power down. If FLASHEN is selected for a power state mode, current consumption is reduced, but a 10us wakeup time must be added to the wakeup sequence. Trade-off is wakeup time for standby power.
bits : 18 - 19 (2 bit)
access : read-write

SELWKTMR : Select WAKEUP Timer:
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKPINWKF : Read Only. This flag indicates that wakeup of device was requested with a high to low transition of the WAKEUP pin. Flag is cleared when DPD mode is entered or any of the DPD bits of RSTSRC register (RSTSRC[10:8]) are cleared.
bits : 24 - 24 (1 bit)
access : read-write

TMRWKF : Read Only. This flag indicates that wakeup of device was requested with TIMER count of the 10Khz oscillator. Flag is cleared when DPD mode is entered or any of the DPD bits of RSTSRC register (RSTSRC [10:8]) are cleared.
bits : 25 - 25 (1 bit)
access : read-write

WKPUEN : Wakeup Pin Pull-up Control This signal is latched in deep power down and preserved.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKTMRSTS : Read-Only. Read back of the current WAKEUP timer setting. This value is updated with SELWKTMR upon entering DPD mode.
bits : 28 - 31 (4 bit)
access : read-write

HCLKSEL : HCLK Clock Source Select Note: 1. When power on, HIRC is selected as HCLK clock source. 2. Before clock switch, the related clock sources (pre-select and new-select) must be turned on.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STICKSEL : SYS_TICK Clock Source Select Note: 1. When power on, HIRC is selected as HCLK clock source. 2. Before clock switch, the related clock sources (pre-select and new-select) must be turned on. 3. SysTick clock source must less than or equal to HCLK/2.
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSCFSEL : HIRC Frequency Selection register These bits are protected, to write to bits first perform the unlock sequence (see Register Lock Control Register (SYS_REGLCTL))
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FCLK_MUX_STATE : These register state shows the current HCLK is from which source clock Others reserved.
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTSEL : Watchdog Timer Clock Source Selection (Write Protect) These bits are protected bits. To program these bits needs an open lock sequence, write 59h , 16h , 88h to SYS_REGLCTL to un-lock these bits. Refer to the register SYS_REGLCTL at address SYS_BA+0x100..
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SARADCSEL : SARADC Clock Source Select
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI0SEL : SPI0 Clock Source Select Note: SPI0 engine clock must be same clock source as PCLK
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI1SEL : SPI1 Clock Source Select Note: SPI1 engine clock must be same clock source as PCLK
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0SEL : Timer0 Clock Source Select
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1SEL : Timer1 Clock Source Select
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2SEL : Timer2 Clock Source Select
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2SSEL : I2S Clock Source Select
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART0SEL : UART0 Clock Source Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART1SEL : UART1 Clock Source Select
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0SEL : PWM Timer Clock Source Select
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM1SEL : PWM Timer Clock Source Select
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HCLKDIV : HCLK Clock Divide Number From HCLK Clock Source
bits : 0 - 3 (4 bit)
access : read-write

UART0DIV : UART0 Clock Divide Number From UART0 Clock Source Note: UART0 engine clock must smaller or equal to PCLK.
bits : 4 - 7 (4 bit)
access : read-write

UART1DIV : UART1 Clock Divide Number From UART1 Clock Source Note: UART1 engine clock must smaller or equal to PCLK.
bits : 8 - 11 (4 bit)
access : read-write

USBDIV : USB Clock Divide Number From PLL Clock
bits : 12 - 15 (4 bit)
access : read-write

SARADCDIV : SARADC Clock Divide Number From ADC Clock Source
bits : 16 - 22 (7 bit)
access : read-write

DACDIV : DAC Clock Divide Number From DAC Clock Source
bits : 0 - 7 (8 bit)
access : read-write

BIQDIV : BIQ Clock Divide Number From HCLK Note: BIQ clock frequency must keep PCLK/2
bits : 8 - 11 (4 bit)
access : read-write

SDADCDIV : SDADC Clock Divide Number From SDADC Clock Source
bits : 16 - 23 (8 bit)
access : read-write

HXTSTB : HXT Clock Source Stable Flag (Read Only)
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LIRCSTB : LIRC Clock Source Stable Flag (Read Only)
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HIRCSTB : HIRC clock source stable flag(Read only)
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PLLSTB : Internal PLL Clock Source Stable Flag (Read Only)
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

XCLKSTB : XCLK Clock Source Stable Flag (Read Only)
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DSF : Deep Sleep Flag This flag is set if core logic was placed in Deep Sleep mode. Write '1' to clear flag.
bits : 0 - 0 (1 bit)
access : read-write

STOPF : Stop Flag This flag is set if core logic was stopped but not powered down. Write '1' to clear flag.
bits : 1 - 1 (1 bit)
access : read-write

USBSEL : USB Clock Source Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

XCLKSEL : Clock Doubler Source Selection
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DACSEL : DAC Clock Source Select
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SDADCSEL : SDADC Clock Source Select
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

XCLKMUL : Clock doubler Output Frequency Multiplication
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

XCLKEN : XCLK Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RELOCK : XCLK relock enable setting When write this bit to 1'b, the XCLK will execute relock action. And this bit will auto clear to 0'b after relock finish and XCLK output clock stable.
bits : 5 - 5 (1 bit)
access : read-write

XCLKFDEN : XCLK Clock Fail Detector Enable Bit
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

XCLKFIEN : XCLK Clock Fail Interrupt Enable Bit
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

XCLKFIF : XCLK Clock Fail Interrupt Flag Note: Write 1 to clear the bit to 0.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FBDIV : PLL Feedback Divider Control (Write Protected) Refer to the formulas below the table. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 5 (6 bit)
access : read-write

INDIV : PLL Input Divider Control (Write Protected) Refer to the formulas below the table. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 9 - 12 (4 bit)
access : read-write

OUTDIV : PLL Output Divider Control (Write Protected) Refer to the formulas below the table. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 14 - 15 (2 bit)
access : read-write

PD : Power-down Mode (Write Protected) If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BP : PLL Bypass Control (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OE : PLL OE (FOUT Enable) Pin Control (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLLSRC : PLL Source Clock Selection (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 19 - 20 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FTREN : Fliter Enable Control
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STBSEL : PLL Stable Counter Selection (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ICP : PLL charge Pump Current (Write Protect) Adjust PLL charge pump current by these register. Default value is 0x1. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 3 (4 bit)
access : read-write

ICPMIS : PLL charge Pump Current Mismatch Compensation Selection (Write Protect) Compensation PLL charge pump current mismatch by these registers. Default value is 0x0. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 11 (4 bit)
access : read-write

IVCO : VCO Current Current (Write Protect) Control VCO current. Default value is 0x0. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 17 (2 bit)
access : read-write

PDMACKEN : PDMA Clock Enable Control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPDCKEN : Companding Clock Enable Control
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPCKEN : Flash ISP Controller Clock Enable Control. The Flash ISP engine clock always is from 49 MHz RC oscillator.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTEN : Watchdog Clock Enable Control This bit is the protected bit. To program this bit needs an open lock sequence, write 59h , 16h , 88h to register SYS_REGLCTL to un-lock this bit. Refer to the register SYS_REGLCTL at address SYS_BA+0x100.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0EN : Timer0 Clock Enable Control
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1EN : Timer1 Clock Enable Control
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2EN : Timer2 Clock Enable Control
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C0EN : I2C0 Clock Enable Control
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C1EN : I2C1 Clock Enable Control
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI1EN : SPI1 Clock Enable Control
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI0EN : SPI0 Clock Enable Control
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2SEN : I2S Clock Enable Control
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART0EN : UART0 Block Clock Enable Control
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART1EN : UART1 Block Clock Enable Control
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BIQEN : Biquad Filter(BIQ) Block Clock Enable Control
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0EN : PWM0 Block Clock Enable Control
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM1EN : PWM1 Block Clock Enable Control
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USBEN : USB Clock Enable Control
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SARADCEN : Analog-Digital-Converter (SARADC) Clock Enable Control
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DACEN : DAC Clock Enable Control
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SDADCEN : SDADC Clock Enable Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ANAEN : Analog Block Clock Enable Control
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HXTFSEL : HXT Filter Select Note: This bit is auto cleared by hardware.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HXTGEN : HXT output gating enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PD_STATE : An 8bit register that is preserved when DPD (Deep Power Down) state is entered and after wakeup is available by reading PD_STATE_RB.
bits : 0 - 7 (8 bit)
access : read-write

PD_STATE_RB : Current values of PD_STATE register.
bits : 8 - 15 (8 bit)
access : read-write

TCLKSEL : Test Clock Source Selection
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TESTEN : Test Clock Output Enable Bit Test clock will output through PD0 pin
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TESTCKDIV : Test Clock Output Divider
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.