PA_MODE

PA_PIN

PA_INTTYPE

PA_INTEN

PA_INTSRC

PB_MODE

PB_DOUT

PB_PIN

PB_INTTYPE

PB_INTEN

PB_INTSRC

PA_DOUT

PC_MODE

PA0_PDIO

PA1_PDIO

PA2_PDIO

PA3_PDIO

PA4_PDIO

PA5_PDIO

PA6_PDIO

PA7_PDIO

PA8_PDIO

PA9_PDIO

PA10_PDIO

PA11_PDIO

PA12_PDIO

PA13_PDIO

PA14_PDIO

PA15_PDIO

PB0_PDIO

PB1_PDIO

PB2_PDIO

PB3_PDIO

PB4_PDIO

PB5_PDIO

PB6_PDIO

PB7_PDIO

PB8_PDIO

PB9_PDIO

PB10_PDIO

PB11_PDIO

PC_DOUT

PC0_PDIO

PC1_PDIO

PC2_PDIO

PC3_PDIO

PC4_PDIO

PC5_PDIO

PC6_PDIO

PC7_PDIO

PC8_PDIO

PC9_PDIO

PC10_PDIO

PC11_PDIO

PC12_PDIO

PC13_PDIO

PC14_PDIO

PC15_PDIO

PD0_PDIO

PD1_PDIO

PD2_PDIO

PD3_PDIO

PD4_PDIO

PD5_PDIO

PD6_PDIO

PD7_PDIO

PD8_PDIO

PD9_PDIO

PD10_PDIO

PD11_PDIO

PD12_PDIO

PD13_PDIO

PD14_PDIO

PD15_PDIO

PC_PIN

PC_INTTYPE

PC_INTEN

PC_INTSRC

PD_MODE

PD_DOUT

PD_PIN

PD_INTTYPE

PD_INTEN

PD_INTSRC

MODE0 : Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE1 : Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE2 : Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE3 : Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE4 : Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE5 : Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0.
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE6 : Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0.
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE7 : Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0.
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE8 : Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0.
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE9 : Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0.
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE10 : Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0.
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE11 : Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE12 : Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0.
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE13 : Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0.
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE14 : Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0.
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE15 : Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0.
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIN : Port [A/B/C/D] Pin[N] Pin Values Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: PB_PIN [15:2] are reserved to 0.
bits : 0 - 15 (16 bit)
access : read-only

TYPE : Port [A/B/C/D] Pin[N] Edge Or Level Detection Interrupt Trigger Type Control TYPE[n] is used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is level triggered, the input source is sampled by one HCLK clock to generate the interrupt Note 1: If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register. If both levels are set, the setting is ignored and no interrupt will occur Note 2: PB_INTTYPE [15:2] are reserved to 0.
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN0 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN1 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN2 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN3 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN4 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN5 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN6 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN7 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN8 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN9 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN10 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN11 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN12 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN13 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN14 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN15 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN0 : Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN1 : Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN2 : Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN3 : Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN4 : Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN5 : Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN6 : Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN7 : Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN8 : Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN9 : Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN10 : Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN11 : Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN12 : Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN13 : Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN14 : Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN15 : Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC : Port [A/B/C/D] Interrupt Source Flag Read operation: Note: PB_INTSRC [15:2] are reserved to 0.
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT : Port [A/B/C/D] Pin[N] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output or open-drain mode. Note: PB_DOUT [15:2] are reserved to 0.
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDIO : GPIO Px.n Pin Data Input/Output Writing this bit can control one GPIO pin output value.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.