\n

PWM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x1C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x28 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x34 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x40 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x50 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x58 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x7C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

Registers

PWM_CLKPSC

PWM_CMPDAT0

PWM_CNT

PWM_CMPDAT1

PWM_CMPDAT2

PWM_CMPDAT3

PWM_CLKDIV

PWM_INTEN

PWM_INTSTS

PWM_CAPCTL

PWM_RCAPDAT

PWM_FCAPDAT

PWM_PCEN

PWM_CTL

PWM_PERIOD


PWM_CLKPSC

PWM Prescaler Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CLKPSC PWM_CLKPSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKPSC DZI0 DZI1

CLKPSC : Clock Prescaler For PWM Timer Clock input is divided by (CLKPSC + 1)
bits : 0 - 7 (8 bit)
access : read-write

DZI0 : Dead Zone Interval Register 0 These 8 bits determine dead zone length. The unit time of dead zone length is that from clock selector.
bits : 16 - 23 (8 bit)
access : read-write

DZI1 : Dead Zone Interval Register 1 These 8 bits determine dead zone length. The unit time of dead zone length is that from clock selector.
bits : 24 - 31 (8 bit)
access : read-write


PWM_CMPDAT0

PWM Comparator Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CMPDAT0 PWM_CMPDAT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP

CMP : PWM Comparator Register CMP determines the PWM duty ratio. Assumption: PWM output initial is high Note2: Any write to CMP will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write


PWM_CNT

PWM Counter Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PWM_CNT PWM_CNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : PWM Counter Register Reports the current value of the 16-bit down counter.
bits : 0 - 15 (16 bit)
access : read-only


PWM_CMPDAT1

PWM Comparator Register 1
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CMPDAT1 PWM_CMPDAT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM_CMPDAT2

PWM Comparator Register 2
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CMPDAT2 PWM_CMPDAT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM_CMPDAT3

PWM Comparator Register 3
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CMPDAT3 PWM_CMPDAT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM_CLKDIV

PWM Clock Select Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CLKDIV PWM_CLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKDIV

CLKDIV : PWM Timer Clock Source Selection Value : Input clock divided by 000 : 2 001 : 4 010 : 8 011 : 16 1xx : 1
bits : 0 - 2 (3 bit)
access : read-write


PWM_INTEN

PWM Interrupt Enable Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_INTEN PWM_INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIEN

PIEN : PWM Timer Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.


PWM_INTSTS

PWM Interrupt Flag Register
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_INTSTS PWM_INTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIF

PIF : PWM Timer Interrupt Flag Flag is set by hardware when PWM down counter reaches zero, software can clear this bit by writing '1' to it.
bits : 0 - 0 (1 bit)
access : read-write


PWM_CAPCTL

Capture Control Register
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CAPCTL PWM_CAPCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPINV CRLIEN CFLIEN CAPEN CAPIF CRLIF CFLIF

CAPINV : Inverter ON/OFF
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Inverter OFF

#1 : 1

Inverter ON. Reverse the input signal from GPIO before fed to Capture timer

End of enumeration elements list.

CRLIEN : Rising Latch Interrupt Enable ON/OFF When enabled, capture block generates an interrupt on rising edge of input.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable rising latch interrupt

#1 : 1

Enable rising latch interrupt

End of enumeration elements list.

CFLIEN : Falling Latch Interrupt Enable ON/OFF When enabled, capture block generates an interrupt on falling edge of input.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable falling latch interrupt

#1 : 1

Enable falling latch interrupt

End of enumeration elements list.

CAPEN : Capture Channel Input Transition Enable/Disable When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition. When disabled, Capture function is inactive as is interrupt.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable capture function

#1 : 1

Enable capture function

End of enumeration elements list.

CAPIF : Capture Indication Flag Note:If this bit is 1 (not clear by SW), PWM counter will not be reloaded when next capture event occurs.
bits : 4 - 4 (1 bit)
access : read-write

CRLIF : PWM_RCAPDAT Latched Indicator Bit When input channel has a rising transition, PWM_RCAPDAT was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
bits : 6 - 6 (1 bit)
access : read-write

CFLIF : PWM_FCAPDAT Latched Indicator Bit When input channel has a falling transition, PWM_FCAPDAT was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
bits : 7 - 7 (1 bit)
access : read-write


PWM_RCAPDAT

Capture Rising Latch Register
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PWM_RCAPDAT PWM_RCAPDAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCAPDAT

RCAPDAT : Capture Rising Latch Register In Capture mode, this register is latched with the value of the PWM counter on a rising edge of the input signal.
bits : 0 - 15 (16 bit)
access : read-only


PWM_FCAPDAT

Capture Falling Latch Register
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PWM_FCAPDAT PWM_FCAPDAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCAPDAT

FCAPDAT : Capture Falling Latch Register In Capture mode, this register is latched with the value of the PWM counter on a falling edge of the input signal.
bits : 0 - 15 (16 bit)
access : read-only


PWM_PCEN

PWM Output and Capture Input Enable Register
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_PCEN PWM_PCEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POEN0 POEN1 POEN2 POEN3 CAPINEN

POEN0 : PWM Channel0 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP)
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable PWM Channel0 output to pin

#1 : 1

Enable PWM Channel0 output to pin

End of enumeration elements list.

POEN1 : PWM Channel 1 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP)
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable PWM Channel 1 output to pin

#1 : 1

Enable PWM Channel 1 output to pin

End of enumeration elements list.

POEN2 : PWM Channel 2 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP)
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable PWM Channel 2output to pin

#1 : 1

Enable PWM Channel 2 output to pin

End of enumeration elements list.

POEN3 : PWM Channel 3 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP)
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable PWM Channel 3 output to pin

#1 : 1

Enable PWM Channel 3 output to pin

End of enumeration elements list.

CAPINEN : Capture Input Enable Register
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

OFF (PA.7/PB.4 pin input disconnected from Capture block)

#1 : 1

ON (PA.7/PB.4 pin, if in PWM alternative function, will be configured as an input and fed to capture function)

End of enumeration elements list.


PWM_CTL

PWM Control Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CTL PWM_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTEN PINV CNTMODE DTEN0 DTEN1

CNTEN : PWM-Timer Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Stop PWM-Timer Running

#1 : 1

Enable PWM-Timer

End of enumeration elements list.

PINV : PWM-Timer Output Inverter ON/OFF
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Inverter OFF

#1 : 1

Inverter ON

End of enumeration elements list.

CNTMODE : PWM-Timer Auto-Reload/One-Shot Mode
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

One-Shot Mode

#1 : 1

Auto-reload Mode

End of enumeration elements list.

DTEN0 : Dead-Zone 0 Generator Enable/Disable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

DTEN1 : Dead-Zone 1 Generator Enable/Disable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.


PWM_PERIOD

PWM Period Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_PERIOD PWM_PERIOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIOD

PERIOD : PWM Counter/Timer Reload Value PERIOD determines the PWM period.
bits : 0 - 15 (16 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.