Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPIEN : SPI Transfer Enable
In Master mode, the transfer will start when there is data in the FIFO buffer after this is set to 1. In Slave mode, the device is ready to receive data when this bit is set to 1.
Note:
All configuration should be set before writing 1 to this SPIEN bit. (e.g.: TXNEG, RXNEG, DWIDTH, LSB, CLKP, and so on).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable SPI Transfer
#1 : 1
Enable SPI Transfer
End of enumeration elements list.
RXNEG : Receive at Negative Edge
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The received data input signal is latched at the rising edge of SCLK
#1 : 1
The received data input signal is latched at the falling edge of SCLK
End of enumeration elements list.
TXNEG : Transmit at Negative Edge
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The transmitted data output signal is changed at the rising edge of SCLK
#1 : 1
The transmitted data output signal is changed at the falling edge of SCLK
End of enumeration elements list.
CLKP : Clock Polarity
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
SCLK idle low
#1 : 1
SCLK idle high
End of enumeration elements list.
SUSPITV : Suspend Interval (Master Only)
The four bits provide configurable suspend interval between two successive transmit/receive transactions in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation. SUSPITV is available for standard SPI transactions, it must be set to 0 for DUAL and QUAD mode transactions.
(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
Example:
Note:
For DUAL and QUAD transactions with SUSPITV must be set to 0.
bits : 4 - 7 (4 bit)
access : read-write
DWIDTH : DWIDTH - Data Word Bit Length
This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted.
bits : 8 - 12 (5 bit)
access : read-write
LSB : LSB First
Note:
For DUAL and QUAD transactions with LSB must be set to 0.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The MSB is transmitted/received first (which bit in TX and RX FIFO depends on the DWIDTH field)
#1 : 1
The LSB is sent first on the line (bit 0 of TX FIFO]), and the first bit received from the line will be put in the LSB position in the SPIn_RX FIFO (bit 0 SPIn_RX)
End of enumeration elements list.
TWOBIT : Two Bits Transfer Mode
When 2-bit mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data. As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable two-bit transfer mode
#1 : 1
Enable two-bit transfer mode
End of enumeration elements list.
IE : Unit Transfer Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable SPI Unit Transfer Interrupt
#1 : 1
Enable SPI Unit Transfer Interrupt to CPU
End of enumeration elements list.
SLAVE : Master Slave Mode Control
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Master mode
#1 : 1
Slave mode
End of enumeration elements list.
REORDER : Byte Reorder Function Enable
Note:
Byte reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
REORDER is only available for Receive mode in DUAL and QUAD transactions.
For DUAL and QUAD transactions with REORDER, SUSPITV must be set to 0.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Byte reorder function Disabled
#1 : 1
Byte reorder function Enabled. A byte suspend interval will be inserted between each byte. The period of the byte suspend interval depends on the setting of SUSPITV
End of enumeration elements list.
QDIODIR : Quad or Dual I/O Mode Direction Control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Quad or Dual Input mode
#1 : 1
Quad or Dual Output mode
End of enumeration elements list.
DUALIOEN : Dual I/O Mode Enable
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dual I/O mode Disabled
#1 : 1
Dual I/O mode Enabled
End of enumeration elements list.
QUADIOEN : Quad I/O Mode Enable
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Quad I/O mode Disabled
#1 : 1
Quad I/O mode Enabled
End of enumeration elements list.
RXTCNTEN : DMA Receive Transaction Count Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable function
#1 : 1
Enable transaction counter for DMA receive only mode. SPI will perform the number of transfers specified in the SPI_RXTSNCNT register, allowing the SPI interface to read ahead of DMA controller
End of enumeration elements list.
RXMODEEN : FIFO Receive Mode Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable function
#1 : 1
Enable FIFO receive mode. In this mode SPI transactions will be continuously performed while RXFULL is not active. To stop transactions, set RXMODEEN to 0
End of enumeration elements list.
FIFO Control/Status Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXRST : Clear Receive FIFO Buffer
Note: If there is slave receive time out event, the RXRST will be set 1 when the SPI_SSCTL.SLVTORST, is enabled.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear receive FIFO buffer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clocks + 3 SPI engine clock after it is set to 1
End of enumeration elements list.
TXRST : Clear Transmit FIFO Buffer
Note: If there is slave receive time out event, the TXRST will be set 1 when the SPI_SSCTL.SLVTORST, is enabled.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear transmit FIFO buffer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clocks + 3 SPI engine clock after it is set to 1
End of enumeration elements list.
RXTHIEN : Receive FIFO Threshold Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
RX FIFO threshold interrupt Disabled
#1 : 1
RX FIFO threshold interrupt Enabled
End of enumeration elements list.
TXTHIEN : Transmit FIFO Threshold Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
TX FIFO threshold interrupt Disabled
#1 : 1
TX FIFO threshold interrupt Enabled
End of enumeration elements list.
RXTOIEN : Slave Receive Time-out Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive time-out interrupt Disabled
#1 : 1
Receive time-out interrupt Enabled
End of enumeration elements list.
RXOVIEN : Receive FIFO Overrun Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive FIFO overrun interrupt Disabled
#1 : 1
Receive FIFO overrun interrupt Enabled
End of enumeration elements list.
TXUDFPOL : Transmit Under-run Data Out
Note: The under run event is active after the serial clock input and the hardware synchronous, so that the first 1~3 bit (depending on the relation between system clock and the engine clock) data out will be the last transaction data.
Note: If the frequency of system clock approach the engine clock, they may be a 3-bit time to report the transmit under-run data out.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The SPI data out is 0 if there is transmit under-run event in Slave mode
#1 : 1
The SPI data out is 1 if there is transmit under-run event in Slave mode
End of enumeration elements list.
TXUDFIEN : Slave Transmit Under Run Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave Transmit FIFO under-run interrupt Disabled
#1 : 1
Slave Transmit FIFO under-run interrupt Enabled
End of enumeration elements list.
RXTH : Receive FIFO Threshold
If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
000: 1 word will transmit
001: 2 word will transmit
010: 3 word will transmit
011: 4 word will transmit
100: 5 word will transmit
101: 6 word will transmit
110: 7 word will transmit
111: 8 word will transmit
bits : 24 - 26 (3 bit)
access : read-write
TXTH : Transmit FIFO Threshold
If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
000: 1 word will transmit
001: 2 word will transmit
010: 3 word will transmit
011: 4 word will transmit
100: 5 word will transmit
101: 6 word will transmit
110: 7 word will transmit
111: 8 word will transmit
bits : 28 - 30 (3 bit)
access : read-write
Status Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUSY : SPI Unit Bus Status (Read Only)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
No transaction in the SPI bus
#1 : 1
SPI controller unit is in busy state
End of enumeration elements list.
UNITIF : Unit Transfer Interrupt Status
Note: This bit will be cleared by writing 1 to itself.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No transaction has been finished since this bit was cleared to 0
#1 : 1
SPI controller has finished one unit transfer
End of enumeration elements list.
SSACTIF : Slave Select Active Interrupt Status
Note: This bit will be cleared by writing 1 to itself.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select active interrupt is clear or not occur
#1 : 1
Slave select active interrupt event has occur
End of enumeration elements list.
SSINAIF : Slave Select Inactive Interrupt Status
Note: This bit will be cleared by writing 1 to itself.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select inactive interrupt is clear or not occur
#1 : 1
Slave select inactive interrupt event has occur
End of enumeration elements list.
SSLINE : Slave Select Line Bus Status (Read Only)
Note: If SPI_SSCTL.SSLVL is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Indicates the slave select line bus status is 0
#1 : 1
Indicates the slave select line bus status is 1
End of enumeration elements list.
SLVTOIF : Slave Time-out Interrupt Status (Read Only)
When the Slave Select is active and the value of SLVTOCNT is not 0 and the serial clock input, the slave time-out counter in SPI controller logic will be start. When the value of time-out counter greater or equal than the value of SPI_SSCTL.SLVTOCNT, during before one transaction done, the slave time-out interrupt event will active.
Note: If the DWIDTH is set 16, one transaction is equal 16 bits serial clock period.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Slave time-out is not active
#1 : 1
Slave time-out is active
End of enumeration elements list.
SLVBEIF : Slave Mode Error 0 Interrupt Status (Read Only)
In Slave mode, there is bit counter mismatch with DWIDTH when the slave select line goes to inactive state.
Note: If the slave select active but there is no any serial clock input, the SLVBEIF also active when the slave select goes to inactive state.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
No Slave mode error 0 event
#1 : 1
Slave mode error 0 occurs
End of enumeration elements list.
SLVURIF : Slave Mode Error 1 Interrupt Status (Read Only)
In Slave mode, transmit under-run occurs when the slave select line goes to inactive state.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No Slave mode error 1 event
#1 : 1
Slave mode error 1 occurs
End of enumeration elements list.
RXEMPTY : Receive FIFO Buffer Empty Indicator (Read Only)
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive FIFO buffer is not empty
#1 : 1
Receive FIFO buffer is empty
End of enumeration elements list.
RXFULL : Receive FIFO Buffer Full Indicator (Read Only)
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive FIFO buffer is not full
#1 : 1
Receive FIFO buffer is full
End of enumeration elements list.
RXTHIF : Receive FIFO Threshold Interrupt Status (Read Only)
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RXTH
#1 : 1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH
End of enumeration elements list.
RXOVIF : Receive FIFO Overrun Status
When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
Note: This bit will be cleared by writing 1 to itself.
bits : 11 - 11 (1 bit)
access : read-write
RXTOIF : Receive Time-out Interrupt Status
Note: This bit will be cleared by writing 1 to itself.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No receive FIFO time-out event
#1 : 1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI engine clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
End of enumeration elements list.
SPIENSTS : SPI Enable Bit Status (Read Only)
Note: The clock source of SPI controller logic is engine clock, it is asynchronous with the system clock. In order to make sure the function is disabled in SPI controller logic, this bit indicates the real status of SPIEN in SPI controller logic for user.
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
Indicate the transmit control bit is disabled
#1 : 1
Indicate the transfer control bit is active
End of enumeration elements list.
TXEMPTY : Transmit FIFO Buffer Empty Indicator (Read Only)
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO buffer is not empty
#1 : 1
Transmit FIFO buffer is empty
End of enumeration elements list.
TXFULL : Transmit FIFO Buffer Full Indicator (Read Only)
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO buffer is not full
#1 : 1
Transmit FIFO buffer is full
End of enumeration elements list.
TXTHIF : Transmit FIFO Threshold Interrupt Status (Read Only)
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
The valid data count of the transmit FIFO buffer is larger than the setting value of TXTH
#1 : 1
The valid data count of the transmit FIFO buffer is less than or equal to the setting value of TXTH
End of enumeration elements list.
TXUFIF : Slave Transmit FIFO Under-run Interrupt Status (Read Only)
When the transmit FIFO buffer is empty and further serial clock pulses occur, data transmitted will be the value of the last transmitted bit and this under-run bit will be set.
Note: This bit will be cleared by writing 1 to itself.
bits : 19 - 19 (1 bit)
access : read-only
TXRXRST : FIFO CLR Status (Read Only)
Note: Both the TXRST, RXRST, need 3 system clock + 3 engine clocks, the status of this bit allows the user to monitor whether the clear function is busy or done.
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
#0 : 0
Done the FIFO buffer clear function of TXRST and RXRST
#1 : 1
Doing the FIFO buffer clear function of TXRST or RXRST
End of enumeration elements list.
RXCNT : Receive FIFO Data Count (Read Only)
This bit field indicates the valid data count of receive FIFO buffer.
bits : 24 - 27 (4 bit)
access : read-only
TXCNT : Transmit FIFO Data Count (Read Only)
This bit field indicates the valid data count of transmit FIFO buffer.
bits : 28 - 31 (4 bit)
access : read-only
Receive Transaction Count Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXTSNCNT : DMA Receive Transaction Count
When using DMA to receive SPI data without transmitting data, this register can be used in conjunction with the control bit SPI_CTL.RXTCNTEN to set number of transactions to perform. Without this, the SPI interface will only initiate a transaction when it receives a request from the DMA system, resulting in a lower achievable data rate.
bits : 0 - 15 (16 bit)
access : read-write
FIFO Data Transmit Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TX : Data Transmit Register
A write to the data transmit register pushes data onto into the 8-level transmit FIFO buffer. The number of valid bits depends on the setting of transmit bit width field of the SPI_CTL register.
For example, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0, the SPI controller will perform a 32-bit transfer.
bits : 0 - 31 (32 bit)
access : write-only
FIFO Data Receive Register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX : Data Receive Register
A read from this register pops data from the 8-level receive FIFO. Valid data is present if the SPI_STATUS. RXEMPTY bit is not set to 1. This is a read-only register.
bits : 0 - 31 (32 bit)
access : read-only
SPI BIST Control Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXBISTEN : SPI RX SRAM BIST Enable Bit (Write Protect)
This bit enables BIST test for ADC SRAM.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI RX SRAM BIST Disabled
#1 : 1
SPI RX SRAM BIST Enabled
End of enumeration elements list.
RXBISTEND : SPI RX SRAM BIST Test Finish
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI RX SRAM BIST active
#1 : 1
SPI RX SRAM BIST finish
End of enumeration elements list.
RXBISTEF : SPI RX SRAM BIST Fail Flag
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI RX SRAM BIST pass
#1 : 1
SPI RX SRAM BIST fail
End of enumeration elements list.
TXBISTEN : SPI TX SRAM BIST Enable Bit (Write Protect)
This bit enables BIST test for ADC SRAM.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI TX SRAM BIST Disabled
#1 : 1
SPI TX SRAM BIST Enabled
End of enumeration elements list.
TXBISTEND : SPI TX SRAM BIST Test Finish
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI TX SRAM BIST active
#1 : 1
SPI TX SRAM BIST finish
End of enumeration elements list.
TXBISTEF : SPI TX SRAM BIST Fail Flag
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI TX SRAM BIST pass
#1 : 1
SPI TX SRAM BIST fail
End of enumeration elements list.
Clock Divider Register (Master Only)
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVIDER : Clock Divider Register
The value in this field is the frequency divider for generating the SPI engine clock,Fspi_sclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation.
where
Fspi_clockSRC is the SPI engine clock source, which is defined in the clock control, CLKSEL1 register.
Note: SPI engine clock must smaller than PCLK/2
bits : 0 - 7 (8 bit)
access : read-write
Slave Select Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SS : Slave Select Control Bits (Master Only)
If AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.
If the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPI_SS0/1 line at inactive state writing 1 to any bit location of this field will select appropriate SPI_SS0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPI_SS0/1 is specified in SSLVL.
Note: SPI_SS0 is defined as the slave select input in Slave mode.
bits : 0 - 1 (2 bit)
access : read-write
SSLVL : Slave Select Active Level
This bit defines the active status of slave select signal (SPI_SS0/1).
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The slave select signal SPI_SS0/1 is active on low-level/falling-edge
#1 : 1
The slave select signal SPI_SS0/1 is active on high-level/rising-edge
End of enumeration elements list.
AUTOSS : Automatic Slave Select Function Enable (Master Only)
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
If this bit is cleared, slave select signals will be asserted/de-asserted by setting/clearing the corresponding bits of SPI_SSCTL[1:0]
#1 : 1
If this bit is set, SPI_SS0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSCTL[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
End of enumeration elements list.
SLV3WIRE : Slave 3-wire Mode Enable
This is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface consisting of SPI_CLK, SPI_MISO, and SPI_MOSI.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
4-wire bi-directional interface
#1 : 1
3-wire bi-directional interface
End of enumeration elements list.
SLVTOIEN : Slave Mode Time-out Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave mode time-out interrupt Disabled
#1 : 1
Slave mode time-out interrupt Enabled
End of enumeration elements list.
SLVTORST : Slave Mode Time-out FIFO Clear
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Function disabled
#1 : 1
Both the FIFO clear function, TXRST and RXRST, are activated automatically when there is a slave mode time-out event
End of enumeration elements list.
SLVBCEIEN : Slave Mode Error 0 Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave mode error 0 interrupt Disable
#1 : 1
Slave mode error 0 interrupt Enable
End of enumeration elements list.
SLVUDRIEN : Slave Mode Error 1 Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave mode error 1 interrupt Disable
#1 : 1
Slave mode error 1 interrupt Enable
End of enumeration elements list.
SSACTIEN : Slave Select Active Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select active interrupt Disable
#1 : 1
Slave select active interrupt Enable
End of enumeration elements list.
SSINAIEN : Slave Select Inactive Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select inactive interrupt Disable
#1 : 1
Slave select inactive interrupt Enable
End of enumeration elements list.
SLVTOCNT : Slave Mode Time-out Period
In Slave mode, these bits indicate the time out period when there is serial clock input during slave select active. The clock source of the time out counter is Slave engine clock. If the value is 0, it indicates the slave mode time-out function is disabled.
bits : 16 - 31 (16 bit)
access : read-write
SPI PDMA Control Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXPDMAEN : Transmit DMA Enable
Setting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.
bits : 0 - 0 (1 bit)
access : read-write
RXPDMAEN : Receive PDMA Enable
Setting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware automatically after PDMA transfer is done.
bits : 1 - 1 (1 bit)
access : read-write
PDMARST : PDMA Reset
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 automatically
End of enumeration elements list.
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