I2S_CTL0 (CTL0)

I2S_TXFIFO (TXFIFO)

I2S_RXFIFO (RXFIFO)

I2S_TEST (TEST)

I2S_CTL1 (CTL1)

I2S_STATUS1 (STATUS1)

I2S_CLKDIV (CLKDIV)

I2S_IEN (IEN)

I2S_STATUS0 (STATUS0)

I2SEN : I2S Controller Enable Control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXEN : Transmit Enable Control
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXEN : Receive Enable Control
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MUTE : Transmit Mute Enable Control
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATWIDTH : Data Width This bit field is used to define the bit-width of data word in each audio channel
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MONO : Monaural Data Control Note: when chip records data, RXLCH (I2S_CTL0[23]) indicates which channel data will be saved if monaural format is selected.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ORDER : Stereo Data Order in FIFO In 8-bit/16-bit data width, this bit is used to select whether the even or odd channel data is stored in higher byte. In 24-bit data width, this is used to select the left/right alignment method of audio data which is stored in data memory consisted of 32-bit FIFO entries. MSB of 24-bit audio data in each channel is aligned to left side in 32-bit FIFO entries.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLAVE : Slave Mode Enable Control Note: I2S can operate as master or slave. For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send out bit clock to Audio CODEC chip. In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MCLKEN : Master Clock Enable Control If MCLKEN is set to 1, I2S controller will generate master clock on I2S_MCLK pin for external audio devices.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FRZCDEN : Force Right Channel Zero Cross Data Option Bit If this bit set to 1, when channel data sign bit changes or next shift data bits are all 0 then the channel ZCIF flag in I2S_STATUS1 register is set to 1 and channel data will force zero. This function is only available in transmit operation.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLZCDEN : Force Left Channel Zero Cross Data Option Bit If this bit set to 1, when channel data sign bit changes or next shift data bits are all 0 then the channel ZCIF flag in I2S_STATUS1 register is set to 1 and channel data will force zero. This function is only available in transmit operation.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXFBCLR : Transmit FIFO Buffer Clear Note1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT (I2S_STATUS1[12:8]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed. Note2: This bit is clear by hardware automatically, read it return zero.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXFBCLR : Receive FIFO Buffer Clear Note1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS1[20:16]) returns 0 and receive FIFO becomes empty. Note2: This bit is cleared by hardware automatically, read it return zero.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXPDMAEN : Transmit PDMA Enable Control
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXPDMAEN : Receive PDMA Enable Control
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXLCH : Receive Left Channel Enable Control
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FORMAT : Data Format Selection
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PCMSYNC : PCM Synchronization Pulse Length Selection This bit field is used to select the high pulse length of frame synchronization signal in PCM protocol Note: This bit is only available in master mode
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHWIDTH : Channel Width This bit fields are used to define the length of audio channel. If CHWIDTH < DATWIDTH, the hardware will set the real channel length as the bit-width of audio data which is defined by DATWIDTH.
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXFIFO : Transmit FIFO Bits I2S contains 16 words (16x32 bit) data buffer for data transmit. Write data to this register to prepare data for transmit. The remaining word number is indicated by TXCNT (I2S_STATUS1[12:8]).
bits : 0 - 31 (32 bit)
access : write-only

RXFIFO : Receive FIFO Bits I2S contains 16 words (16x32 bit) data buffer for data receive. Read this register to get data in FIFO. The remaining data word number is indicated by RXCNT (I2S_STATUS1[20:16]).
bits : 0 - 31 (32 bit)
access : read-only

LOOKBACK : Look Back Control Set this bit, the TX and RX are connected
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BCLKINV : BCLK Invert Control
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0ZCEN : Channel0 Zero-cross Detection Enable Control Note2: If this bit is set to 1, when channel0 data sign bit change or next shift data bits are all zero then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1. Note3: If CH0ZCIF Flag is set to 1, the channel0 will be mute.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1ZCEN : Channel1 Zero-cross Detect Enable Control Note2: If this bit is set to 1, when channel1 data sign bit change or next shift data bits are all zero then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1. Note3: If CH1ZCIF Flag is set to 1, the channel1 will be mute.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXTH : Transmit FIFO Threshold Level Note: If remain data word number in transmit FIFO is the same or less than threshold level then TXTHIF (I2S_STATUS0[18]) flag is set.
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXTH : Receive FIFO Threshold Level Note: When received data word number in receive buffer is greater than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set.
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBWIDTH : Peripheral Bus Data Width Selection This bit is used to choice the available data width of APB bus. It must be set to 1 while PDMA function is enable and it is set to 16-bit transmission mode
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB16ORD : FIFO Read/Write Order in 16-bit Width of Peripheral Bus
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0ZCIF : Channel0 Zero-cross Interrupt Flag It indicates channel0 next sample data sign bit is changed or all data bits are zero.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1ZCIF : Channel1 Zero-cross Interrupt Flag It indicates channel1 next sample data sign bit is changed or all data bits are zero.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXCNT : Transmit FIFO Level (Read Only) These bits indicate the number of available entries in transmit FIFO Others are reserved. Do not use.
bits : 8 - 12 (5 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXCNT : Receive FIFO Level (Read Only) These bits indicate the number of available entries in receive FIFO Others are reserved. Do not use.
bits : 16 - 20 (5 bit)
access : read-only

Enumeration:

End of enumeration elements list.

MCLKDIV : Master Clock Divider If chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip. If MCLKDIV is set to 0, MCLK is the same as external clock input. Note: F_MCLK is the frequency of MCLK, and F_I2SCLK is the frequency of the I2S_CLK
bits : 0 - 6 (7 bit)
access : read-write

BCLKDIV : Bit Clock Divider The I2S controller will generate bit clock in Master mode. Software can program these bit fields to generate sampling rate clock frequency. Note: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK
bits : 8 - 17 (10 bit)
access : read-write

RXUDFIEN : Receive FIFO Underflow Interrupt E Enable Control Note: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXOVFIEN : Receive FIFO Overflow Interrupt Enable Control Note: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXTHIEN : Receive FIFO Threshold Level Interrupt Enable Control Note: When data word in receive FIFO is equal or higher than RXTH (I2S_CTL1[19:16]) and the RXTHIF (I2S_STATUS0[10]) bit is set to 1. If RXTHIEN bit is enabled, interrupt occur.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXUDFIEN : Transmit FIFO Underflow Interrupt Enable Control Note: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXOVFIEN : Transmit FIFO Overflow Interrupt Enable Control Note: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXTHIEN : Transmit FIFO Threshold Level Interrupt Enable Control Note: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH (I2S_CTL1[11:8]).
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0ZCIEN : Channel0 Zero-cross Interrupt Enable Control
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1ZCIEN : Channel1 Zero-cross Interrupt Enable Control
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2SINT : I2S Interrupt Flag (Read Only) Note: It is wire-OR of I2STXINT and I2SRXINT bits.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

I2SRXINT : I2S Receive Interrupt (Read Only)
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

I2STXINT : I2S Transmit Interrupt (Read Only)
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DATACH : Transmission Data Channel (Read Only) This bit fields are used to indicate which audio channel is current transmit data belong.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXUDIF : Receive FIFO Underflow Interrupt Flag Note1: When receive FIFO is empty, and software reads the receive FIFO again. This bit will be set to 1, and it indicates underflow situation occurs. Note2: Write 1 to clear this bit to zero
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXOVIF : Receive FIFO Overflow Interrupt Flag Note1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote. Note2: Write 1 to clear this bit to 0.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXTHIF : Receive FIFO Threshold Interrupt Flag (Read Only) Note: When data word(s) in receive FIFO is higher than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1. It keeps at 1 till RXCNT (I2S_STATUS1[20:16]) is not higher than RXTH (I2S_CTL1[19:16]) after software read RXFIFO register.
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXFULL : Receive FIFO Full (Read Only) Note: This bit reflects data words number in receive FIFO is 12.
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXEMPTY : Receive FIFO Empty (Read Only) Note: This bit reflects data words number in receive FIFO is zero
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXUDIF : Transmit FIFO Underflow Interrupt Flag Note1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame. Note2: Write 1 to clear this bit to 0.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXOVIF : Transmit FIFO Overflow Interrupt Flag Note1: Write data to transmit FIFO when it is full and this bit set to 1 Note2: Write 1 to clear this bit to 0.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXTHIF : Transmit FIFO Threshold Interrupt Flag (Read Only) Note: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1. It keeps at 1 till TXCNT (I2S_STATUS1[12:8]) is higher than TXTH (I2S_CTL1[11:8]) after software write TXFIFO register.
bits : 18 - 18 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXFULL : Transmit FIFO Full (Read Only) This bit reflect data word number in transmit FIFO is 12
bits : 19 - 19 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXEMPTY : Transmit FIFO Empty (Read Only) This bit reflect data word number in transmit FIFO is zero
bits : 20 - 20 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXBUSY : Transmit Busy (Read Only) Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out. And set to 1 when 1st data is load to shift buffer.
bits : 21 - 21 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.