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address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x20 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x34 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x40 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
Timer0 Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSC : Timer Clock Prescaler
Note: No matter CNTEN is 0 or 1, whenever software writes a new value into this register, TIMER will restart counting by using this new value and abort previous count.
bits : 0 - 7 (8 bit)
access : read-write
ACTSTS : Timer Active Status Bit (Read Only)
This bit indicates the counter status of Timer.
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
Timer is not active
#1 : 1
Timer is active
End of enumeration elements list.
RSTCNT : Counter Reset Bit
Set this bit will reset the Timer counter, pre-scale and also force CNTEN to 0.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset Timer's pre-scale counter, internal 16-bit up-counter and CNTEN bit
End of enumeration elements list.
OPMODE : Timer Operating Mode
Note: When changing the Timer Operating Mode, the CNTEN bit should be set to 0 disable first.
bits : 27 - 28 (2 bit)
access : read-write
Enumeration:
#00 : 0
The Timer is operating in the one-shot mode. The associated interrupt signal is generated once (if INTEN is 1) and CNTEN is automatically cleared by hardware
#01 : 1
The Timer is operating in the periodic mode. The associated interrupt signal is generated periodically (if INTEN is 1)
#10 : 2
Reserved
#11 : 3
The Timer is operating in continuous counting mode. The associated interrupt signal is generated when TIMERx_CNT = TIMERx_CMP (if INTEN is 1) however, the 16-bit up-counter counts continuously without reset
End of enumeration elements list.
INTEN : Interrupt Enable Bit
If timer interrupt is enabled, and time-out flag (TIF) is 1'b .The timer asserts its interrupt signal to CPU.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable TIMER Interrupt
#1 : 1
Enable TIMER Interrupt
End of enumeration elements list.
CNTEN : Counter Enable Bit
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stop/Suspend counting
#1 : 1
Start counting
End of enumeration elements list.
Timer1 Control and Status Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 Compare Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 Interrupt Status Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 Data Register
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IR Carrier Output Control Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NONCS : Non-carrier state
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
IROUT keeps low when IRCEN is 0,
#1 : 1
IROUT keeps high when IRCEN is 0
End of enumeration elements list.
IRCEN : IR carrier output enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable IR carrier output,
#1 : 1
Enable IR carrier output. Timer1 time out will toggle the output state on IROUT pin
End of enumeration elements list.
Timer0 Compare Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPDAT : Timer Comparison Value
CMPDAT is a 16-bit comparison register. When the 16-bit up-counter is enabled and its value is equal to CMPDAT value, a Timer out flag (TIF) is requested.
Note 1: Never set CMPDAT to 0x000 or 0x001. Timer will not function correctly.
Note 2: No matter CNTEN is 0 or 1, whenever software writes a new value into this register, TIMER will restart counting by using this new value and abort previous count.
bits : 0 - 15 (16 bit)
access : read-write
Timer2 Control and Status Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer2 Compare Register
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer2 Interrupt Status Register
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer2 Data Register
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer0 Interrupt Status Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIF : Timer Interrupt Flag (Read Only)
This bit indicates the interrupt status of Timer.
TIF bit is set by hardware when the 16-bit counter matches the timer comparison value (CMPDAT). It is cleared by writing 1 to itself
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
No effect
#1 : 1
CNT (TIMERx_CNT [15:0]) value matches the CMPDAT (TIMERx_CMP[15:0]) value
End of enumeration elements list.
Timer0 Data Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Timer Data Register
User can read this register for the current up-counter value while TIMERx_CTL.CNTEN is set to 1,
bits : 0 - 15 (16 bit)
access : read-only
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