SARADC_DAT0 (DAT0)

SARADC_DAT4 (DAT4)

SARADC_DAT5 (DAT5)

SARADC_DAT6 (DAT6)

SARADC_DAT7 (DAT7)

SARADC_DAT8 (DAT8)

SARADC_DAT9 (DAT9)

SARADC_DAT10 (DAT10)

SARADC_DAT11 (DAT11)

SARADC_DAT12 (DAT12)

SARADC_DAT13 (DAT13)

SARADC_DAT14 (DAT14)

SARADC_CTL (CTL)

SARADC_DAT1 (DAT1)

SARADC_CHSEQ0 (CHSEQ0)

SARADC_CHSEQ1 (CHSEQ1)

SARADC_CMP0 (CMP0)

SARADC_CMP1 (CMP1)

SARADC_STATUS0 (STATUS0)

SARADC_STATUS1 (STATUS1)

SARADC_PDMADAT (PDMADAT)

SARADC_HWPARA (HWPARA)

SARADC_DAT2 (DAT2)

SARADC_DAT3 (DAT3)

RESULT : A/D Conversion Result This field contains the 12-bit conversion result. Its data format is defined by ADCFM bit.
bits : 0 - 11 (12 bit)
access : read-only

EXTS : Extension Bits Of RESULT for Different Data Format If ADCFM is 0 , EXTS all are read as 0 . If ADCFM is 1 , EXTS all are read as bit RESULT [11].
bits : 12 - 15 (4 bit)
access : read-only

OV : Over Run Flag If converted data in RESULT [11:0] have not been read before new conversion result is loaded to this register, OV is set to 1. It is cleared by hardware after ADC_DAT register is read.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

VALID : Valid Flag This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read.
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ADCEN : A/D Converter Enable Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCIE : A/D Interrupt Enable A/D conversion end interrupt request is generated if ADCIE bit is set to 1.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE : A/D Converter Operation Mode Note 1: When changing the operation mode, software should disable SWTRG bit firstly.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMAEN : PDMA Transfer Enable Bit When A/D conversion is completed, the converted data is loaded into ADC_DATn (n: 0 ~ 1314) register, user can enable this bit to generate a PDMA data transfer request.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MUXSW : MUXEN software control register 0 : MUX always enable turn on 1 : MUX control by MUXEN
bits : 5 - 5 (1 bit)
access : read-write

DLYTRIM : Trim bit for SARADC speed
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MUXEN : Input channel MUX enable control
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODESEL : SARADC conversion speed mode selection
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OVRIE : Sample rate over interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SWTRG : A/D Conversion Start Note1: SWTRG bit can be reset to 0 by software, or can be cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channel. In continuous scan mode, A/D conversion is continuously performed sequentially until software writes 0 to this bit or chip resets. Note2: Before trigger SWTRG to start ADC convert , the ADC relative setting should be completed.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCFM : Data Format Of ADC Conversion Result
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHSEQ0 : Select Channel N As The 1st Conversion In Scan Sequence
bits : 0 - 3 (4 bit)
access : read-write

CHSEQ1 : Select Channel N As The 2nd Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 4 - 7 (4 bit)
access : read-write

CHSEQ2 : Select Channel N As The 3rd Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 8 - 11 (4 bit)
access : read-write

CHSEQ3 : Select Channel N As The 4th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 12 - 15 (4 bit)
access : read-write

CHSEQ4 : Select Channel N As The 5th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 16 - 19 (4 bit)
access : read-write

CHSEQ5 : Select Channel N As The 6th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 20 - 23 (4 bit)
access : read-write

CHSEQ6 : Select Channel N As The 7th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 24 - 27 (4 bit)
access : read-write

CHSEQ7 : Select Channel N As The 8th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 28 - 31 (4 bit)
access : read-write

CHSEQ8 : Select Channel N As The 9th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 0 - 3 (4 bit)
access : read-write

CHSEQ9 : Select Channel N As The 10th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 4 - 7 (4 bit)
access : read-write

CHSEQ10 : Select Channel N As The 11th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 8 - 11 (4 bit)
access : read-write

CHSEQ11 : Select Channel N As The 12th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 12 - 15 (4 bit)
access : read-write

CHSEQ12 : Select Channel N As The 13th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 16 - 19 (4 bit)
access : read-write

CHSEQ13 : Select Channel N As The 14th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 20 - 23 (4 bit)
access : read-write

CHSEQ14 : Select Channel N As The 15th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 24 - 27 (4 bit)
access : read-write

ADCMPEN : Compare Enable Set this bit to 1 to enable the comparison CMPDAT with specified channel conversion result when converted data is loaded into SARADC_DAT register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCMPIE : Compare Interrupt Enable When converted data in RESULT is less (or greater) than the compare data CMPDAT, ADCMPF bit is asserted. If ADCMPIE is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCOND : Compare Condition
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCH : Compare Channel Selection
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPMCNT : Compare Match Count When the specified A/D channel analog conversion result matches the comparing condition, the internal match counter will increase 1. When the internal counter achieves the setting, (CMPMCNT+1) hardware will set the ADCMPF bit.
bits : 8 - 11 (4 bit)
access : read-write

CMPDAT : Compare Data This field possessing 12-bit compare data, is used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage transition in scan mode without imposing a load on software. The data format should be consistent with the setting of ADCFM bit.
bits : 16 - 27 (12 bit)
access : read-write

ADIF : A/D Conversion End Flag A status flag that indicates the end of A/D conversion. ADIF is set to 1 under the following two conditions: When A/D conversion ends in single mode, When A/D conversion ends on all channels specified by channel sequence register in scan mode. And it is cleared when 1 is written.
bits : 0 - 0 (1 bit)
access : read-write

ADCMPF0 : Compare Flag0 When the selected channel A/D conversion result meets setting conditions in SARADC_CMP0, then this bit is set to 1. And it is cleared by write 1.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCMPF1 : Compare Flag1 When the selected channel A/D conversion result meets setting conditions in SARADC_CMP1, then this bit is set to 1. And it is cleared by write 1.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSY : BUSY/IDLE This bit is mirror of SWTRG bit in SARADC_CTL. It is read only.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHANNEL : Current Conversion Channel It is read only.
bits : 4 - 7 (4 bit)
access : read-write

OVRF : Sampling rate over flag It is cleared when 1 is written.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VALID : Data Valid Flag It is a mirror of VALID bit in SARADC_DATn.
bits : 0 - 14 (15 bit)
access : read-write

OV : Over Run Flag It is a mirror to OV bit in SARADC_DATn.
bits : 16 - 30 (15 bit)
access : read-write

DATA : SARADC PDMA transfer data This is a read only register.
bits : 0 - 15 (16 bit)
access : read-write

SHCLKN : Specify the high level of SARADC start signal. Note: SHCLKN must larger than 400ns.
bits : 0 - 5 (6 bit)
access : read-write

CONVN : Specify SARADC conversion clock number To update this field, programmer can only revise bit [14:8] and keep other bits the same as before. Note: CONVN value must bigger than SHCLKN value and should bigger than 2us(500KSPS).
bits : 8 - 14 (7 bit)
access : read-write