Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection :
PDMA Channel x Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMACEN : PDMA Channel Enable
Setting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.
bits : 0 - 0 (1 bit)
access : read-write
SWRST : Software Engine Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writing 0 to this bit has no effect
#1 : 1
Writing 1 to this bit will reset the internal state machine and pointers. The contents of the control register will not be cleared. This bit will auto clear after a few clock cycles
End of enumeration elements list.
MODESEL : PDMA Mode Select
This parameter selects to transfer direction of the PDMA channel. Possible values are:
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Memory to Memory mode (SRAM-to-SRAM)
#01 : 1
IP to Memory mode (APB-to-SRAM)
#10 : 2
Memory to IP mode (SRAM-to-APB)
End of enumeration elements list.
SASEL : Source Address Select
This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed, incremented or wrapped.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Transfer Source address is incremented
#01 : 1
Reserved
#10 : 2
Transfer Source address is fixed
#11 : 3
Transfer Source address is wrapped. When CBCR (Current Byte Count) equals zero, the CSAR (Current Source Address) and CBCR registers will be reloaded from the SAR (Source Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMACEN=0. When PDMACEN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address
End of enumeration elements list.
DASEL : Destination Address Select
This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed, incremented or wrapped.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Transfer Destination Address is incremented
#01 : 1
Reserved
#10 : 2
Transfer Destination Address is fixed (Used when data transferred from multiple addresses to a single destination such as peripheral FIFO input)
#11 : 3
Transfer Destination Address is wrapped. When CBCR (Current Byte Count) equals zero, the CDAR (Current Destination Address) and CBCR registers will be reloaded from the DAR (Destination Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMA_EN=0. When PDMA_EN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address
End of enumeration elements list.
WAINTSEL : Wrap Interrupt Select
x1x1: Both half and w interrupts generated.
bits : 12 - 15 (4 bit)
access : read-write
APBTWS : Peripheral Transfer Width Select.
This parameter determines the data width to be transferred each PDMA transfer operation.
Note: This field is meaningful only when MODESEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB).
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
#00 : 0
One word (32 bits) is transferred for every PDMA operation
#01 : 1
One byte (8 bits) is transferred for every PDMA operation
#10 : 2
One half-word (16 bits) is transferred for every PDMA operation
#11 : 3
Reserved
End of enumeration elements list.
TRGEN : Trigger Enable - Start a PDMA operation.
Note: When PDMA transfer completed, this bit will be cleared automatically.
If a bus error occurs, all PDMA transfer will be stopped. Software must reset PDMA channel, and then trigger again.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Write: no effect. Read: Idle/Finished
#1 : 1
Enable PDMA data read or write transfer
End of enumeration elements list.
PDMA Channel x Internal Buffer Pointer Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
POINT : PDMA Internal Buffer Pointer Register (Read Only)
A PDMA transaction consists of two stages, a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between the read and write transactions are different, this register tracks which byte/half-word of the internal buffer is being processed by the current transaction.
bits : 0 - 3 (4 bit)
access : read-only
PDMA Channel x Current Source Address Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CSAR : PDMA Current Source Address Register (Read Only)
This register returns the source address from which the PDMA transfer is occurring. This register is loaded from SAR when PDMA is triggered or when a wraparound occurs.
bits : 0 - 31 (32 bit)
access : read-only
PDMA Channel x Current Destination Address Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CDAR : PDMA Current Destination Address Register (Read Only)
This register returns the destination address to which the PDMA transfer is occurring. This register is loaded from DAR when PDMA is triggered or when a wraparound occurs.
bits : 0 - 31 (32 bit)
access : read-only
PDMA Channel x Current Transfer Byte Count Register
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CBCR : PDMA Current Byte Count Register (Read Only)
This field indicates the current remaining byte count of PDMA transfer. This register is initialized with BCR register when PDMA is triggered or when a wraparound occurs
bits : 0 - 15 (16 bit)
access : read-only
PDMA Channel x Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ABTIEN : PDMA Read/Write Target Abort Interrupt Enable
If enabled, the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted, PDMA channel must be reset to resume DMA operation.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PDMA transfer target abort interrupt generation
#1 : 1
Enable PDMA transfer target abort interrupt generation
End of enumeration elements list.
TXIEN : PDMA Transfer Done Interrupt Enable
If enabled, the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PDMA transfer done interrupt generation
#1 : 1
Enable PDMA transfer done interrupt generation
End of enumeration elements list.
WRAPIEN : Wraparound Interrupt Enable
If enabled, and channel source or destination address is in wraparound mode, the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of CSR.WAINTSEL. This can be interrupts when the transaction has finished and has wrapped around and/or when the transaction is half way in progress. This allows the efficient implementation of circular buffers for DMA.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable Wraparound PDMA interrupt generation
#1 : 1
Enable Wraparound interrupt generation
End of enumeration elements list.
PDMA Channel x Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ABTIF : PDMA Read/Write Target Abort Interrupt Flag
This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller receives a bus error from AHB master. Upon occurrence PDMA will stop transfer and go to idle state. To resume, software must reset PDMA channel and initiate transfer again.
Note: This bit is cleared by writing 1 to itself.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No bus ERROR response received
#1 : 1
Bus ERROR response received
End of enumeration elements list.
TXIF : Block Transfer Done Interrupt Flag
This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transfer ongoing or Idle
#1 : 1
Transfer Complete
End of enumeration elements list.
WRAPIF : Wrap around transfer byte count interrupt flag.
These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits.
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0001 : 1
Current transfer finished flag (CBCR==0)
#0100 : 4
Current transfer half complete flag (CBCR==BCR/2)
End of enumeration elements list.
INTR : Interrupt Pin Status (Read Only)
This bit is the Interrupt pin status of PDMA channel.
bits : 31 - 31 (1 bit)
access : read-only
PDMA Channel x Source Address Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : PDMA Transfer Source Address Register
This register holds the initial Source Address of PDMA transfer.
Note: The source address must be word aligned.
bits : 0 - 31 (32 bit)
access : read-write
PDMA Channel x Destination Address Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : PDMA Transfer Destination Address Register
This register holds the initial Destination Address of PDMA transfer.
Note: The destination address must be word aligned.
bits : 0 - 31 (32 bit)
access : read-write
PDMA Channel x Transfer Byte Count Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BCR : PDMA Transfer Byte Count Register
This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF.
Note: The transfer byte count must be word aligned, that is multiples of 4bytes.
bits : 0 - 15 (16 bit)
access : read-write
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