\n

PDMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

Registers

PDMA_GCRCSR

PDMA_PDSSR0

PDMA_PDSSR1

PDMA_GCRISR


PDMA_GCRCSR

PDMA Global Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_GCRCSR PDMA_GCRCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RST HCLKEN

RST : PDMA Software Reset Note: This bit can reset all channels register(global reset) , but not reset each channel internal state machine.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Writing 0 to this bit has no effect

#1 : 1

Writing 1 to this bit will reset the internal state machine and pointers. The contents of control register will be cleared. This bit will auto clear after several clock cycles

End of enumeration elements list.

HCLKEN : PDMA Controller Channel Clock Enable Control To enable clock for channel n HCLKEN[n] must be set.
bits : 8 - 15 (8 bit)
access : read-write


PDMA_PDSSR0

PDMA Service Selection Control Register 0
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_PDSSR0 PDMA_PDSSR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI0RXSEL SPI0TXSEL I2SRXSEL I2STXSEL UART1RXSEL UART1TXSEL UART0RXSEL UART0TXSEL

SPI0RXSEL : PDMA SPI0 Receive Selection This field defines which PDMA channel is connected to SPI0 peripheral receive (PDMA source) request.
bits : 0 - 3 (4 bit)
access : read-write

SPI0TXSEL : PDMA SPI0 Transmit Selection This field defines which PDMA channel is connected to SPI0 peripheral transmit (PDMA destination) request.
bits : 4 - 7 (4 bit)
access : read-write

I2SRXSEL : PDMA I2S Receive Selection This field defines which PDMA channel is connected to I2S peripheral receive (PDMA source) request.
bits : 8 - 11 (4 bit)
access : read-write

I2STXSEL : PDMA I2S Transmit Selection This field defines which PDMA channel is connected to I2S peripheral transmit (PDMA destination) request.
bits : 12 - 15 (4 bit)
access : read-write

UART1RXSEL : PDMA UART1 Receive Selection This field defines which PDMA channel is connected to UART1 peripheral receive (PDMA source) request.
bits : 16 - 19 (4 bit)
access : read-write

UART1TXSEL : PDMA UART1 Transmit Selection This field defines which PDMA channel is connected to UART1 peripheral transmit (PDMA destination) request.
bits : 20 - 23 (4 bit)
access : read-write

UART0RXSEL : PDMA UART0 Receive Selection This field defines which PDMA channel is connected to UART0 peripheral receive (PDMA source) request.
bits : 24 - 27 (4 bit)
access : read-write

UART0TXSEL : PDMA UART0 Transmit Selection This field defines which PDMA channel is connected to UART0 peripheral transmit (PDMA destination) request.
bits : 28 - 31 (4 bit)
access : read-write


PDMA_PDSSR1

PDMA Service Selection Control Register 1
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_PDSSR1 PDMA_PDSSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDADCSEL DACTXSEL SARADCSEL SPI1RXSEL SPI1TXSEL

SDADCSEL : PDMA SDADC Receive Selection This field defines which PDMA channel is connected to SDADC peripheral receive (PDMA source) request.
bits : 0 - 3 (4 bit)
access : read-write

DACTXSEL : PDMA DAC Transmit Selection This field defines which PDMA channel is connected to DAC peripheral transmit (PDMA destination) request.
bits : 4 - 7 (4 bit)
access : read-write

SARADCSEL : PDMA SARADC Receive Selection This field defines which PDMA channel is connected to SARADC peripheral receive (PDMA source) request.
bits : 8 - 11 (4 bit)
access : read-write

SPI1RXSEL : PDMA SPI1 Receive Selection This field defines which PDMA channel is connected to SPI1 peripheral receive (PDMA source) request.
bits : 16 - 19 (4 bit)
access : read-write

SPI1TXSEL : PDMA SPI1 Transmit Selection This field defines which PDMA channel is connected to SPI1 peripheral transmit (PDMA destination) request.
bits : 20 - 23 (4 bit)
access : read-write


PDMA_GCRISR

PDMA Global Interrupt Status Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PDMA_GCRISR PDMA_GCRISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GCRISR

GCRISR : Interrupt Pin Status (Read Only) GCRISR[n] is the interrupt status of PDMA channel n.
bits : 0 - 7 (8 bit)
access : read-only



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