\n
address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection :
UART Receive/Transmit FIFO Register.
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAT : Receive/Transmit FIFO Register
Reading this register will return data from the receive data FIFO. By reading this register, the UART will return the 8-bit data received from Rx pin (LSB first).
By writing to this register, transmit data will be pushed onto the transmit FIFO. The UART will send out an 8-bit data through the Tx pin (LSB first).
bits : 0 - 7 (8 bit)
access : read-write
UART Modem Control Register.
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTS : RTS (Request-To-Send) Signal
bits : 1 - 1 (1 bit)
access : read-write
LBMEN : Loopback Mode Enable.
bits : 4 - 4 (1 bit)
access : read-write
RTSACTLV : Request-to-Send (RTS)Active Trigger Level
This bit can change the RTS trigger level.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTS is active high level
#1 : 1
RTS is active low level
End of enumeration elements list.
RTSSTS : RTS Pin State(read only)
This bit is the pin status of RTS.
bits : 13 - 13 (1 bit)
access : read-only
UART Modem Status Register.
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTSDETF : Detect CTS State Change Flag
Note: This bit is cleared by writing 1 to itself.
bits : 0 - 0 (1 bit)
access : read-write
CTSSTS : CTS Pin Status (read only)
This bit is the pin status of CTS.
bits : 4 - 4 (1 bit)
access : read-only
CTSACTLV : Clear-to-Send (CTS)Active Trigger Level
This bit can change the CTS trigger level.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
CTS is active high level
#1 : 1
CTS is active low level
End of enumeration elements list.
UART FIFO Status Register.
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXOVIF : Rx Overflow Error Interrupt Flag
If the Rx FIFO (UART->DATA) is full, and an additional byte is received by the UART, an overflow condition will occur and set this bit to logic 1. It will also generate a BUFERRIF event and interrupt if enabled.
Note: This bit is cleared by writing 1 to itself.
bits : 0 - 0 (1 bit)
access : read-write
PEF : Parity Error Flag
This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit.
bits : 4 - 4 (1 bit)
access : read-write
FEF : Framing Error Flag
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0),and is reset whenever the CPU writes 1 to this bit.
bits : 5 - 5 (1 bit)
access : read-write
BIF : Break Interrupt Flag
This bit is set to a logic 1 whenever the receive data input(Rx) is held in the space state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). It is reset whenever the CPU writes 1 to this bit.
bits : 6 - 6 (1 bit)
access : read-write
RXPTR : Rx FIFO pointer (Read Only)
This field returns the Rx FIFO buffer pointer. It is the number of bytes available for read in the Rx FIFO. When UART receives one byte from external device, RXPTR is incremented. When one byte of Rx FIFO is read by CPU, RXPTR is decremented.
bits : 8 - 13 (6 bit)
access : read-only
RXEMPTY : Receive FIFO Empty(Read Only)
This bit indicates whether the Rx FIFO is empty or not.
When the last byte of Rx FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
bits : 14 - 14 (1 bit)
access : read-only
RXFULL : Receive FIFO Full(Read Only)
This bit indicates whether the Rx FIFO is full or not.
This bit is set when RxFIFO is full otherwise it is cleared by hardware.
bits : 15 - 15 (1 bit)
access : read-only
TXPTR : Tx FIFO Pointer (Read Only)
This field returns the Tx FIFO buffer pointer. When CPU writes a byte into the TxFIFO, TXPTR is incremented. When a byte from Tx FIFO is transferred to the Transmit Shift Register, TXPTR is decremented.
bits : 16 - 21 (6 bit)
access : read-only
TXEMPTY : Transmit FIFO Empty(Read Only)
This bit indicates whether the Tx FIFO is empty or not.
When the last byte of Tx FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared after writing data to FIFO (Tx FIFO not empty).
bits : 22 - 22 (1 bit)
access : read-only
TXFULL : Transmit FIFO Full(Read Only)
This bit indicates whether the Tx FIFO is full or not.
bits : 23 - 23 (1 bit)
access : read-only
TXOVIF : Tx Overflow Error Interrupt Flag
If the Tx FIFO (UART->DATA) is full, an additional write to UART->DATA will cause an overflow condition and set this bit to logic 1. It will also generate a BUFERRIF event and interrupt if enabled.
Note: This bit is cleared by writing 1 to itself.
bits : 24 - 24 (1 bit)
access : read-write
TXEMPTYF : Transmitter Empty (Read Only)
Bit is set by hardware when Tx FIFO is empty and the STOP bit of the last byte has been transmitted.
Bit is cleared automatically when Tx FIFO is not empty or the last byte transmission has not completed.
Note: This bit is read only.
bits : 28 - 28 (1 bit)
access : read-only
UART Interrupt Status Register.
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDAIF : Receive Data Available Interrupt Flag (Read Only).
When the number of bytes in the Rx FIFO equals FCR.RFITL then the RDA_IF will be set. If IER.RDA_IEN is enabled, the RDA interrupt will be generated.
Note: This bit is read only and it will be cleared when the number of unread bytes of Rx FIFO drops below the threshold level (RFITL).
bits : 0 - 0 (1 bit)
access : read-only
THREIF : Transmit Holding Register Empty Interrupt Flag (Read Only).
This bit is set when the last data of Tx FIFO is transferred to Transmitter Shift Register. If IER.THRE_IEN is enabled, the THRE interrupt will be generated.
Note: This bit is read only and it will be cleared when writing data into the Tx FIFO.
bits : 1 - 1 (1 bit)
access : read-only
RLSIF : Receive Line Status Interrupt Flag (Read Only).
This bit is set when the Rx receive data has a parity, framing or break error (at least one of, FSR.BIF, FSR.FEF and FSR.PEF, is set). If IER.RLS_IEN is enabled, the RLS interrupt will be generated.
Note: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
bits : 2 - 2 (1 bit)
access : read-only
MODEMIF : MODEM Interrupt Flag (Read Only)
Note: This bit is read only and reset when bit MSR.DCTSF is cleared by a write 1.
bits : 3 - 3 (1 bit)
access : read-only
RXTOIF : Time Out Interrupt Flag (Read Only)
This bit is set when the Rx FIFO is not empty and no activity occurs in the Rx FIFO and the time out counter equal to TOIC. If IER.RXTOIEN is enabled a CPU interrupt request will be generated.
Note: This bit is read only and user can read FIFO to clear it.
bits : 4 - 4 (1 bit)
access : read-only
BUFERRIF : Buffer Error Interrupt Flag (Read Only)
This bit is set when either the Tx or Rx FIFO overflows (FSR.TXOVIF or FSR.RXOVIF is set). When BUFERRIF is set, the serial transfer may be corrupted. If IER.BUFERRIEN is enabled a CPU interrupt request will be generated.
Note: This bit is cleared when both FSR.TXOVIF and FSR.RXOVIF are cleared.
bits : 5 - 5 (1 bit)
access : read-only
RDAINT : Receive Data Available Interrupt Indicator to Interrupt Controller
Logical AND of IER.RDAIEN and RDAIF
bits : 8 - 8 (1 bit)
access : read-write
THREINT : Transmit Holding Register Empty Interrupt Indicator to Interrupt Controller
Logical AND of IER.THREIEN and THREIF
bits : 9 - 9 (1 bit)
access : read-write
RLSINT : Receive Line Status Interrupt Indicator to Interrupt Controller
Logical AND of IER.RLSIEN and RLSIF
bits : 10 - 10 (1 bit)
access : read-write
MODEMINT : MODEM Status Interrupt Indicator to Interrupt
Logical AND of IER.MSIEN and MODEMIF
bits : 11 - 11 (1 bit)
access : read-write
RXTOINT : Time Out Interrupt Indicator to Interrupt Controller
Logical AND of IER.RXTOIEN and RXTOIF
bits : 12 - 12 (1 bit)
access : read-write
BUFERRINT : Buffer Error Interrupt Indicator to Interrupt Controller
Logical AND of IER.BUFERRIEN and BUFERRIF
bits : 13 - 13 (1 bit)
access : read-write
DRLSIF : DMA MODE Receive Line Status Interrupt Flag (Read Only)
This bit is set when the Rx receive data has a parity, framing or break error (at least one of, UART_FIFOSTS.BIF, UART_FIFOSTS.FEF and UART_FIFOSTS.PEF, is set). If UART_INTEN.RLSIEN is enabled, the RLS interrupt will be generated.
NOTE: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
bits : 18 - 18 (1 bit)
access : read-only
DMODIF : DMA MODE MODEM Interrupt Flag (Read Only)
NOTE: This bit is read only and reset when bit UART_MODEMSTS.DCTSF is cleared by a write 1.
bits : 19 - 19 (1 bit)
access : read-only
DRXTOIF : DMA MODE Time Out Interrupt Flag (Read Only)
This bit is set when the Rx FIFO is not empty and no activity occurs in the Rx FIFO and the time out counter equal to TOIC. If UART_INTEN.RXTOIEN is enabled a CPU interrupt request will be generated.
NOTE: This bit is read only and user can read FIFO to clear it.
bits : 20 - 20 (1 bit)
access : read-only
DBERRIF : DMA MODE Buffer Error Interrupt Flag (Read Only)
This bit is set when either the Tx or Rx FIFO overflows (UART_FIFOSTS.TXOVIF or UART_FIFOSTS.RXOVIF is set). When BUFERRIF is set, the serial transfer may be corrupted. If UART_INTEN.BUFERRIEN is enabled a CPU interrupt request will be generated.
NOTE: This bit is cleared when both UART_FIFOSTS.TXOVIF and UART_FIFOSTS.RXOVIF are cleared.
bits : 21 - 21 (1 bit)
access : read-only
DRLSINT : DMA MODE Receive Line Status Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DRLSIF.
bits : 26 - 26 (1 bit)
access : read-write
DMODINT : DMA MODE MODEM Status Interrupt Indicator to Interrupt
Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DMODENIF.
bits : 27 - 27 (1 bit)
access : read-write
DRXTOINT : DMA MODE Time Out Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DRXTOIF.
bits : 28 - 28 (1 bit)
access : read-write
DBERRINT : DMA MODE Buffer Error Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DBERRIF.
bits : 29 - 29 (1 bit)
access : read-write
UART Time Out Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOIC : Time Out Interrupt Comparator
The time out counter resets and starts counting whenever the Rx FIFO receives a new data word. Once the content of time out counter (TOIC) is equal to that of time out interrupt comparator (TOIC), a receiver time out interrupt (RXTOINT) is generated if IER.RXTOIEN is set. A new incoming data word or RX FIFO empty clears RXTOIF. The period of the time out counter is the baud rate.
bits : 0 - 6 (7 bit)
access : read-write
UART Baud Rate Divisor Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRD : Baud Rate Divider. Refer to Table 5.155 for more information.
bits : 0 - 15 (16 bit)
access : read-write
EDIVM1 : Extra Divider for BAUD Rate Mode 1
bits : 24 - 27 (4 bit)
access : read-write
BAUDM0 : BAUD Rate Mode Selection Bit 0
Refer to Table 5.155 for more information.
bits : 28 - 28 (1 bit)
access : read-write
BAUDM1 : BAUD Rate Mode Selection Bit 1
Refer to Table 5.155 for more information.
NOTE: When in IrDA mode, this bit must disabled.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable divider X ( M = 16)
#1 : 1
Enable divider X (M = EDIVM1+1, with EDIVM1 ≥8)
End of enumeration elements list.
UART Interrupt Enable Register.
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDAIEN : Receive Data Available Interrupt Enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask off RDA_INT
#1 : 1
Enable RDA_INT
End of enumeration elements list.
THREIEN : Transmit FIFO Register Empty Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask off THRE_INT
#1 : 1
Enable THRE_INT
End of enumeration elements list.
RLSIEN : Receive Line Status Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask off RLS_INT
#1 : 1
EnableRLS_INT
End of enumeration elements list.
MODEMIEN : Modem Status Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask off MODEM_INT
#1 : 1
Enable MODEM_INT
End of enumeration elements list.
RXTOIEN : Receive Time out Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask off TOUT_INT
#1 : 1
Enable TOUT_INT
End of enumeration elements list.
BUFERRIEN : Buffer Error Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask off BUF_ERR_INT
#1 : 1
Enable IBUF_ERR_INT
End of enumeration elements list.
TOCNTEN : Time-Out Counter Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable Time-out counter
#1 : 1
Enable Time-out counter
End of enumeration elements list.
ATORTSEN : RTS Auto Flow Control Enable
When RTS auto-flow is enabled, if the number of bytes in the Rx FIFO equals FCR.RTS_TRIG_LEVEL, the UART will de-assert the RTS signal.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable RTS auto flow control
#1 : 1
Enable RTS auto flow control
End of enumeration elements list.
ATOCTSEN : CTS Auto Flow Control Enable
When CTS auto-flow is enabled, the UART will send data to external device when CTS input is asserted (UART will not send data to device until CTS is de-asserted).
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable CTS auto flow control
#1 : 1
Enable CTS auto flow control
End of enumeration elements list.
DMATXEN : Transmit DMA Enable
If enabled, the UART will request DMA service when space is available in transmit FIFO.
bits : 14 - 14 (1 bit)
access : read-write
DMARXEN : Receive DMA Enable
If enabled, the UART will request DMA service when data is available in receive FIFO.
bits : 15 - 15 (1 bit)
access : read-write
UART FIFO Control Register.
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXRST : Receive FIFO Reset
When RFR is set, all the bytes in the receive FIFO are cleared and receive internal state machine is reset.
Note: This bit will auto-clear after 3 UART engine clock cycles.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writing 0 to this bit has no effect
#1 : 1
Writing 1 to this bit will reset the receive internal state machine and pointers
End of enumeration elements list.
TXRST : Transmit FIFO Reset
When TFR is set, all the bytes in the transmit FIFO are cleared and transmit internal state machine is reset.
Note: This bit will auto-clear after 3 UART engine clock cycles.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writing 0 to this bit has no effect
#1 : 1
Writing 1 to this bit will reset the transmit internal state machine and pointers
End of enumeration elements list.
RFITL : Receive FIFO Interrupt (RDA_INT) Trigger Level
bits : 4 - 7 (4 bit)
access : read-write
RTSTRGLV : RTS Trigger Level for Auto-flow Control
bits : 16 - 19 (4 bit)
access : read-write
UART Line Control Register.
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WLS : Word Length Select
bits : 0 - 1 (2 bit)
access : read-write
NSB : Number of STOP bits
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
One STOP bit is generated after the transmitted data
#1 : 1
Two STOP bits are generated when 6-, 7- and 8-bit word length is selected One and a half STOP bits are generated in the transmitted data when 5-bit word length is selected
End of enumeration elements list.
PBE : Parity Bit Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Parity bit is not generated (transmit data) or checked (receive data) during transfer
#1 : 1
Parity bit is generated or checked between the last data word bit and stop bit of the serial data
End of enumeration elements list.
EPE : Even Parity Enable
This bit has effect only when PBE (parity bit enable) is set.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Odd number of logic 1's are transmitted or checked in the data word and parity bits
#1 : 1
Even number of logic 1's are transmitted or checked in the data word and parity bits
End of enumeration elements list.
SPE : Stick Parity Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable stick parity
#1 : 1
When bits PBE and SPE are set 'Stick Parity' is enabled. If EPE=0 the parity bit is transmitted and checked as always set, if EPE=1, the parity bit is transmitted and checked as always cleared
End of enumeration elements list.
BCB : Break Control Bit
When this bit is set to logic 1, the serial data output (Tx) is forced to the 'Space' state (logic 0). Normal condition is serial data output is 'Mark' state. This bit acts only on Tx and has no effect on the transmitter logic.
bits : 6 - 6 (1 bit)
access : read-write
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