FMC_ISPCTL (ISPCTL)

FMC_ISPTRG (ISPTRG)

FMC_DFBADR (DFBADR)

FMC_ICPCON (ICPCON)

FMC_ICPRMP (ICPRMP)

FMC_RMPRD (RMPRD)

FMC_ISPADR (ISPADR)

FMC_ISPDAT (ISPDAT)

FMC_ISPCMD (ISPCMD)

ISPEN : ISP Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BS : Boot Select 0: APROM 1: LDROM This bit functions as MCU boot status flag, which can be used to check where MCU booted from. This bit is initialized after power-on reset with the inverse of CBS in Config0 It is not reset for any other reset event.
bits : 1 - 1 (1 bit)
access : read-write

APUWEN : APU Write Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFGUEN : CONFIG Update Enable When enabled, ISP functions can access the CONFIG address space and modify device configuration area.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LDUEN : LDROM Update Enable LDROM update enable bit.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag This bit is set by hardware when a triggered ISP meets any of the following conditions: (1) APROM writes to itself. (2) LDROM writes to itself. (3) Destination address is illegal, such as over an available range. (4) BOD event happen Write 1 to clear.
bits : 6 - 6 (1 bit)
access : read-write

WAIT_CFG : Flash Access Wait State Configuration Before changing WAIT_CFG, ensure HCLK speed is < 25 MHz.
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CACHE_DIS : Cache Disable When set to 1, caching of flash memory reads is disabled.
bits : 21 - 21 (1 bit)
access : read-write

ISPGO : ISP Start Trigger Write 1 to start ISP operation. This will be cleared to 0 by hardware automatically when ISP operation is finished. After triggering an ISP function M0 instruction pipeline should be flushed with a ISB instruction to guarantee data integrity. This is a protected register, user must first follow the unlock sequence see Register Lock Control Register (SYS_REGLCTL)) to gain access.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DFBA : Data Flash Base Address This register reports the data flash starting address. It is a read only register. Data flash size is defined by user configuration, register content is loaded from Config1 when chip is reset.
bits : 0 - 31 (32 bit)
access : read-only

ICP_EN : ICP control enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ICPRMP : ICP ROM MAP control enable When write ICP_EN to 0 , clear ICPRMP_EN to 0 If ICP_EN is 1 and ICPRMP_EN is 1 , ISP can access MAP
bits : 0 - 23 (24 bit)
access : read-write

RMPRD_EN : ROM MAP RD control enable ICP_EN is 1 and ICPRMP_EN is 1 , ISP can access MAP
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPADR : ISP Address Register This is the memory address register that a subsequent ISP command will access. ISP operation are carried out on 32bit words only, consequently ISPARD [1:0] must be 00b for correct ISP operation.
bits : 0 - 31 (32 bit)
access : read-write

ISPDAT : ISP Data Register Write data to this register before an ISP program operation. Read data from this register after an ISP read operation
bits : 0 - 31 (32 bit)
access : read-write

ISPCMD : ISP Command
bits : 0 - 5 (6 bit)
access : read-write