CPD_CTRL (CTRL)

CPD_DECIN (DECIN)

CPD_DECOUT (DECOUT)

CPD_STS (STS)

CPD_ENCIN (ENCIN)

CPD_ENCOUT (ENCOUT)

EN : CPD enable control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE : CPD encode/decode algorithm select
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE : CPD encoder input and decoder output type select
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LAW : CPD A-law / u-law select
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BITRATE : CPD ADPCM bitrate select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ENCRST : Encoder reset register Write 1 to this bit will reset encoder state machine and clear input/output FIFO. This bit will auto change to 0 after reset done.
bits : 8 - 8 (1 bit)
access : read-write

DECRST : Decoder reset register Write 1 to this bit will reset decoder state machine and clear input/output FIFO. This bit will auto change to 0 after reset done.
bits : 9 - 9 (1 bit)
access : read-write

EITH : Encoder input FIFO Threshold Level If the valid data count of the FIFO data buffer is less than or equal to EITH (CPD_CTRL[18:16]) setting, the EITHIF (CPD_STS[3]) will set to 1, else the DITHIF (CPD_STS[3]) will be cleared to 0.
bits : 16 - 18 (3 bit)
access : read-write

EITHIE : Encoder input FIFO Threshold Interrupt
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EOTH : Encoder output FIFO Threshold Level If the valid data count of the FIFO data buffer is larger than or equal to EOTH (CPD_CTRL[22:20]) setting, the EOTHIF (CPD_STS[11]) will set to 1, else the EOTHIF (CPD_STS[11]) will be cleared to 0.
bits : 20 - 22 (3 bit)
access : read-write

EOTHIE : Encoder output FIFO Threshold Interrupt
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DITH : Decoder input FIFO Threshold Level If the valid data count of the FIFO data buffer is less than or equal to DITH (CPD_CTRL[26:24]) setting, the DITHIF (CPD_STS[19]) will set to 1, else the DITHIF (CPD_STS[19]) will be cleared to 0.
bits : 24 - 26 (3 bit)
access : read-write

DITHIE : Decoder input FIFO Threshold Interrupt
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOTH : Decoder output FIFO Threshold Level If the valid data count of the FIFO data buffer is larger than or equal to DOTH (CPD_CTRL[30:28]) setting, the DOTHIF (CPD_STS[27]) will set to 1, else the DOTHIF (CPD_STS[27]) will be cleared to 0.
bits : 28 - 30 (3 bit)
access : read-write

DOTHIE : Decoder output FIFO Threshold Interrupt
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DECIN : CPD decoder input FIFO By writing to this register, decoder input data will be pushed onto the transmit FIFO. CPD will start encoding if this FIFO is not empty.
bits : 0 - 7 (8 bit)
access : write-only

DECOUT : CPD decoder output FIFO Reading this register will return data from decoder output data FIFO.
bits : 0 - 15 (16 bit)
access : read-only

EIF : CPD encoder input FIFO full flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EIE : CPD encoder input FIFO empty flag
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EIOV : CPD encoder input FIFO overflow flag If encoder input FIFO (CPD->CPD_ENC_IN) is full, and an additional data is written to the FIFO, an overflow condition will occur and set this bit to logic 1.
bits : 2 - 2 (1 bit)
access : read-write

EITHIF : CPD encoder input FIFO Threshold Interrupt Status (Read Only)
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

EIFPTR : CPD encoder input FIFO Pointer (Read Only) The FULL (CPD_STS[0]) and FIFOPTR (CPD_STS[7:4]) indicates the field that the valid data count within the encoder input FIFO buffer. The maximum value shown in FIFOPTR is 8. When the using level of encoder input FIFO buffer equal to 8, The FULL (CPD_STS[0]) is set to 1.
bits : 4 - 7 (4 bit)
access : read-only

EOF : CPD encoder output FIFO full flag
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EOE : CPD encoder output FIFO empty flag
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EOOV : CPD encoder output FIFO overflow flag If encoder output FIFO (CPD->CPD_ENC_OUT) is full, and an additional converted data is written to the FIFO, an overflow condition will occur and set this bit to logic 1.
bits : 10 - 10 (1 bit)
access : read-write

EOTHIF : CPD encoder output FIFO Threshold Interrupt Status (Read Only)
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

EOFPTR : CPD encoder output FIFO Pointer (Read Only) The FULL (CPD_STS[8]) and FIFOPTR (CPD_STS[15:12]) indicates the field that the valid data count within the encoder output FIFO buffer. The maximum value shown in FIFOPTR is 8. When the using level of encoder output FIFO buffer equal to 8, The FULL (CPD_STS[8]) is set to 1.
bits : 12 - 15 (4 bit)
access : read-only

DIF : CPD decoder input FIFO full flag
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIE : CPD decoder input FIFO empty flag
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIOV : CPD decoder input FIFO overflow flag If decoder input FIFO (CPD->CPD_DEC_IN) is full, and an additional data is written to the FIFO, an overflow condition will occur and set this bit to logic 1.
bits : 18 - 18 (1 bit)
access : read-write

DITHIF : CPD decoder input FIFO Threshold Interrupt Status (Read Only)
bits : 19 - 19 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DIFPTR : CPD decoder input FIFO Pointer (Read Only) The FULL (CPD_STS[16]) and FIFOPTR (CPD_STS[23:20]) indicates the field that the valid data count within the decoder input FIFO buffer. The maximum value shown in FIFOPTR is 8. When the using level of decoder input FIFO buffer equal to 8, The FULL (CPD_STS[16]) is set to 1.
bits : 20 - 23 (4 bit)
access : read-only

DOF : CPD decoder output FIFO full flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOE : CPD decoder output FIFO empty flag
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOOV : CPD decoder output FIFO overflow flag If decoder output FIFO (CPD->CPD_DEC_OUT) is full, and an additional converted data is written to the FIFO, an overflow condition will occur and set this bit to logic 1.
bits : 26 - 26 (1 bit)
access : read-write

DOTHIF : CPD decoder output FIFO Threshold Interrupt Status (Read Only)
bits : 27 - 27 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DOFPTR : CPD decoder output FIFO Pointer (Read Only) The FULL (CPD_STS[24]) and FIFOPTR (CPD_STS[31:28]) indicates the field that the valid data count within the Decoder output FIFO buffer. The maximum value shown in FIFOPTR is 8. When the using level of decoder output FIFO buffer equal to 8, The FULL (CPD_STS[24]) is set to 1.
bits : 28 - 31 (4 bit)
access : read-only

ENCIN : CPD encoder input FIFO By writing to this register, encoder input data will be pushed onto the transmit FIFO. CPD will start encoding if this FIFO is not empty.
bits : 0 - 15 (16 bit)
access : write-only

ENCOUT : CPD encoder output FIFO Reading this register will return data from encoder output data FIFO.
bits : 0 - 7 (8 bit)
access : read-only