DAC_DAT (DAT)

DAC_PDMACTL (PDMACTL)

DAC_HPVOL (HPVOL)

DAC_ZOHDIV (ZOHDIV)

DAC_CTL1 (CTL1)

DAC_CTL2 (CTL2)

DAC_CTL12 (CTL12)

DAC_CTL3 (CTL3)

DAC_ANA0 (ANA0)

DAC_ANA1 (ANA1)

DAC_CTL0 (CTL0)

DAC_DVOL (DVOL)

DAC_FIFOSTS (FIFOSTS)

FIFO : FIFO Data Input Register DAC contains 32 words (32x32 bit) data buffer for data transmit. A write to this register pushes data onto the FIFO data buffer and increments the write pointer. This is the address that CPU/PDMA writes audio data to. The remaining word number is indicated by FIFOPTR (DAC_FIFOSTS[9:4]).
bits : 0 - 31 (32 bit)
access : read-write

PDMAEN : PDMA Transfer Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HPLVOL : HP Output Left Channel Volume Control Register Note: Volume per step 0.5dB
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HPLM : HP Output Left Channel Mute Control Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HPRVOL : HP Output Right Channel Volume Control Register Note: Volume per step 0.5dB
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HPRM : HP Output Right Channel Mute Control Register
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZOHDIV : Zero Order Hold, Down-sampling Divisor The input sample rate of the DPWM is set by DAC_CLK frequency and the divisor set in this register by the following formula:
bits : 0 - 7 (8 bit)
access : read-write

DACENL : SDMOD enable control for left channel
bits : 0 - 0 (1 bit)
access : read-write

DACENR : SDMOD enable control for right channel
bits : 1 - 1 (1 bit)
access : read-write

SDDITHER : SDMOD dither control Number of bits of dithering on SD Modulator . Each level increments dithering by 1 bit
bits : 2 - 6 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DEMDITHER : DEM dither control Set Probability of DEM Dithering Set probability of first order DEM dithering. Each level increments probability by 1/16
bits : 7 - 10 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSR100 :
bits : 11 - 11 (1 bit)
access : read-write

MIPS500 :
bits : 12 - 12 (1 bit)
access : read-write

DACOSR32 : DAC Oversample Rate 32 Selection
bits : 13 - 13 (1 bit)
access : read-write

DACOSR128 : DAC Oversample Rate 128 Selection
bits : 14 - 14 (1 bit)
access : read-write

DACOSR256 : DAC Oversample Rate 256 Selection
bits : 15 - 15 (1 bit)
access : read-write

DISDEM : Disable DEM (dynamic element matching)
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CICIADJ : Digital filter control ???
bits : 0 - 15 (16 bit)
access : read-write

CICCLPOFF : Digital filter control ???
bits : 16 - 16 (1 bit)
access : read-write

CICGADJ : DAC Output Fine Tuning
bits : 17 - 19 (3 bit)
access : read-write

COFFSEL : Digital filter control ???
bits : 20 - 20 (1 bit)
access : read-write

CLKSYNC : Keep dault
bits : 21 - 21 (1 bit)
access : read-write

SDSEL : Digital filter control ???
bits : 24 - 31 (8 bit)
access : read-write

ACLKSEL : Analog DAC clock source selection
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMCTL : Soft mute control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UNMUTECTL : Power-up soft unmute control
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DACENSM : DACEN Soft Mute enable DAC volume ramping up of a channel on a rising edge of when it turned on.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZCEN : DAC zero cross enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BV1P5 : HP output Volume Control
bits : 0 - 5 (6 bit)
access : read-write

CAPV1P5 : Bypass cap setting
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CKDLYV1P5 : Delay clock choice for DAC
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IBADJV1P5 : BIAS current adjust control
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VREFSEL : DAC Vref select control
bits : 13 - 14 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKINV : Clock input inverse
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ENCLK1 : Left channel DAC clock enable control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ENCLK2 : Right channel DAC clock enable control
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ENDAC1 : Left channel DAC enable control
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ENDAC2 : Right channel DAC enable control
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ENHP1 : Left channel headphone driver block enable control
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ENHP2 : Right channel headphone driver block enable control
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDFLITSM1 : Left channel smooth filter block power down control
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDFLITSM2 : Right channel smooth filter block power down control
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDVBUF1 : Left channel VMID buffer block power down control
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDVBUF2 : Right channel VMID buffer block power down control
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDIBGEN : IBGEN block power down control
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDBIAS :
bits : 13 - 14 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDBIAS2 :
bits : 15 - 16 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDBDAC1 : Left DAC power down control
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDBDAC2 : Right DAC power down control
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VOLEN1 : Left volume enable control
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VOLEN2 : Right volume enable control
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VOLMUTE : Volume mute control
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VROI : VROI Control(for pop control)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEST : Test mode enable
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TESTDACIN : DAC input while in active mode
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIFOWIDTH : FIFO Data Width This bit field is used to define the bit-width of data word and valid bits in register DAC_DAT.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODESEL : Data Control in FIFO
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIFOEN : DAC FIFO enable control
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

THIE : FIFO Threshold Interrupt
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TH : FIFO Threshold Level If the valid data count of the FIFO data buffer is less than or equal to TH (DAC_CTL[16:12]) setting, the THIF (DAC_FIFOSTS[2]) will set to 1, else the THIF (DAC_FIFOSTS[2]) will be cleared to 0.
bits : 12 - 16 (5 bit)
access : read-write

FCLR : FIFO Clear Note 1: To clear the FIFO, need to write FCLR (DAC_CTL[29:28]) to 11b, and can read the EMPTY (DAC_FIFOSTS[1]) bit to make sure that the FIFO has been cleared. Note 2: This field is auto cleared by hardware.
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SWRST : State Machine Software Reset
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKSET : Working Clock Selection
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DACLVOL : DACL Digital Volume Control Register Note: Volume per step 0.5dB
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DACRVOL : DACR Digital Volume Control Register Note: Volume per step 0.5dB
bits : 8 - 15 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FULL : FIFO Full (Read Only)
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

EMPTY : FIFO Empty (Read Only)
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

THIF : FIFO Threshold Interrupt Status (Read Only)
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

FIFOPTR : FIFO Pointer (Read Only) The FULL (DAC_FIFOSTS[0]) and FIFOPTR (DAC_FIFOSTS[9:4]) indicates the field that the valid data count within the DAC FIFO buffer. The maximum value shown in FIFOPTR is 32. When the using level of DAC FIFO buffer equal to 32, The FULL (DAC_FIFOSTS[0]) is set to 1. The minimum value shown in FIFOPTR is 0. When the using level of DAC FIFO buffer equal to 0, The EMPTY (DAC_FIFOSTS[1]) is set to 1.
bits : 4 - 9 (6 bit)
access : read-only

FIFOFAIL : FIFO TEST Failed flag
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIFOEND : FIFO TEST Finish flag
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RAMFAIL : RAM TEST Failed Flag(internal use)
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RAMEND : RAM TEST Finish Flag(internal use)
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIFOTEST : Enable FIFO test mode
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BISTEN : BIST Enable(internal use) Bit[30]: Interpolator RAM BIST Mode control Bit[29]: FIFO BIST Mode control Note: FIFO can be testing by Cortex-M0
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.