Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x28 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
SD ADC FIFO Data Read Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : Delta-Sigma ADC DATA FIFO Read
A read of this register will read data from the audio FIFO and increment the read pointer. A read past empty will repeat the last data. Can be used with SDADC_FIFOSTS.THIF interrupt to determine if valid data is present in FIFO.
Data width can be selected by SDADC_CTL.FIFO_BITS
bits : 0 - 31 (32 bit)
access : read-only
SD ADC FIFO Status Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FULL : FIFO Full
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
FIFO is not full
#1 : 1
FIFO is full
End of enumeration elements list.
EMPTY : FIFO Empty
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
FIFO is not empty
#1 : 1
FIFO is empty
End of enumeration elements list.
THIF : ADC FIFO Threshold Interrupt Status (Read Only)
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
The valid data count within the transmit FIFO buffer is less than to the setting value of FIFOTH
#1 : 1
The valid data count within the ADC FIFO buffer is larger than or equal the setting value of FIFOTH
End of enumeration elements list.
POINTER : ADC FIFO Pointer (Read Only)
The FULL bit and FIFOPOINTER[4:0] indicates the field that the valid data count within the SDADC FIFO buffer.
The Maximum value shown in FIFOPOINTER is 31. When the using level of SDADC FIFO Buffer equal to 32, The FULL bit is set to 1.
bits : 4 - 8 (5 bit)
access : read-only
BISTEN : SDADC BIST Enable(internal use)
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable BIST testing
#1 : 1
Enable BIST testing
End of enumeration elements list.
BISTFAIL : SDADC BIST TEST Failed Flag(internal use)
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
memory bist pass, if set BISTEN to 1 and BISTEND is 1
#1 : 1
memory bist fail, if set BISTEN to 1 and BISTEND is 1
End of enumeration elements list.
BISTEND : SDADC BIST TEST Finish Flag(internal use)
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
is not finishing, if set BISTEN to 1
#1 : 1
finish, if set BISTEN to 1
End of enumeration elements list.
FIFOTEST : Enable FIFO test mode
Internal use
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable ADC FIFO testing
#1 : 1
Enable ADC FIFO testing ADC FIFO can be testing by Cortex-M0
End of enumeration elements list.
SD ADC PDMA Control Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMAEN : Enable SDADC PDMA Receive Channel
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable SDADC PDMA
#1 : 1
Enable SDADC PDMA
End of enumeration elements list.
SD ADC Comparator 0 Control Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMPEN : Compare Enable
Set this bit to 1 to enable compare CMPDAT with FIFO data output.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable compare
#1 : 1
Enable compare
End of enumeration elements list.
CMPIE : Compare Interrupt Enable
If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, if CMPIE is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable compare function interrupt
#1 : 1
Enable compare function interrupt
End of enumeration elements list.
CMPCOND : Compare Condition
Note: When the internal counter reaches the value (CMPMATCNT +1), the CMPF bit will be set.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set the compare condition that result is less than CMPD
#1 : 1
Set the compare condition that result is greater or equal to CMPD
End of enumeration elements list.
CMPF : Compare Flag
When the conversion result meets condition in ADCMPR0 this bit is set to 1. It is cleared by writing 1 to self.
bits : 3 - 3 (1 bit)
access : read-write
CMPMATCNT : Compare Match Count
When the A/D FIFO result matches the compare condition defined by CMPCOND, the internal match counter will increase by 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
bits : 4 - 7 (4 bit)
access : read-write
CMPD : Comparison Data
23 bit value to compare to FIFO output word.
bits : 8 - 30 (23 bit)
access : read-write
CMPOEN : Compare Match output FIFO zero
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
FIFO data keep original one
#1 : 1
compare match then FIFO out zero
End of enumeration elements list.
SD ADC Comparator 1 Control Register
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMPEN : Compare Enable
Set this bit to 1 to enable compare CMPDAT with FIFO data output.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable compare
#1 : 1
Enable compare
End of enumeration elements list.
CMPIE : Compare Interrupt Enable
If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, if CMPIE is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable compare function interrupt
#1 : 1
Enable compare function interrupt
End of enumeration elements list.
CMPCOND : Compare Condition
Note: When the internal counter reaches the value (CMPMATCNT +1), the CMPF bit will be set.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set the compare condition that result is less than CMPD
#1 : 1
Set the compare condition that result is greater or equal to CMPD
End of enumeration elements list.
CMPF : Compare Flag
When the conversion result meets condition in ADCMPR0 this bit is set to 1. It is cleared by writing 1 to self.
bits : 3 - 3 (1 bit)
access : read-write
CMPMATCNT : Compare Match Count
When the A/D FIFO result matches the compare condition defined by CMPCOND, the internal match counter will increase by 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
bits : 4 - 7 (4 bit)
access : read-write
CMPD : Comparison Data
23 bit value to compare to FIFO output word.
bits : 8 - 30 (23 bit)
access : read-write
CMPOEN : Compare Match output FIFO zero
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
FIFO data keep original one
#1 : 1
compare match then FIFO out zero
End of enumeration elements list.
SD ADC Analog Block Control Register 0
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD : SDADC Power Down
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SDADC power on
#1 : 1
SDADC power off
End of enumeration elements list.
BIAS : SDADC Bias Current Selection
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
#00 : 0
1.35
#01 : 1
1
#10 : 2
0.67
#11 : 3
1.68
End of enumeration elements list.
VREF : SDADC Chopper in Reference Buffer
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
chopper off
#1 : 1
chopper on
End of enumeration elements list.
PU : Power up PGA
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable
End of enumeration elements list.
MUTE : PGA Mute control signal
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable
End of enumeration elements list.
MODE : PGA mode selection
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : 0
Disable
1 : 1
Enable
End of enumeration elements list.
IBCTR : Trim PGA Current
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0 : 0
default
End of enumeration elements list.
IBLOOP : Trim PGA current
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#1 : 1
default
End of enumeration elements list.
CMLCK : PGA Common mode Threshold lock adjust enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable
#1 : 1
Disable
End of enumeration elements list.
CMLCKADJ :
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
0.98 (default)
#01 : 1
0.96
#10 : 2
1.01
#11 : 3
1.04
End of enumeration elements list.
CLASSA : Enable PGA Class A mode of operation
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Class AB
#1 : 1
Class A (default)
End of enumeration elements list.
TRIMOBC : Trim PGA current in output driver
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable (default)
End of enumeration elements list.
CHOPF : SDADC Chopper Frequency in fixed chop mode
bits : 23 - 24 (2 bit)
access : read-write
Enumeration:
#00 : 0
Fs/2 (default)
#01 : 1
Fs/4
#10 : 2
Fs/8
#11 : 3
Fs/16
End of enumeration elements list.
CHOPCKPH : SDADC Chopper Clock phase selection
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
chopper transition after falling edge of SD_CLK (default)
#1 : 1
chopper transition after rising edge of SD_CLK
End of enumeration elements list.
CHOPFIX : SDADC Chopper Fixed Frequency
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
dither chopper frequency (default)
#1 : 1
choose fixed frequency
End of enumeration elements list.
CHOPORD : SDADC Chopper Order
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
1st order dithering of chopper frequency (default)
#1 : 1
2nd order dithering of chopper frequency
End of enumeration elements list.
CHOPPH : SDADC chopper phase
When chopper is off:
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
chopper switches in default state
#1 : 1
invert chopper switches
End of enumeration elements list.
CHOPEN : SDADC chopper enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable (default)
#1 : 1
enable
End of enumeration elements list.
SD ADC Analog Block Control Register 1
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMLCKADJ : Default 00'b
bits : 0 - 1 (2 bit)
access : read-write
CMLCKEN :
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
#1 : 1
(default)
End of enumeration elements list.
CLASSAEN :
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
(default)
#1 : 1
End of enumeration elements list.
DISCHRG : BST Charge inputs selected by ACDC[1:0] to VMID
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
IBCTRCODE : Trim Current of BST
Keep default 000'b
bits : 5 - 7 (3 bit)
access : read-write
IBLOOPCTR : Trim Current of BST
Keep default 0'b
bits : 8 - 8 (1 bit)
access : read-write
BSTMODE : BST mode selection
bits : 9 - 12 (4 bit)
access : read-write
Enumeration:
0 : 0
Disable
1 : 1
Enable
End of enumeration elements list.
BSTMUTE : Boost mute
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Unmute
#1 : 1
Mute(default)
End of enumeration elements list.
BSTPUP : Boost power on
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Power off(default)
#1 : 1
Power on
End of enumeration elements list.
BSTTRIMOBC : Trim Current: BST driver
Keep default 0'b
bits : 15 - 15 (1 bit)
access : read-write
ACDC : BST ACDC Control register
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Default
End of enumeration elements list.
SD ADC Analog Block Control Register 2
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAINSET : Select The PGA Gain Setting
From -12dB to 34.5dB in 1.5dB step size. 0x00 is lowest gain setting at -12dB and 0x1F is largest gain at 34.5dB.(0x8 is 0 dB)
bits : 0 - 4 (5 bit)
access : read-write
SD ADC Enable Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDADCEN : SDADC Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion stopped and ADC is reset including FIFO pointers
#1 : 1
ADC Conversion enabled
End of enumeration elements list.
DINEDGE : SDADC data input clock edge selection
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADC clock negetive edge latch
#1 : 1
ADC clock positive edge latch
End of enumeration elements list.
DINBYPS : SDADC data input bypass (internal debug)
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
normal mode
#1 : 1
analog 5bits to FIFO for testing
End of enumeration elements list.
SD ADC Clock Divider Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKDIV : SDADC Clock Divider
This register determines the clock division ration between the incoming SD_CLK and the Sigma-Delta sampling clock of the ADC. This together with the over-sampling ratio (OSR) determines the audio sample rate of the converter. CLKDIV should be set to give a SD_CLK frequency in the range of 1.024-6.144MHz.
CLKDIV must be greater than or equal 4.
bits : 0 - 7 (8 bit)
access : read-write
SD ADC Control Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSRATE : Down Sampling Ratio
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
reserved
#01 : 1
down sample X 16
#10 : 2
down sample X 32
#11 : 3
down sample X 64 when SPDS = 0 . 11 = down sample X 62.5 when SPDS = 1
End of enumeration elements list.
FIFOBITS : FIFO Data Bits Selection
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
32 bits
#01 : 1
16 bits
#10 : 2
8 bits
#11 : 3
24 bits
End of enumeration elements list.
FIFOTH : FIFO Threshold:
Determines at what level the ADC FIFO will generate a interrupt.
Interrupt will be generated when number of words present in ADC FIFO is >
FIFOTH.
bits : 4 - 7 (4 bit)
access : read-write
FIFOTHIE : FIFO Threshold Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable interrupt whenever FIFO level exceeds that set in FIFOTH
#1 : 1
enable interrupt whenever FIFO level exceeds that set in FIFOTH
End of enumeration elements list.
SPDS : Specific down sampling ratio control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable specific DS rate
#1 : 1
Enable specific DS rate
End of enumeration elements list.
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