\n
address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x4C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x80 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xC0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
ISP Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPEN : ISP Enable Bit (Write Protected)
ISP function enable bit. Set this bit to enable ISP function.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
ISP function Disabled
#1 : 1
ISP function Enabled
End of enumeration elements list.
BS : Boot Select (Write Protected)
Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in CONFIG0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Boot from APROM
#1 : 1
Boot from LDROM
End of enumeration elements list.
APUEN : APROM Update Enable Bit (Write Protected)
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
APROM cannot be updated when the chip runs in APROM
#1 : 1
APROM can be updated when the chip runs in APROM
End of enumeration elements list.
CFGUEN : Config-Bits Update By ISP Enable Bit(Write Protected)
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
ISP Disabled to update config-bits
#1 : 1
ISP Enabled to update config-bits
End of enumeration elements list.
LDUEN : LDROM Update Enable Bit (Write Protected)
LDROM update enable bit.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
LDROM cannot be updated
#1 : 1
LDROM can be updated
End of enumeration elements list.
ISPFF : ISP Fail Flag (Write Protected)
This bit is set by hardware when a triggered ISP meets any of the following conditions:
(1) APROM writes to itself if APUEN is set to 0.
(2) LDROM writes to itself if LDUEN is set to 0.
(3) CONFIG is erased/programmed if CFGUEN is set to 0.
(4) Destination address is illegal, such as over an available range.
Note: This bit needs to be cleared by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-write
ISP Trigger Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPGO : ISP Start Trigger (Write Protected)
Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
ISP operation is finished
#1 : 1
ISP is progressed
End of enumeration elements list.
Data Flash Base Address
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DFBA : Data Flash Base Address
This register indicates Data Flash start address. It is a read only register.
The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1
bits : 0 - 31 (32 bit)
access : read-only
ISP Address Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPADDR : ISP Address
The I94100 series is equipped with an embedded . ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. ISPADDR[2:0] must be kept 000 for ISP 64-bit operation. ISPADDR[3:0] must be kept 0000 for ISP multi-word operation.
For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 4 Kbytes alignment is necessary for CRC32 checksum calculation.
For FLASH 32-bit Program, ISP address needs word alignment (4-byte). For FLASH 64-bit Program, ISP address needs double word alignment (8-byte). For FLASH multi-word Program, ISP address needs four word alignment (16-byte).
bits : 0 - 31 (32 bit)
access : read-write
ISP Status Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ISPBUSY : ISP Busy Flag (Read Only)
Note: The reset value of FMC_ISPSTS[3:0] is 1xx0b.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
ISP operation is finished
#1 : 1
ISP is progressed
End of enumeration elements list.
CBS : Chip Boot Selection Mode (Read Only)
This CBS field is just a copy of flash controller user configuration register CBS (CONFIG0 [7:6]).
Note: The reset value of FMC_ISPSTS[3:0] is 1xx0b.
bits : 1 - 2 (2 bit)
access : read-only
FCYCDIS : Flash Access Cycle Auto-tuning Disabled Flag (Read Only)
This bit is set if flash access cycle auto-tunning function is disabled. The auto-tunning function is disabled by FADIS(FMC_CYCCTL[8]) or HIRC clock is not ready.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Flash access cycle auto-tuning is Enabled
#1 : 1
Flash access cyle auto-tuning is Disabled
End of enumeration elements list.
PGFF : Flash Program with Fast Verification Flag (Read Only)
This bit is set if data is mismatched at ISP programming verification. This bit is cleared by performing ISP flash erase or ISP read CID operation
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Flash Program is success
#1 : 1
Flash Program has failed. Program data is different with data in the flash memory
End of enumeration elements list.
ISPFF : ISP Fail Flag (Read Only)
This bit is set by hardware when a triggered ISP meets any of the following conditions:
(1) APROM writes to itself if APUEN is set to 0.
(2) LDROM writes to itself if LDUEN is set to 0.
(3) CONFIG is erased/programmed if CFGUEN is set to 0.
(4) Destination address is illegal, such as over an available range.
bits : 6 - 6 (1 bit)
access : read-only
ALLONE : Flash All-one Verification Flag
This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after Run Flash All-One Verification complete this bit also can be clear by writing 1
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
All of flash bits are 1 after Run Flash All-One Verification complete
#1 : 1
Flash bits are not all 1 after Run Flash All-One Verification complete
End of enumeration elements list.
VECMAP : Vector Page Mapping Address (Read Only)
The current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[14:0], 9'h000} ~ {VECMAP[14:0], 9'h1FF}
bits : 9 - 23 (15 bit)
access : read-only
Flash Access Cycle Control Register
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CYCLE : Flash Access Cycle Control (Write Protect)
This register is updated automaticly by hardware while FCYCDIS (FMC_ISPSTS[4]) is 0, and updated by software while auto-tuning function disabled ( FADIS (FMC_CYCCTL[8]) is 1)
The optimized HCLK working frequency range is >192 MHz
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
CPU access with zero wait cycle flash access cycle is 1
#0001 : 1
CPU access with one wait cycle if cache miss flash access cylcle is 1
#0010 : 2
CPU access wtih two wait cycles if cahce miss flash access cycle is 2
#0011 : 3
CPU access with three wait cycles if cache miss flash access cylcle is 3
#0100 : 4
CPU access with four wait cycles if cahce miss flash access cycle is 4
#0101 : 5
CPU access with five wait cycles if cache miss flash access cylcle is 5
#0110 : 6
CPU access with six wait cycles if cahce miss flash access cycle is 6
#0111 : 7
CPU access with seven wait cycles if cahce miss flash access cycle is 7
#1000 : 8
CPU access with eight wait cycles if cache miss flash access cylcle is 8
End of enumeration elements list.
FADIS : Flash Access Cycle Auto-tuning Disabled Control (Write Protect)
Set this bit to disable flash access cycle auto-tuning function
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash access cycle auto-tuning is enabled
#1 : 1
Flash access cycle auto-tuning is disabled
End of enumeration elements list.
ISP Data Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPDAT : ISP Data
Write data to this register before ISP program operation.
Read data from this register after ISP read operation.
bits : 0 - 31 (32 bit)
access : read-write
ISP Multi-word Program Data0 Register
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPDAT0 : ISP Data 0
This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data.
bits : 0 - 31 (32 bit)
access : read-write
ISP Multi-word Program Data1 Register
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPDAT1 : ISP Data 1
This register is the second 32-bit data for 64-bit/multi-word programming.
bits : 0 - 31 (32 bit)
access : read-write
ISP Multi-word Program Data2 Register
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPDAT2 : ISP Data 2
This register is the third 32-bit data for multi-word programming.
bits : 0 - 31 (32 bit)
access : read-write
ISP Multi-word Program Data3 Register
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPDAT3 : ISP Data 3
This register is the fourth 32-bit data for multi-word programming.
bits : 0 - 31 (32 bit)
access : read-write
ISP Command Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : ISP Command
ISP command table is shown below:
The other commands are invalid.
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x00 : 0
FLASH Read
0x04 : 4
Read Unique ID
0x08 : 8
Read Flash All-One Result
0x0b : 11
Read Company ID
0x0c : 12
Read Device ID
0x0d : 13
Read Checksum
0x21 : 33
FLASH 32-bit Program
0x22 : 34
FLASH Page Erase. Erase page
0x23 : 35
FLASH Bank Erase. Erase all pages of APROM
0x25 : 37
FLASH Block Erase. Erase four pages alignment of APROM
0x27 : 39
FLASH Multi-Word Program
0x28 : 40
Run Flash All-One Verification
0x2d : 45
Run Checksum Calculation
0x2e : 46
Vector Remap
0x40 : 64
FLASH 64-bit Read
0x61 : 97
FLASH 64-bit Program
End of enumeration elements list.
ISP Multi-word Program Status Register
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MPBUSY : ISP Multi-word Program Busy Flag (Read Only)
Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.
This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
ISP Multi-Word program operation is finished
#1 : 1
ISP Multi-Word program operation is progressed
End of enumeration elements list.
PPGO : ISP Multi-program Status (Read Only)
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
ISP multi-word program operation is not active
#1 : 1
ISP multi-word program operation is in progress
End of enumeration elements list.
ISPFF : ISP Fail Flag (Read Only)
This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:
(1) APROM writes to itself if APUEN is set to 0.
(2) LDROM writes to itself if LDUEN is set to 0.
(3) CONFIG is erased/programmed if CFGUEN is set to 0.
(4) Page Erase command at LOCK mode with ICE connection
(5) Erase or Program command at brown-out detected
(6) Destination address is illegal, such as over an available range.
(7) Invalid ISP commands
bits : 2 - 2 (1 bit)
access : read-only
D0 : ISP DATA 0 Flag (Read Only)
This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
FMC_MPDAT0 register is empty, or program to flash complete
#1 : 1
FMC_MPDAT0 register has been written, and not program to flash complete
End of enumeration elements list.
D1 : ISP DATA 1 Flag (Read Only)
This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
FMC_MPDAT1 register is empty, or program to flash complete
#1 : 1
FMC_MPDAT1 register has been written, and not program to flash complete
End of enumeration elements list.
D2 : ISP DATA 2 Flag (Read Only)
This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
FMC_MPDAT2 register is empty, or program to flash complete
#1 : 1
FMC_MPDAT2 register has been written, and not program to flash complete
End of enumeration elements list.
D3 : ISP DATA 3 Flag (Read Only)
This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
FMC_MPDAT3 register is empty, or program to flash complete
#1 : 1
FMC_MPDAT3 register has been written, and not program to flash complete
End of enumeration elements list.
ISP Multi-word Program Address Status Register
address_offset : 0xC4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MPADDR : ISP Multi-word Program Address
MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.
MPADDR will keep the final ISP address when ISP multi-word program is complete.
bits : 0 - 31 (32 bit)
access : read-only
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