\n
address_offset : 0x0 Bytes (0x0)
size : 0x140 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x400 Bytes (0x0)
size : 0x44 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x460 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x480 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x500 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection :
PDMA_REQSEL12_15 (REQSEL12_15)
PDMA_DSCT10_NEXT (DSCT10_NEXT)
PDMA_DSCT11_NEXT (DSCT11_NEXT)
PDMA_DSCT12_NEXT (DSCT12_NEXT)
PDMA_DSCT13_NEXT (DSCT13_NEXT)
PDMA_DSCT14_NEXT (DSCT14_NEXT)
PDMA_DSCT15_NEXT (DSCT15_NEXT)
Descriptor Table Control Register of PDMA Channel 0
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPMODE : PDMA Operation Mode Selection
Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically
#01 : 1
Basic mode: The descriptor table only has one task. When this task is finished, the PDMA_INTSTS[n] will be asserted
#10 : 2
Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register PDMA controller will ignore this task, then load the next task to execute
#11 : 3
Reserved. Do not use
End of enumeration elements list.
TXTYPE : Transfer Type
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Burst transfer type
#1 : 1
Single transfer type
End of enumeration elements list.
BURSIZE : Burst Size
This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.
Note: This field is only useful in burst transfer type.
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 0
128 Transfers
#001 : 1
64 Transfers
#010 : 2
32 Transfers
#011 : 3
16 Transfers
#100 : 4
8 Transfers
#101 : 5
4 Transfers
#110 : 6
2 Transfers
#111 : 7
1 Transfers
End of enumeration elements list.
TBINTDIS : Table Interrupt Disable Bit
This field can be used to decide whether to enable table interrupt or not. This bit is only used for scatter-gather mode. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Table interrupt Enabled
#1 : 1
Table interrupt Disabled
End of enumeration elements list.
SAINC : Source Address Increment
This field is used to set the source address increment size.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#11 : 3
No increment (fixed address)
End of enumeration elements list.
DAINC : Destination Address Increment
This field is used to set the destination address increment size.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#11 : 3
No increment (fixed address)
End of enumeration elements list.
TXWIDTH : Transfer Width Selection
This field is used for transfer width.
Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
One byte (8 bit) is transferred for every operation
#01 : 1
One half-word (16 bit) is transferred for every operation
#10 : 2
One word (32-bit) is transferred for every operation
#11 : 3
Reserved. Do not use
End of enumeration elements list.
STRIDEEN : Stride Mode Enable Bit
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stride transfer mode Disabled
#1 : 1
Stride transfer mode Enabled
End of enumeration elements list.
TXCNT : Transfer Count
The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1) The maximum transfer count is 65536, every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
Note: When PDMA finish each transfer data, this field will be decrease immediately.
bits : 16 - 31 (16 bit)
access : read-write
Descriptor Table Control Register of PDMA Channel 1
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel 0
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CURADDR : PDMA Current Description Address Register (Read Only)
This field indicates a 32-bit current external description address of PDMA controller.
Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address.
bits : 0 - 31 (32 bit)
access : read-only
Current Scatter-gather Descriptor Table Address of PDMA Channel 1
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel 2
address_offset : 0x108 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel 3
address_offset : 0x10C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel 4
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel 5
address_offset : 0x114 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel 6
address_offset : 0x118 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel 7
address_offset : 0x11C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel 8
address_offset : 0x120 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel 9
address_offset : 0x124 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel 10
address_offset : 0x128 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel 11
address_offset : 0x12C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel 12
address_offset : 0x130 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel 13
address_offset : 0x134 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel 14
address_offset : 0x138 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel 15
address_offset : 0x13C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel 1
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 1
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Descriptor Table Control Register of PDMA Channel 2
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel 2
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel 2
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 2
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Descriptor Table Control Register of PDMA Channel 3
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel 3
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel 3
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 3
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel 0
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SA : PDMA Transfer Source Address Register
This field indicates a 32-bit source address of PDMA controller.
bits : 0 - 31 (32 bit)
access : read-write
Descriptor Table Control Register of PDMA Channel 4
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMA Channel Control Register
address_offset : 0x400 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN0 : PDMA Channel 0 Enable Bit
Set this bit to 1 to enable PDMA channel 0 operation. Channel 0 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel 0 Disabled
#1 : 1
PDMA Channel 0 Enabled
End of enumeration elements list.
CHEN1 : PDMA Channel 1 Enable Bit
Set this bit to 1 to enable PDMA channel 1 operation. Channel 1 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel 1 Disabled
#1 : 1
PDMA Channel 1 Enabled
End of enumeration elements list.
CHEN2 : PDMA Channel 2 Enable Bit
Set this bit to 1 to enable PDMA channel 2 operation. Channel 2 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel 2 Disabled
#1 : 1
PDMA Channel 2 Enabled
End of enumeration elements list.
CHEN3 : PDMA Channel 3 Enable Bit
Set this bit to 1 to enable PDMA channel 3 operation. Channel 3 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel 3 Disabled
#1 : 1
PDMA Channel 3 Enabled
End of enumeration elements list.
CHEN4 : PDMA Channel 4 Enable Bit
Set this bit to 1 to enable PDMA channel 4 operation. Channel 4 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel 4 Disabled
#1 : 1
PDMA Channel 4 Enabled
End of enumeration elements list.
CHEN5 : PDMA Channel 5 Enable Bit
Set this bit to 1 to enable PDMA channel 5 operation. Channel 5 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel 5 Disabled
#1 : 1
PDMA Channel 5 Enabled
End of enumeration elements list.
CHEN6 : PDMA Channel 6 Enable Bit
Set this bit to 1 to enable PDMA channel 6 operation. Channel 6 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel 6 Disabled
#1 : 1
PDMA Channel 6 Enabled
End of enumeration elements list.
CHEN7 : PDMA Channel 7 Enable Bit
Set this bit to 1 to enable PDMA channel 7 operation. Channel 7 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel 7 Disabled
#1 : 1
PDMA Channel 7 Enabled
End of enumeration elements list.
CHEN8 : PDMA Channel 8 Enable Bit
Set this bit to 1 to enable PDMA channel 8 operation. Channel 8 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel 8 Disabled
#1 : 1
PDMA Channel 8 Enabled
End of enumeration elements list.
CHEN9 : PDMA Channel 9 Enable Bit
Set this bit to 1 to enable PDMA channel 9 operation. Channel 9 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 9 Disabled
#1 : 1
PDMA channel 9 Enabled
End of enumeration elements list.
CHEN10 : PDMA Channel 10 Enable Bit
Set this bit to 1 to enable PDMA channel 10 operation. Channel 10 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel 10 Disabled
#1 : 1
PDMA Channel 10 Enabled
End of enumeration elements list.
CHEN11 : PDMA Channel 11 Enable Bit
Set this bit to 1 to enable PDMA channel 11 operation. Channel 11 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel 11 Disabled
#1 : 1
PDMA Channel 11 Enabled
End of enumeration elements list.
CHEN12 : PDMA Channel 12 Enable Bit
Set this bit to 1 to enable PDMA channel 12 operation. Channel 12 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel 12 Disabled
#1 : 1
PDMA Channel 12 Enabled
End of enumeration elements list.
CHEN13 : PDMA Channel 13 Enable Bit
Set this bit to 1 to enable PDMA channel 13 operation. Channel 13 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel 13 Disabled
#1 : 1
PDMA Channel 13 Enabled
End of enumeration elements list.
CHEN14 : PDMA Channel 14 Enable Bit
Set this bit to 1 to enable PDMA channel 14 operation. Channel 14 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel 14 Disabled
#1 : 1
PDMA Channel 14 Enabled
End of enumeration elements list.
CHEN15 : PDMA Channel 15 Enable Bit
Set this bit to 1 to enable PDMA channel 15 operation. Channel 15 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel 15 Disabled
#1 : 1
PDMA Channel 15 Enabled
End of enumeration elements list.
PDMA Transfer Stop Control Register
address_offset : 0x404 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
STOP0 : PDMA Channel 0 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 0 transfer. When user sets STOP0 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN0 (PDMA_CHCTL [0]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Stop PDMA channel 0 transfer
End of enumeration elements list.
STOP1 : PDMA Channel 1 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 1 transfer. When user sets STOP1 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN1 (PDMA_CHCTL [1]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 1 - 1 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Stop PDMA channel 1 transfer
End of enumeration elements list.
STOP2 : PDMA Channel 2 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 2 transfer. When user sets STOP2 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN2 (PDMA_CHCTL [2]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 2 - 2 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Stop PDMA channel 2 transfer
End of enumeration elements list.
STOP3 : PDMA Channel 3 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 3 transfer. When user sets STOP3 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN3 (PDMA_CHCTL [3]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 3 - 3 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Stop PDMA channel 3 transfer
End of enumeration elements list.
STOP4 : PDMA Channel 4 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 4 transfer. When user sets STOP4 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN4 (PDMA_CHCTL [4]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 4 - 4 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Stop PDMA channel 4 transfer
End of enumeration elements list.
STOP5 : PDMA Channel 5 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 5 transfer. When user sets STOP5 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN5 (PDMA_CHCTL [5]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 5 - 5 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Stop PDMA channel 5 transfer
End of enumeration elements list.
STOP6 : PDMA Channel 6 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 6 transfer. When user sets STOP6 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN6 (PDMA_CHCTL [6]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 6 - 6 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Stop PDMA channel 6 transfer
End of enumeration elements list.
STOP7 : PDMA Channel 7 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 7 transfer. When user sets STOP7 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN7 (PDMA_CHCTL [7]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 7 - 7 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Stop PDMA channel 7 transfer
End of enumeration elements list.
STOP8 : PDMA Channel 8 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 8 transfer. When user sets STOP8 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN8 (PDMA_CHCTL [8]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 8 - 8 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Stop PDMA channel 8 transfer
End of enumeration elements list.
STOP9 : PDMA Channel 9 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 9 transfer. When user sets STOP9 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN9 (PDMA_CHCTL [9]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 9 - 9 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Stop PDMA channel 9 transfer
End of enumeration elements list.
STOP10 : PDMA Channel 10 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 10 transfer. When user sets STOP10 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN10 (PDMA_CHCTL [10]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 10 - 10 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Stop PDMA channel 10 transfer
End of enumeration elements list.
STOP11 : PDMA Channel 11 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 11 transfer. When user sets STOP11 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN11 (PDMA_CHCTL [11]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 11 - 11 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Stop PDMA channel 11 transfer
End of enumeration elements list.
STOP12 : PDMA Channel 12 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 12 transfer. When user sets STOP12 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN12 (PDMA_CHCTL [12]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 12 - 12 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Stop PDMA channel 12 transfer
End of enumeration elements list.
STOP13 : PDMA Channel 13 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 13 transfer. When user sets STOP13 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN13 (PDMA_CHCTL [13]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 13 - 13 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Stop PDMA channel 13 transfer
End of enumeration elements list.
STOP14 : PDMA Channel 14 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 14 transfer. When user sets STOP14 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN14 (PDMA_CHCTL [14]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 14 - 14 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Stop PDMA channel 14 transfer
End of enumeration elements list.
STOP15 : PDMA Channel 15 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 15 transfer. When user sets STOP15 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN15 (PDMA_CHCTL [15]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 15 - 15 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Stop PDMA channel 15 transfer
End of enumeration elements list.
PDMA Software Request Register
address_offset : 0x408 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWREQ0 : PDMA Channel 0 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 0.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
#0 : 0
PDMA Channel 0 no effect
#1 : 1
PDMA Channel 0 generate a software request
End of enumeration elements list.
SWREQ1 : PDMA Channel 1 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 1.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 1 - 1 (1 bit)
access : write-only
Enumeration:
#0 : 0
PDMA Channel 1 no effect
#1 : 1
PDMA Channel 1 generate a software request
End of enumeration elements list.
SWREQ2 : PDMA Channel 2 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 2.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 2 - 2 (1 bit)
access : write-only
Enumeration:
#0 : 0
PDMA Channel 2 no effect
#1 : 1
PDMA Channel 2 generate a software request
End of enumeration elements list.
SWREQ3 : PDMA Channel 3 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 3.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 3 - 3 (1 bit)
access : write-only
Enumeration:
#0 : 0
PDMA Channel 3 no effect
#1 : 1
PDMA Channel 3 generate a software request
End of enumeration elements list.
SWREQ4 : PDMA Channel 4 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 4.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 4 - 4 (1 bit)
access : write-only
Enumeration:
#0 : 0
PDMA Channel 4 no effect
#1 : 1
PDMA Channel 4 generate a software request
End of enumeration elements list.
SWREQ5 : PDMA Channel 5 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 5.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 5 - 5 (1 bit)
access : write-only
Enumeration:
#0 : 0
PDMA Channel 5 no effect
#1 : 1
PDMA Channel 5 generate a software request
End of enumeration elements list.
SWREQ6 : PDMA Channel 6 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 6.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 6 - 6 (1 bit)
access : write-only
Enumeration:
#0 : 0
PDMA Channel 6 no effect
#1 : 1
PDMA Channel 6 generate a software request
End of enumeration elements list.
SWREQ7 : PDMA Channel 7 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 7.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 7 - 7 (1 bit)
access : write-only
Enumeration:
#0 : 0
PDMA Channel 7 no effect
#1 : 1
PDMA Channel 7 generate a software request
End of enumeration elements list.
SWREQ8 : PDMA Channel 8 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 8.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 8 - 8 (1 bit)
access : write-only
Enumeration:
#0 : 0
PDMA Channel 8 no effect
#1 : 1
PDMA Channel 8 generate a software request
End of enumeration elements list.
SWREQ9 : PDMA Channel 9 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 9.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 9 - 9 (1 bit)
access : write-only
Enumeration:
#0 : 0
PDMA Channel 9 no effect
#1 : 1
PDMA Channel 9 generate a software request
End of enumeration elements list.
SWREQ10 : PDMA Channel 10 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 10.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 10 - 10 (1 bit)
access : write-only
Enumeration:
#0 : 0
PDMA Channel 10 no effect
#1 : 1
PDMA Channel 10 generate a software request
End of enumeration elements list.
SWREQ11 : PDMA Channel 11 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 11.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 11 - 11 (1 bit)
access : write-only
Enumeration:
#0 : 0
PDMA Channel 11 no effect
#1 : 1
PDMA Channel 11 generate a software request
End of enumeration elements list.
SWREQ12 : PDMA Channel 12 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 12.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 12 - 12 (1 bit)
access : write-only
Enumeration:
#0 : 0
PDMA Channel 12 no effect
#1 : 1
PDMA Channel 12 generate a software request
End of enumeration elements list.
SWREQ13 : PDMA Channel 13 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 13.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 13 - 13 (1 bit)
access : write-only
Enumeration:
#0 : 0
PDMA Channel 13 no effect
#1 : 1
PDMA Channel 13 generate a software request
End of enumeration elements list.
SWREQ14 : PDMA Channel 14 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 14.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 14 - 14 (1 bit)
access : write-only
Enumeration:
#0 : 0
PDMA Channel 14 no effect
#1 : 1
PDMA Channel 14 generate a software request
End of enumeration elements list.
SWREQ15 : PDMA Channel 15 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 15.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 15 - 15 (1 bit)
access : write-only
Enumeration:
#0 : 0
PDMA Channel 15 no effect
#1 : 1
PDMA Channel 15 generate a software request
End of enumeration elements list.
PDMA Channel Request Status Register
address_offset : 0x40C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REQSTS0 : PDMA Channel 0 Request Status (Read Only)
This flag indicates whether channel 0 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel 0 has no request
#1 : 1
PDMA Channel 0 has a request
End of enumeration elements list.
REQSTS1 : PDMA Channel 1 Request Status (Read Only)
This flag indicates whether channel 1 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel 1 has no request
#1 : 1
PDMA Channel 1 has a request
End of enumeration elements list.
REQSTS2 : PDMA Channel 2 Request Status (Read Only)
This flag indicates whether channel 2 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel 2 has no request
#1 : 1
PDMA Channel 2 has a request
End of enumeration elements list.
REQSTS3 : PDMA Channel 3 Request Status (Read Only)
This flag indicates whether channel 3 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel 3 has no request
#1 : 1
PDMA Channel 3 has a request
End of enumeration elements list.
REQSTS4 : PDMA Channel 4 Request Status (Read Only)
This flag indicates whether channel 4 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel 4 has no request
#1 : 1
PDMA Channel 4 has a request
End of enumeration elements list.
REQSTS5 : PDMA Channel 5 Request Status (Read Only)
This flag indicates whether channel 5 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel 5 has no request
#1 : 1
PDMA Channel 5 has a request
End of enumeration elements list.
REQSTS6 : PDMA Channel 6 Request Status (Read Only)
This flag indicates whether channel 6 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel 6 has no request
#1 : 1
PDMA Channel 6 has a request
End of enumeration elements list.
REQSTS7 : PDMA Channel 7 Request Status (Read Only)
This flag indicates whether channel 7 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel 7 has no request
#1 : 1
PDMA Channel 7 has a request
End of enumeration elements list.
REQSTS8 : PDMA Channel 8 Request Status (Read Only)
This flag indicates whether channel 8 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel 8 has no request
#1 : 1
PDMA Channel 8 has a request
End of enumeration elements list.
REQSTS9 : PDMA Channel 9 Request Status (Read Only)
This flag indicates whether channel 9 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note1: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel 9 has no request
#1 : 1
PDMA Channel 9 has a request
End of enumeration elements list.
REQSTS10 : PDMA Channel 10 Request Status (Read Only)
This flag indicates whether channel 10 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel 10 has no request
#1 : 1
PDMA Channel 10 has a request
End of enumeration elements list.
REQSTS11 : PDMA Channel 11 Request Status (Read Only)
This flag indicates whether channel 11 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel 11 has no request
#1 : 1
PDMA Channel 11 has a request
End of enumeration elements list.
REQSTS12 : PDMA Channel 12 Request Status (Read Only)
This flag indicates whether channel 12 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel 12 has no request
#1 : 1
PDMA Channel 12 has a request
End of enumeration elements list.
REQSTS13 : PDMA Channel 13 Request Status (Read Only)
This flag indicates whether channel 13 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel 13 has no request
#1 : 1
PDMA Channel 13 has a request
End of enumeration elements list.
REQSTS14 : PDMA Channel 14 Request Status (Read Only)
This flag indicates whether channel 14 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel 14 has no request
#1 : 1
PDMA Channel 14 has a request
End of enumeration elements list.
REQSTS15 : PDMA Channel 15 Request Status (Read Only)
This flag indicates whether channel 15 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel 15 has no request
#1 : 1
PDMA Channel 15 has a request
End of enumeration elements list.
PDMA Fixed Priority Setting Register
address_offset : 0x410 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPRISET0 : PDMA Channel 0 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
Corresponding PDMA channel 0 is round-robin priority
#1 : 1
Set PDMA channel 0 to fixed priority channel.
Corresponding PDMA channel 0 is fixed priority
End of enumeration elements list.
FPRISET1 : PDMA Channel 1 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
Corresponding PDMA channel 1 is round-robin priority
#1 : 1
Set PDMA channel 1 to fixed priority channel.
Corresponding PDMA channel 1 is fixed priority
End of enumeration elements list.
FPRISET2 : PDMA Channel 2 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
Corresponding PDMA channel 2 is round-robin priority
#1 : 1
Set PDMA channel 2 to fixed priority channel.
Corresponding PDMA channel 2 is fixed priority
End of enumeration elements list.
FPRISET3 : PDMA Channel 3 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
Corresponding PDMA channel 3 is round-robin priority
#1 : 1
Set PDMA channel 3 to fixed priority channel.
Corresponding PDMA channel 3 is fixed priority
End of enumeration elements list.
FPRISET4 : PDMA Channel 4 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
Corresponding PDMA channel 4 is round-robin priority
#1 : 1
Set PDMA channel 4 to fixed priority channel.
Corresponding PDMA channel 4 is fixed priority
End of enumeration elements list.
FPRISET5 : PDMA Channel 5 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
Corresponding PDMA channel 5 is round-robin priority
#1 : 1
Set PDMA channel 5 to fixed priority channel.
Corresponding PDMA channel 5 is fixed priority
End of enumeration elements list.
FPRISET6 : PDMA Channel 6 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
Corresponding PDMA channel 6 is round-robin priority
#1 : 1
Set PDMA channel 6 to fixed priority channel.
Corresponding PDMA channel 6 is fixed priority
End of enumeration elements list.
FPRISET7 : PDMA Channel 7 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
Corresponding PDMA channel 7 is round-robin priority
#1 : 1
Set PDMA channel 7 to fixed priority channel.
Corresponding PDMA channel 7 is fixed priority
End of enumeration elements list.
FPRISET8 : PDMA Channel 8 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
Corresponding PDMA channel 8 is round-robin priority
#1 : 1
Set PDMA channel 8 to fixed priority channel.
Corresponding PDMA channel 8 is fixed priority
End of enumeration elements list.
FPRISET9 : PDMA Channel 9 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
Corresponding PDMA channel 9 is round-robin priority
#1 : 1
Set PDMA channel 9 to fixed priority channel.
Corresponding PDMA channel 9 is fixed priority
End of enumeration elements list.
FPRISET10 : PDMA Channel 10 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
Corresponding PDMA channel 10 is round-robin priority
#1 : 1
Set PDMA channel 10 to fixed priority channel.
Corresponding PDMA channel 10 is fixed priority
End of enumeration elements list.
FPRISET11 : PDMA Channel 10 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
Corresponding PDMA channel 11 is round-robin priority
#1 : 1
Set PDMA channel 11 to fixed priority channel.
Corresponding PDMA channel 11 is fixed priority
End of enumeration elements list.
FPRISET12 : PDMA Channel 12 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
Corresponding PDMA channel 12 is round-robin priority
#1 : 1
Set PDMA channel 12 to fixed priority channel.
Corresponding PDMA channel 12 is fixed priority
End of enumeration elements list.
FPRISET13 : PDMA Channel 13 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
Corresponding PDMA channel 13 is round-robin priority
#1 : 1
Set PDMA channel 13 to fixed priority channel.
Corresponding PDMA channel 13 is fixed priority
End of enumeration elements list.
FPRISET14 : PDMA Channel 14 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
Corresponding PDMA channel 14 is round-robin priority
#1 : 1
Set PDMA channel 14 to fixed priority channel.
Corresponding PDMA channel 14 is fixed priority
End of enumeration elements list.
FPRISET15 : PDMA Channel 15 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
Corresponding PDMA channel 15 is round-robin priority
#1 : 1
Set PDMA channel 15 to fixed priority channel.
Corresponding PDMA channel 15 is fixed priority
End of enumeration elements list.
PDMA Fixed Priority Clear Register
address_offset : 0x414 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FPRICLR0 : PDMA Channel 0 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel 0 fixed priority setting
End of enumeration elements list.
FPRICLR1 : PDMA Channel 1 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
bits : 1 - 1 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel 1 fixed priority setting
End of enumeration elements list.
FPRICLR2 : PDMA Channel 2 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
bits : 2 - 2 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel 2 fixed priority setting
End of enumeration elements list.
FPRICLR3 : PDMA Channel 3 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
bits : 3 - 3 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel 3 fixed priority setting
End of enumeration elements list.
FPRICLR4 : PDMA Channel 4 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
bits : 4 - 4 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel 4 fixed priority setting
End of enumeration elements list.
FPRICLR5 : PDMA Channel 5 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
bits : 5 - 5 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel 5 fixed priority setting
End of enumeration elements list.
FPRICLR6 : PDMA Channel 6 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
bits : 6 - 6 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel 6 fixed priority setting
End of enumeration elements list.
FPRICLR7 : PDMA Channel 7 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
bits : 7 - 7 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel 7 fixed priority setting
End of enumeration elements list.
FPRICLR8 : PDMA Channel 8 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
bits : 8 - 8 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel 8 fixed priority setting
End of enumeration elements list.
FPRICLR9 : PDMA Channel 9 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
bits : 9 - 9 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel 9 fixed priority setting
End of enumeration elements list.
FPRICLR10 : PDMA Channel 10 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
bits : 10 - 10 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel 10 fixed priority setting
End of enumeration elements list.
FPRICLR11 : PDMA Channel 11 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
bits : 11 - 11 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel 11 fixed priority setting
End of enumeration elements list.
FPRICLR12 : PDMA Channel 12 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
bits : 12 - 12 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel 12 fixed priority setting
End of enumeration elements list.
FPRICLR13 : PDMA Channel 13 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
bits : 13 - 13 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel 13 fixed priority setting
End of enumeration elements list.
FPRICLR14 : PDMA Channel 14 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
bits : 14 - 14 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel 14 fixed priority setting
End of enumeration elements list.
FPRICLR15 : PDMA Channel 15 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
bits : 15 - 15 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel 15 fixed priority setting
End of enumeration elements list.
PDMA Interrupt Enable Register
address_offset : 0x418 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTEN0 : PDMA Channel 0 Interrupt Enable Register
This field is used for enabling PDMA channel 0 interrupt.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 0 interrupt Disabled
#1 : 1
PDMA channel 0 interrupt Enabled
End of enumeration elements list.
INTEN1 : PDMA Channel 1 Interrupt Enable Register
This field is used for enabling PDMA channel 1 interrupt.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 1 interrupt Disabled
#1 : 1
PDMA channel 1 interrupt Enabled
End of enumeration elements list.
INTEN2 : PDMA Channel 2 Interrupt Enable Register
This field is used for enabling PDMA channel 2 interrupt.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 2 interrupt Disabled
#1 : 1
PDMA channel 2 interrupt Enabled
End of enumeration elements list.
INTEN3 : PDMA Channel 3 Interrupt Enable Register
This field is used for enabling PDMA channel 3 interrupt.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 3 interrupt Disabled
#1 : 1
PDMA channel 3 interrupt Enabled
End of enumeration elements list.
INTEN4 : PDMA Channel 4 Interrupt Enable Register
This field is used for enabling PDMA channel 4 interrupt.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 4 interrupt Disabled
#1 : 1
PDMA channel 4 interrupt Enabled
End of enumeration elements list.
INTEN5 : PDMA Channel 5 Interrupt Enable Register
This field is used for enabling PDMA channel 5 interrupt.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 5 interrupt Disabled
#1 : 1
PDMA channel 5 interrupt Enabled
End of enumeration elements list.
INTEN6 : PDMA Channel 6 Interrupt Enable Register
This field is used for enabling PDMA channel 6 interrupt.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 6 interrupt Disabled
#1 : 1
PDMA channel 6 interrupt Enabled
End of enumeration elements list.
INTEN7 : PDMA Channel 7 Interrupt Enable Register
This field is used for enabling PDMA channel 7 interrupt.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 7 interrupt Disabled
#1 : 1
PDMA channel 7 interrupt Enabled
End of enumeration elements list.
INTEN8 : PDMA Channel 8 Interrupt Enable Register
This field is used for enabling PDMA channel 8 interrupt.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 8 interrupt Disabled
#1 : 1
PDMA channel 8 interrupt Enabled
End of enumeration elements list.
INTEN9 : PDMA Channel 9 Interrupt Enable Register
This field is used for enabling PDMA channel 9 interrupt.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 9 interrupt Disabled
#1 : 1
PDMA channel 9 interrupt Enabled
End of enumeration elements list.
INTEN10 : PDMA Channel 10 Interrupt Enable Register
This field is used for enabling PDMA channel 10 interrupt.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 10 interrupt Disabled
#1 : 1
PDMA channel 10 interrupt Enabled
End of enumeration elements list.
INTEN11 : PDMA Channel 11 Interrupt Enable Register
This field is used for enabling PDMA channel 11 interrupt.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 11 interrupt Disabled
#1 : 1
PDMA channel 11 interrupt Enabled
End of enumeration elements list.
INTEN12 : PDMA Channel 0 Interrupt Enable Register
This field is used for enabling PDMA channel 12 interrupt.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 12 interrupt Disabled
#1 : 1
PDMA channel 12 interrupt Enabled
End of enumeration elements list.
INTEN13 : PDMA Channel 13 Interrupt Enable Register
This field is used for enabling PDMA channel 13 interrupt.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 13 interrupt Disabled
#1 : 1
PDMA channel 13 interrupt Enabled
End of enumeration elements list.
INTEN14 : PDMA Channel 14 Interrupt Enable Register
This field is used for enabling PDMA channel 14 interrupt.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 14 interrupt Disabled
#1 : 1
PDMA channel 14 interrupt Enabled
End of enumeration elements list.
INTEN15 : PDMA Channel 15 Interrupt Enable Register
This field is used for enabling PDMA channel 15 interrupt.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 15 interrupt Disabled
#1 : 1
PDMA channel 15 interrupt Enabled
End of enumeration elements list.
PDMA Interrupt Status Register
address_offset : 0x41C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ABTIF : PDMA Read/Write Target Abort Interrupt Flag (Read-only)
This bit indicates that PDMA has target abort error Software can read PDMA_ABTSTS register to find which channel has target abort error.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received
#1 : 1
AHB bus ERROR response received
End of enumeration elements list.
TDIF : Transfer Done Interrupt Flag (Read Only)
This bit indicates that PDMA controller has finished transmission User can read PDMA_TDSTS register to indicate which channel finished transfer.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Not finished yet
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
ALIGNF : Transfer Alignment Interrupt Flag (Read Only)
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel source address and destination address both follow transfer width setting
#1 : 1
PDMA channel source address or destination address is not follow transfer width setting
End of enumeration elements list.
REQTOF0 : Request Time-out Flag for Channel 0
This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear these bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No request time-out
#1 : 1
Peripheral request time-out
End of enumeration elements list.
REQTOF1 : Request Time-out Flag for Channel 1
This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear these bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No request time-out
#1 : 1
Peripheral request time-out
End of enumeration elements list.
PDMA Channel Read/Write Target Abort Flag Register
address_offset : 0x420 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ABTIF0 : PDMA Channel 0 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 0 has target abort error User can write 1 to clear these bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel 0 transfer
#1 : 1
AHB bus ERROR response received when channel 0 transfer
End of enumeration elements list.
ABTIF1 : PDMA Channel 1 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 1 has target abort error User can write 1 to clear these bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel 1 transfer
#1 : 1
AHB bus ERROR response received when channel 1 transfer
End of enumeration elements list.
ABTIF2 : PDMA Channel 2 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 2 has target abort error User can write 1 to clear these bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel 2 transfer
#1 : 1
AHB bus ERROR response received when channel 2 transfer
End of enumeration elements list.
ABTIF3 : PDMA Channel 3 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 3 has target abort error User can write 1 to clear these bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel 3 transfer
#1 : 1
AHB bus ERROR response received when channel 3 transfer
End of enumeration elements list.
ABTIF4 : PDMA Channel 4 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 4 has target abort error User can write 1 to clear these bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel 4 transfer
#1 : 1
AHB bus ERROR response received when channel 4 transfer
End of enumeration elements list.
ABTIF5 : PDMA Channel 5 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 5 has target abort error User can write 1 to clear these bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel 5 transfer
#1 : 1
AHB bus ERROR response received when channel 5 transfer
End of enumeration elements list.
ABTIF6 : PDMA Channel 6 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 6 has target abort error User can write 1 to clear these bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel 6 transfer
#1 : 1
AHB bus ERROR response received when channel 6 transfer
End of enumeration elements list.
ABTIF7 : PDMA Channel 7 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 7 has target abort error User can write 1 to clear these bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel 7 transfer
#1 : 1
AHB bus ERROR response received when channel 7 transfer
End of enumeration elements list.
ABTIF8 : PDMA Channel 8 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 8 has target abort error User can write 1 to clear these bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel 8 transfer
#1 : 1
AHB bus ERROR response received when channel 8 transfer
End of enumeration elements list.
ABTIF9 : PDMA Channel 9 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 9 has target abort error User can write 1 to clear these bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel 9 transfer
#1 : 1
AHB bus ERROR response received when channel 9 transfer
End of enumeration elements list.
ABTIF10 : PDMA Channel 10 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 10 has target abort error User can write 1 to clear these bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel 10 transfer
#1 : 1
AHB bus ERROR response received when channel 10 transfer
End of enumeration elements list.
ABTIF11 : PDMA Channel 11 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 11 has target abort error User can write 1 to clear these bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel 11 transfer
#1 : 1
AHB bus ERROR response received when channel 11 transfer
End of enumeration elements list.
ABTIF12 : PDMA Channel 12 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 12 has target abort error User can write 1 to clear these bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel 12 transfer
#1 : 1
AHB bus ERROR response received when channel 12 transfer
End of enumeration elements list.
ABTIF13 : PDMA Channel 13 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 13 has target abort error User can write 1 to clear these bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel 13 transfer
#1 : 1
AHB bus ERROR response received when channel 13 transfer
End of enumeration elements list.
ABTIF14 : PDMA Channel 14 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 14 has target abort error User can write 1 to clear these bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel 14 transfer
#1 : 1
AHB bus ERROR response received when channel 14 transfer
End of enumeration elements list.
ABTIF15 : PDMA Channel 15 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 15 has target abort error User can write 1 to clear these bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel 15 transfer
#1 : 1
AHB bus ERROR response received when channel 15 transfer
End of enumeration elements list.
PDMA Channel Transfer Done Flag Register
address_offset : 0x424 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDIF0 : PDMA Channel 0 Transfer Done Flag Register
This bit indicates PDMA channel 0 transfer has been finished or not, user can write 1 to clear this bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 0 transfer has not finished
#1 : 1
PDMA channel 0 has finished transmission
End of enumeration elements list.
TDIF1 : PDMA Channel 1 Transfer Done Flag Register
This bit indicates PDMA channel 1 transfer has been finished or not, user can write 1 to clear this bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 1 transfer has not finished
#1 : 1
PDMA channel 1 has finished transmission
End of enumeration elements list.
TDIF2 : PDMA Channel 2 Transfer Done Flag Register
This bit indicates PDMA channel 2 transfer has been finished or not, user can write 1 to clear this bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 2 transfer has not finished
#1 : 1
PDMA channel 2 has finished transmission
End of enumeration elements list.
TDIF3 : PDMA Channel 3 Transfer Done Flag Register
This bit indicates PDMA channel 3 transfer has been finished or not, user can write 1 to clear this bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 3 transfer has not finished
#1 : 1
PDMA channel 3 has finished transmission
End of enumeration elements list.
TDIF4 : PDMA Channel 4 Transfer Done Flag Register
This bit indicates PDMA channel 4 transfer has been finished or not, user can write 1 to clear this bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 4 transfer has not finished
#1 : 1
PDMA channel 4 has finished transmission
End of enumeration elements list.
TDIF5 : PDMA Channel 5 Transfer Done Flag Register
This bit indicates PDMA channel 5 transfer has been finished or not, user can write 1 to clear this bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 5 transfer has not finished
#1 : 1
PDMA channel 5 has finished transmission
End of enumeration elements list.
TDIF6 : PDMA Channel 6 Transfer Done Flag Register
This bit indicates PDMA channel 6 transfer has been finished or not, user can write 1 to clear this bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 6 transfer has not finished
#1 : 1
PDMA channel 6 has finished transmission
End of enumeration elements list.
TDIF7 : PDMA Channel 7 Transfer Done Flag Register
This bit indicates PDMA channel 7 transfer has been finished or not, user can write 1 to clear this bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 7 transfer has not finished
#1 : 1
PDMA channel 7 has finished transmission
End of enumeration elements list.
TDIF8 : PDMA Channel 8 Transfer Done Flag Register
This bit indicates PDMA channel 8 transfer has been finished or not, user can write 1 to clear this bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 8 transfer has not finished
#1 : 1
PDMA channel 8 has finished transmission
End of enumeration elements list.
TDIF9 : PDMA Channel 9 Transfer Done Flag Register
This bit indicates PDMA channel 9 transfer has been finished or not, user can write 1 to clear this bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 9 transfer has not finished
#1 : 1
PDMA channel 9 has finished transmission
End of enumeration elements list.
TDIF10 : PDMA Channel 10 Transfer Done Flag Register
This bit indicates PDMA channel 10 transfer has been finished or not, user can write 1 to clear this bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 10 transfer has not finished
#1 : 1
PDMA channel 10 has finished transmission
End of enumeration elements list.
TDIF11 : PDMA Channel 11 Transfer Done Flag Register
This bit indicates PDMA channel 11 transfer has been finished or not, user can write 1 to clear this bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 11 transfer has not finished
#1 : 1
PDMA channel 11 has finished transmission
End of enumeration elements list.
TDIF12 : PDMA Channel 12 Transfer Done Flag Register
This bit indicates PDMA channel 12 transfer has been finished or not, user can write 1 to clear this bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 12 transfer has not finished
#1 : 1
PDMA channel 12 has finished transmission
End of enumeration elements list.
TDIF13 : PDMA Channel 13 Transfer Done Flag Register
This bit indicates PDMA channel 13 transfer has been finished or not, user can write 1 to clear this bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 13 transfer has not finished
#1 : 1
PDMA channel 13 has finished transmission
End of enumeration elements list.
TDIF14 : PDMA Channel 14 Transfer Done Flag Register
This bit indicates PDMA channel 14 transfer has been finished or not, user can write 1 to clear this bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 14 transfer has not finished
#1 : 1
PDMA channel 14 has finished transmission
End of enumeration elements list.
TDIF15 : PDMA Channel 15 Transfer Done Flag Register
This bit indicates PDMA channel 15 transfer has been finished or not, user can write 1 to clear this bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 15 transfer has not finished
#1 : 1
PDMA channel 15 has finished transmission
End of enumeration elements list.
PDMA Transfer Alignment Status Register
address_offset : 0x428 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALIGN0 : PDMA Channel 0 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 0 source address and destination address both follow transfer width setting
#1 : 1
PDMA channel 0 source address or destination address is not follow transfer width setting
End of enumeration elements list.
ALIGN1 : PDMA Channel 1 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 1 source address and destination address both follow transfer width setting
#1 : 1
PDMA channel 1 source address or destination address is not follow transfer width setting
End of enumeration elements list.
ALIGN2 : PDMA Channel 2 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 2 source address and destination address both follow transfer width setting
#1 : 1
PDMA channel 2 source address or destination address is not follow transfer width setting
End of enumeration elements list.
ALIGN3 : PDMA Channel 3 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 3 source address and destination address both follow transfer width setting
#1 : 1
PDMA channel 3 source address or destination address is not follow transfer width setting
End of enumeration elements list.
ALIGN4 : PDMA Channel 4 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 4 source address and destination address both follow transfer width setting
#1 : 1
PDMA channel 4 source address or destination address is not follow transfer width setting
End of enumeration elements list.
ALIGN5 : PDMA Channel 5 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 5 source address and destination address both follow transfer width setting
#1 : 1
PDMA channel 5 source address or destination address is not follow transfer width setting
End of enumeration elements list.
ALIGN6 : PDMA Channel 6 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 6 source address and destination address both follow transfer width setting
#1 : 1
PDMA channel 6 source address or destination address is not follow transfer width setting
End of enumeration elements list.
ALIGN7 : PDMA Channel 7 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 7 source address and destination address both follow transfer width setting
#1 : 1
PDMA channel 7 source address or destination address is not follow transfer width setting
End of enumeration elements list.
ALIGN8 : PDMA Channel 8 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 8 source address and destination address both follow transfer width setting
#1 : 1
PDMA channel 8 source address or destination address is not follow transfer width setting
End of enumeration elements list.
ALIGN9 : PDMA Channel 9 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 9 source address and destination address both follow transfer width setting
#1 : 1
PDMA channel 9 source address or destination address is not follow transfer width setting
End of enumeration elements list.
ALIGN10 : PDMA Channel 10 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 10 source address and destination address both follow transfer width setting
#1 : 1
PDMA channel 10 source address or destination address is not follow transfer width setting
End of enumeration elements list.
ALIGN11 : PDMA Channel 11 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 11 source address and destination address both follow transfer width setting
#1 : 1
PDMA channel 11 source address or destination address is not follow transfer width setting
End of enumeration elements list.
ALIGN12 : PDMA Channel 12 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 12 source address and destination address both follow transfer width setting
#1 : 1
PDMA channel 12 source address or destination address is not follow transfer width setting
End of enumeration elements list.
ALIGN13 : PDMA Channel 13 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 13 source address and destination address both follow transfer width setting
#1 : 1
PDMA channel 13 source address or destination address is not follow transfer width setting
End of enumeration elements list.
ALIGN14 : PDMA Channel 14 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 14 source address and destination address both follow transfer width setting
#1 : 1
PDMA channel 14 source address or destination address is not follow transfer width setting
End of enumeration elements list.
ALIGN15 : PDMA Channel 15 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel 15 source address and destination address both follow transfer width setting
#1 : 1
PDMA channel 15 source address or destination address is not follow transfer width setting
End of enumeration elements list.
PDMA Transfer Active Flag Register
address_offset : 0x42C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXACTF0 : PDMA Channel 0 Transfer on Active Flag Register (Read Only)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel 0 is not finished
#1 : 1
PDMA channel 0 is in active
End of enumeration elements list.
TXACTF1 : PDMA Channel 1 Transfer on Active Flag Register (Read Only)
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel 1 is not finished
#1 : 1
PDMA channel 1 is in active
End of enumeration elements list.
TXACTF2 : PDMA Channel 2 Transfer on Active Flag Register (Read Only)
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel 2 is not finished
#1 : 1
PDMA channel 2 is in active
End of enumeration elements list.
TXACTF3 : PDMA Channel 3 Transfer on Active Flag Register (Read Only)
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel 3 is not finished
#1 : 1
PDMA channel 3 is in active
End of enumeration elements list.
TXACTF4 : PDMA Channel 4 Transfer on Active Flag Register (Read Only)
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel 4 is not finished
#1 : 1
PDMA channel 4 is in active
End of enumeration elements list.
TXACTF5 : PDMA Channel 5 Transfer on Active Flag Register (Read Only)
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel 5 is not finished
#1 : 1
PDMA channel 5 is in active
End of enumeration elements list.
TXACTF6 : PDMA Channel 6 Transfer on Active Flag Register (Read Only)
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel 6 is not finished
#1 : 1
PDMA channel 6 is in active
End of enumeration elements list.
TXACTF7 : PDMA Channel 7 Transfer on Active Flag Register (Read Only)
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel 7 is not finished
#1 : 1
PDMA channel 7 is in active
End of enumeration elements list.
TXACTF8 : PDMA Channel 8 Transfer on Active Flag Register (Read Only)
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel 8 is not finished
#1 : 1
PDMA channel 8 is in active
End of enumeration elements list.
TXACTF9 : PDMA Channel 9 Transfer on Active Flag Register (Read Only)
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel 9 is not finished
#1 : 1
PDMA channel 9 is in active
End of enumeration elements list.
TXACTF10 : PDMA Channel 10 Transfer on Active Flag Register (Read Only)
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel 10 is not finished
#1 : 1
PDMA channel 10 is in active
End of enumeration elements list.
TXACTF11 : PDMA Channel 11 Transfer on Active Flag Register (Read Only)
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel 11 is not finished
#1 : 1
PDMA channel 11 is in active
End of enumeration elements list.
TXACTF12 : PDMA Channel 12 Transfer on Active Flag Register (Read Only)
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel 12 is not finished
#1 : 1
PDMA channel 12 is in active
End of enumeration elements list.
TXACTF13 : PDMA Channel 13 Transfer on Active Flag Register (Read Only)
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel 13 is not finished
#1 : 1
PDMA channel 13 is in active
End of enumeration elements list.
TXACTF14 : PDMA Channel 14 Transfer on Active Flag Register (Read Only)
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel 14 is not finished
#1 : 1
PDMA channel 14 is in active
End of enumeration elements list.
TXACTF15 : PDMA Channel 15 Transfer on Active Flag Register (Read Only)
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel 15 is not finished
#1 : 1
PDMA channel 15 is in active
End of enumeration elements list.
PDMA Time-out Prescaler Register
address_offset : 0x430 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUTPSC0 : PDMA Channel 0 Time-out Clock Source Prescaler Bits
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
PDMA channel 0 time-out clock source is HCLK/28
#001 : 1
PDMA channel 0 time-out clock source is HCLK/29
#010 : 2
PDMA channel 0 time-out clock source is HCLK/210
#011 : 3
PDMA channel 0 time-out clock source is HCLK/211
#100 : 4
PDMA channel 0 time-out clock source is HCLK/212
#101 : 5
PDMA channel 0 time-out clock source is HCLK/213
#110 : 6
PDMA channel 0 time-out clock source is HCLK/214
#111 : 7
PDMA channel 0 time-out clock source is HCLK/215
End of enumeration elements list.
TOUTPSC1 : PDMA Channel 1 Time-out Clock Source Prescaler Bits
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 0
PDMA channel 1 time-out clock source is HCLK/28
#001 : 1
PDMA channel 1 time-out clock source is HCLK/29
#010 : 2
PDMA channel 1 time-out clock source is HCLK/210
#011 : 3
PDMA channel 1 time-out clock source is HCLK/211
#100 : 4
PDMA channel 1 time-out clock source is HCLK/212
#101 : 5
PDMA channel 1 time-out clock source is HCLK/213
#110 : 6
PDMA channel 1 time-out clock source is HCLK/214
#111 : 7
PDMA channel 1 time-out clock source is HCLK/215
End of enumeration elements list.
PDMA Time-out Enable Register
address_offset : 0x434 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUTEN0 : PDMA Channel 0 Time-out Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel 0 time-out function Disable
#1 : 1
PDMA Channel 0 time-out function Enable
End of enumeration elements list.
TOUTEN1 : PDMA Channel 1 Time-out Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel 1 time-out function Disable
#1 : 1
PDMA Channel 1 time-out function Enable
End of enumeration elements list.
PDMA Time-out Interrupt Enable Register
address_offset : 0x438 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUTIEN0 : PDMA Channel 0 Time-out Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel 0 time-out interrupt Disable
#1 : 1
PDMA Channel 0 time-out interrupt Enable
End of enumeration elements list.
TOUTIEN1 : PDMA Channel 1 Time-out Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel 1 time-out interrupt Disable
#1 : 1
PDMA Channel 1 time-out interrupt Enable
End of enumeration elements list.
PDMA Scatter-gather Descriptor Table Base Address Register
address_offset : 0x43C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCATBA : PDMA Scatter-gather Descriptor Table Address Register
In Scatter-Gather mode, this is the base address for calculating the next link - list address. The next link address equation is
Note: Only useful in Scatter-Gather mode.
bits : 16 - 31 (16 bit)
access : read-write
Source Address Register of PDMA Channel 4
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMA Time-out Counter Ch1 and Ch0 Register
address_offset : 0x440 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOC0 : Time-out Counter for Channel 0
This controls the period of time-out function for channel 0. The calculation unit is based on the setting of TOUTPSC0.
bits : 0 - 15 (16 bit)
access : read-write
TOC1 : Time-out Counter for Channel 1
This controls the period of time-out function for channel 1. The calculation unit is based on the setting of TOUTPSC1.
bits : 16 - 31 (16 bit)
access : read-write
PDMA Channel Reset Register
address_offset : 0x460 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0RST : Channel 0 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
corresponding channel 0 not reset
#1 : 1
corresponding channel 0 is reset
End of enumeration elements list.
CH1RST : Channel 1 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
corresponding channel 1 not reset
#1 : 1
corresponding channel 1 is reset
End of enumeration elements list.
CH2RST : Channel 2 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
corresponding channel 2 not reset
#1 : 1
corresponding channel 2 is reset
End of enumeration elements list.
CH3RST : Channel 3 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
corresponding channel 3 not reset
#1 : 1
corresponding channel 3 is reset
End of enumeration elements list.
CH4RST : Channel 4 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
corresponding channel 4 not reset
#1 : 1
corresponding channel 4 is reset
End of enumeration elements list.
CH5RST : Channel 5 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
corresponding channel 5 not reset
#1 : 1
corresponding channel 5 is reset
End of enumeration elements list.
CH6RST : Channel 6 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
corresponding channel 6 not reset
#1 : 1
corresponding channel 6 is reset
End of enumeration elements list.
CH7RST : Channel 7 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
corresponding channel 7 not reset
#1 : 1
corresponding channel 7 is reset
End of enumeration elements list.
CH8RST : Channel 8 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
corresponding channel 8 not reset
#1 : 1
corresponding channel 8 is reset
End of enumeration elements list.
CH9RST : Channel 9 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
corresponding channel 9 not reset
#1 : 1
corresponding channel 9 is reset
End of enumeration elements list.
CH10RST : Channel 10 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
corresponding channel 10 not reset
#1 : 1
corresponding channel 10 is reset
End of enumeration elements list.
CH11RST : Channel 11 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
corresponding channel 11 not reset
#1 : 1
corresponding channel 11 is reset
End of enumeration elements list.
CH12RST : Channel 12 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
corresponding channel 12 not reset
#1 : 1
corresponding channel 12 is reset
End of enumeration elements list.
CH13RST : Channel 13 Reset
Note 1 : This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
corresponding channel 13 not reset
#1 : 1
corresponding channel 13 is reset
End of enumeration elements list.
CH14RST : Channel 14 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
corresponding channel 14 not reset
#1 : 1
corresponding channel 14 is reset
End of enumeration elements list.
CH15RST : Channel 15 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
corresponding channel 15 not reset
#1 : 1
corresponding channel 15 is reset
End of enumeration elements list.
Destination Address Register of PDMA Channel 4
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMA Request Source Select Register 0
address_offset : 0x480 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REQSRC0 : Channel 0 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0.
Note 1: A peripheral can't assign to two channels at the same time.
Note 2: This field is useless when transfer between memory and memory.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
Disable PDMA peripheral request
4 : 4
Channel connects to UART0_TX
5 : 5
Channel connects to UART0_RX
20 : 20
Channel connects to SPI0_TX
21 : 21
Channel connects to SPI0_RX
22 : 22
Channel connects to SPI1_TX
23 : 23
Channel connects to SPI1_RX
24 : 24
Channel connects to SPI2_TX
25 : 25
Channel connects to SPI2_RX
27 : 27
Channel connects to DMIC_RX
28 : 28
Channel connects to DPWM_TX
32 : 32
Channel connects to PWM0_P1_RX
33 : 33
Channel connects to PWM0_P2_RX
34 : 34
Channel connects to PWM0_P3_RX
44 : 44
Channel connects to I2S0_TX
45 : 45
Channel connects to I2S0_RX
46 : 46
Channel connects to TMR0
47 : 47
Channel connects to TMR1
48 : 48
Channel connects to TMR2
49 : 49
Channel connects to TMR3
50 : 50
Channel connects to ADC_RX
End of enumeration elements list.
REQSRC1 : Channel 1 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 8 - 13 (6 bit)
access : read-write
REQSRC2 : Channel 2 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 16 - 21 (6 bit)
access : read-write
REQSRC3 : Channel 3 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 24 - 29 (6 bit)
access : read-write
PDMA Request Source Select Register 1
address_offset : 0x484 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REQSRC4 : Channel 4 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 0 - 5 (6 bit)
access : read-write
REQSRC5 : Channel 5 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 5. User can configure the peripheral setting by REQSRC5.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 8 - 13 (6 bit)
access : read-write
REQSRC6 : Channel 6 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 6. User can configure the peripheral setting by REQSRC6.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 16 - 21 (6 bit)
access : read-write
REQSRC7 : Channel 7 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 7. User can configure the peripheral setting by REQSRC7.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 24 - 29 (6 bit)
access : read-write
PDMA Request Source Select Register 2
address_offset : 0x488 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REQSRC8 : Channel 8 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 8. User can configure the peripheral setting by REQSRC8.
Note: The channel configuration is the same as REQSRC.0 field. Please refer to the explanation of REQSRC0.
bits : 0 - 5 (6 bit)
access : read-write
REQSRC9 : Channel 9 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 9. User can configure the peripheral setting by REQSRC9.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 8 - 13 (6 bit)
access : read-write
REQSRC10 : Channel 10 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 10. User can configure the peripheral setting by REQSRC10.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 16 - 21 (6 bit)
access : read-write
REQSRC11 : Channel 11 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 11. User can configure 1the peripheral setting by REQSRC11.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 24 - 29 (6 bit)
access : read-write
PDMA Request Source Select Register 3
address_offset : 0x48C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REQSRC12 : Channel 4 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 12. User can configure the peripheral setting by REQSRC12.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 0 - 5 (6 bit)
access : read-write
REQSRC13 : Channel 5 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 13. User can configure the peripheral setting by REQSRC13.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 8 - 13 (6 bit)
access : read-write
REQSRC14 : Channel 6 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 14. User can configure the peripheral setting by REQSRC14.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 16 - 21 (6 bit)
access : read-write
REQSRC15 : Channel 7 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 15. User can configure the peripheral setting by REQSRC15.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 24 - 29 (6 bit)
access : read-write
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 4
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Descriptor Table Control Register of PDMA Channel 5
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Stride Transfer Count Register of PDMA Channel 0
address_offset : 0x500 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STC : PDMA Stride Transfer Count
bits : 0 - 15 (16 bit)
access : read-write
Address Stride Offset Register of PDMA Channel 0
address_offset : 0x504 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SASOL : PDMA Source Address Stride Offset Length
The 16-bit register defines the source address stride transfer offset count of each row.
bits : 0 - 15 (16 bit)
access : read-write
DASOL : PDMA Destination Address Stride Offset Length
The 16-bit register defines the destination address stride transfer offset count of each row.
bits : 16 - 31 (16 bit)
access : read-write
Stride Transfer Count Register of PDMA Channel 1
address_offset : 0x508 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Address Stride Offset Register of PDMA Channel 1
address_offset : 0x50C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Stride Transfer Count Register of PDMA Channel 2
address_offset : 0x510 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Address Stride Offset Register of PDMA Channel 2
address_offset : 0x514 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Stride Transfer Count Register of PDMA Channel 3
address_offset : 0x518 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Address Stride Offset Register of PDMA Channel 3
address_offset : 0x51C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Stride Transfer Count Register of PDMA Channel 4
address_offset : 0x520 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Address Stride Offset Register of PDMA Channel 4
address_offset : 0x524 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Stride Transfer Count Register of PDMA Channel 5
address_offset : 0x528 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Address Stride Offset Register of PDMA Channel 5
address_offset : 0x52C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel 5
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel 5
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 5
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Descriptor Table Control Register of PDMA Channel 6
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel 6
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel 6
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 6
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Descriptor Table Control Register of PDMA Channel 7
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel 7
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel 7
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 7
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel 0
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DA : PDMA Transfer Destination Address Register
This field indicates a 32-bit destination address of PDMA controller.
bits : 0 - 31 (32 bit)
access : read-write
Descriptor Table Control Register of PDMA Channel 8
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel 8
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel 8
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 8
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Descriptor Table Control Register of PDMA Channel 9
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel 9
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel 9
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 9
address_offset : 0x9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Descriptor Table Control Register of PDMA Channel 10
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel 10
address_offset : 0xA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel 10
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 10
address_offset : 0xAC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Descriptor Table Control Register of PDMA Channel 11
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel 11
address_offset : 0xB4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel 11
address_offset : 0xB8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 11
address_offset : 0xBC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 0
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NEXT : PDMA Next Descriptor Table Offset
This field indicates the offset of the next descriptor table address in system memory.
Write Operation:
If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the next descriptor table is start from 0x2000_0100, then this field must fill in 0x0100.
Read Operation:
When operating in scatter-gather mode, the last two bits NEXT[1:0] will become reserved, and indicate the first next address of system memory.
Note 1: The first descriptor table address must be word boundary.
Note 2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.
Note 3: The address of descriptor tables must be in the same 64KB area.
bits : 0 - 15 (16 bit)
access : read-write
EXENEXT : PDMA Execution Next Descriptor Table Offset
This field indicates the offset of next descriptor table address of current execution descriptor table in system memory.
Note: write operation is useless in this field.
bits : 16 - 31 (16 bit)
access : read-write
Descriptor Table Control Register of PDMA Channel 12
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel 12
address_offset : 0xC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel 12
address_offset : 0xC8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 12
address_offset : 0xCC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Descriptor Table Control Register of PDMA Channel 13
address_offset : 0xD0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel 13
address_offset : 0xD4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel 13
address_offset : 0xD8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 13
address_offset : 0xDC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Descriptor Table Control Register of PDMA Channel 14
address_offset : 0xE0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel 14
address_offset : 0xE4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel 14
address_offset : 0xE8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 14
address_offset : 0xEC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Descriptor Table Control Register of PDMA Channel 15
address_offset : 0xF0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel 15
address_offset : 0xF4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel 15
address_offset : 0xF8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 15
address_offset : 0xFC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.