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PWM Control Register 0
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRLD0 : PWM Channel 0 Center Re-load
In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
bits : 0 - 0 (1 bit)
access : read-write
CTRLD1 : PWM Channel 1 Center Re-load
In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
bits : 1 - 1 (1 bit)
access : read-write
CTRLD2 : PWM Channel 2 Center Re-load
In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
bits : 2 - 2 (1 bit)
access : read-write
CTRLD3 : PWM Channel 3 Center Re-load
In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
bits : 3 - 3 (1 bit)
access : read-write
CTRLD4 : PWM Channel 4 Center Re-load
In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
bits : 4 - 4 (1 bit)
access : read-write
CTRLD5 : PWM Channel 5 Center Re-load
In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
bits : 5 - 5 (1 bit)
access : read-write
WINLDEN0 : PWM Channel 0 Window Load Enable Bits
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register and cleared by hardware after load success
End of enumeration elements list.
WINLDEN1 : PWM Channel 1 Window Load Enable Bits
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register and cleared by hardware after load success
End of enumeration elements list.
WINLDEN2 : PWM Channel 2 Window Load Enable Bits
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register and cleared by hardware after load success
End of enumeration elements list.
WINLDEN3 : PWM Channel 3 Window Load Enable Bits
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register and cleared by hardware after load success
End of enumeration elements list.
WINLDEN4 : PWM Channel 4 Window Load Enable Bits
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register and cleared by hardware after load success
End of enumeration elements list.
WINLDEN5 : PWM Channel 5 Window Load Enable Bits
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register and cleared by hardware after load success
End of enumeration elements list.
IMMLDEN0 : PWM Channel 0 Immediately Load Enable Bits
Note: If IMMLDEN0 is enabled, WINLDEN0 and CTRLD0 will be invalid.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
End of enumeration elements list.
IMMLDEN1 : PWM Channel 1 Immediately Load Enable Bits
Note: If IMMLDEN1 is enabled, WINLDEN1 and CTRLD1 will be invalid.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
End of enumeration elements list.
IMMLDEN2 : PWM Channel 2 Immediately Load Enable Bits
Note: If IMMLDEN2 is enabled, WINLDEN2 and CTRLD2 will be invalid.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
End of enumeration elements list.
IMMLDEN3 : PWM Channel 3 Immediately Load Enable Bits
Note: If IMMLDEN3 is enabled, WINLDEN3 and CTRLD3 will be invalid.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
End of enumeration elements list.
IMMLDEN4 : PWM Channel 4 Immediately Load Enable Bits
Note: If IMMLDEN4 is enabled, WINLDEN4 and CTRLD4 will be invalid.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
End of enumeration elements list.
IMMLDEN5 : PWM Channel 5 Immediately Load Enable Bits
Note: If IMMLDEN5 is enabled, WINLDEN5 and CTRLD5 will be invalid.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
End of enumeration elements list.
GROUPEN : Group Function Enable Bit(S)
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
The output waveform of each PWM channel are independent
#1 : 1
Unify the PWM_CH2 and PWM_CH4 to output the same waveform as PWM_CH0 and unify the PWM_CH3 and PWM_CH5 to output the same waveform as PWM_CH1
End of enumeration elements list.
DBGHALT : ICE Debug Mode Counter Halt (Write Protected)
If counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode.
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode counter halt disable
#1 : 1
ICE debug mode counter halt enable
End of enumeration elements list.
DBGTRIOFF : ICE Debug Mode Acknowledge Disable (Write Protected)
PWM pin will keep output no matter ICE debug mode acknowledged or not.
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode acknowledgement effects PWM output
#1 : 1
ICE debug mode acknowledgement disabled
End of enumeration elements list.
PWM Clock Source Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECLKSRC0 : PWM_CH01 External Clock Source Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
PWM0_CLK
#001 : 1
TIMER0 overflow
#010 : 2
TIMER1 overflow
#011 : 3
TIMER2 overflow
#100 : 4
TIMER3 overflow
End of enumeration elements list.
ECLKSRC2 : PWM_CH23 External Clock Source Select
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
PWM0_CLK
#001 : 1
TIMER0 overflow
#010 : 2
TIMER1 overflow
#011 : 3
TIMER2 overflow
#100 : 4
TIMER3 overflow
End of enumeration elements list.
ECLKSRC4 : PWM_CH45 External Clock Source Select
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 0
PWM0_CLK
#001 : 1
TIMER0 overflow
#010 : 2
TIMER1 overflow
#011 : 3
TIMER2 overflow
#100 : 4
TIMER3 overflow
End of enumeration elements list.
PWM Free Trigger Compare Register 0/1
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTCMP : PWM Free Trigger Compare Register
FTCMP use to compare with even CNTR to trigger EADC. FTCMPDAT0_1, 2_3, 4_5 corresponding complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
bits : 0 - 15 (16 bit)
access : read-write
PWM Free Trigger Compare Register 2/3
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Free Trigger Compare Register 4/5
address_offset : 0x108 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Synchronous Start Control Register
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSEN0 : PWM Channel 0 Synchronous Start Function Enable Bits
When synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM synchronous start function Disabled
#1 : 1
PWM synchronous start function Enabled
End of enumeration elements list.
SSEN1 : PWM Channel 1 Synchronous Start Function Enable Bits
When synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM synchronous start function Disabled
#1 : 1
PWM synchronous start function Enabled
End of enumeration elements list.
SSEN2 : PWM Channel 2 Synchronous Start Function Enable Bits
When synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM synchronous start function Disabled
#1 : 1
PWM synchronous start function Enabled
End of enumeration elements list.
SSEN3 : PWM Channel 3 Synchronous Start Function Enable Bits
When synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM synchronous start function Disabled
#1 : 1
PWM synchronous start function Enabled
End of enumeration elements list.
SSEN4 : PWM Channel 4 Synchronous Start Function Enable Bits
When synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM synchronous start function Disabled
#1 : 1
PWM synchronous start function Enabled
End of enumeration elements list.
SSEN5 : PWM Channel 5 Synchronous Start Function Enable Bits
When synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM synchronous start function Disabled
#1 : 1
PWM synchronous start function Enabled
End of enumeration elements list.
SSRC : PWM Synchronous Start Source Select Bits
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Synchronous start source come from PWM0
End of enumeration elements list.
PWM Synchronous Start Trigger Register
address_offset : 0x114 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CNTSEN : PWM Counter Synchronous Start Enable (Write Only)
PMW counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx) start counting at the same time.
Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated PWM channel counter synchronous start function is enabled.
bits : 0 - 0 (1 bit)
access : write-only
PWM Status Register
address_offset : 0x120 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTMAXF0 : PWM Channel 0 Time-base Counter Equal to 0xFFFF Latched Flag
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
indicates the time-base counter never reached its maximum value 0xFFFF
#1 : 1
indicates the time-base counter reached its maximum value, software can write 1 to clear this bit
End of enumeration elements list.
CNTMAXF1 : PWM Channel 1 Time-base Counter Equal to 0xFFFF Latched Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
indicates the time-base counter never reached its maximum value 0xFFFF
#1 : 1
indicates the time-base counter reached its maximum value, software can write 1 to clear this bit
End of enumeration elements list.
CNTMAXF2 : PWM Channel 2 Time-base Counter Equal to 0xFFFF Latched Flag
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
indicates the time-base counter never reached its maximum value 0xFFFF
#1 : 1
indicates the time-base counter reached its maximum value, software can write 1 to clear this bit
End of enumeration elements list.
CNTMAXF3 : PWM Channel 3 Time-base Counter Equal to 0xFFFF Latched Flag
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
indicates the time-base counter never reached its maximum value 0xFFFF
#1 : 1
indicates the time-base counter reached its maximum value, software can write 1 to clear this bit
End of enumeration elements list.
CNTMAXF4 : PWM Channel 4 Time-base Counter Equal to 0xFFFF Latched Flag
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
indicates the time-base counter never reached its maximum value 0xFFFF
#1 : 1
indicates the time-base counter reached its maximum value, software can write 1 to clear this bit
End of enumeration elements list.
CNTMAXF5 : PWM Channel 5 Time-base Counter Equal to 0xFFFF Latched Flag
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
indicates the time-base counter never reached its maximum value 0xFFFF
#1 : 1
indicates the time-base counter reached its maximum value, software can write 1 to clear this bit
End of enumeration elements list.
SYNCINF0 : PWM Channel 0 Input Synchronization Latched Flag
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates no SYNC_IN event has occurred
#1 : 1
Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit
End of enumeration elements list.
SYNCINF2 : PWM Channel 2 Input Synchronization Latched Flag
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates no SYNC_IN event has occurred
#1 : 1
Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit
End of enumeration elements list.
SYNCINF4 : PWM Channel 4 Input Synchronization Latched Flag
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates no SYNC_IN event has occurred
#1 : 1
Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit
End of enumeration elements list.
ADCTRGF0 : PWM Channel 0 EADC Start of Conversion Flag
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates no EADC start of conversion trigger event has occurred
#1 : 1
Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit
End of enumeration elements list.
ADCTRGF1 : PWM Channel 1 EADC Start of Conversion Flag
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates no EADC start of conversion trigger event has occurred
#1 : 1
Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit
End of enumeration elements list.
ADCTRGF2 : PWM Channel 2 EADC Start of Conversion Flag
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates no EADC start of conversion trigger event has occurred
#1 : 1
Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit
End of enumeration elements list.
ADCTRGF3 : PWM Channel 3 EADC Start of Conversion Flag
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates no EADC start of conversion trigger event has occurred
#1 : 1
Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit
End of enumeration elements list.
ADCTRGF4 : PWM Channel 4 EADC Start of Conversion Flag
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates no EADC start of conversion trigger event has occurred
#1 : 1
Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit
End of enumeration elements list.
ADCTRGF5 : PWM Channel 5 EADC Start of Conversion Flag
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates no EADC start of conversion trigger event has occurred
#1 : 1
Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit
End of enumeration elements list.
PWM Clock Pre-scale Register 0/1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKPSC : PWM Counter Clock Pre-scale
The clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1).
bits : 0 - 11 (12 bit)
access : read-write
PWM Clock Pre-scale Register 2/3
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Clock Pre-scale Register 4/5
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Counter Enable Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTEN0 : PWM Channel 0 Counter Enable Bits
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Counter and clock prescaler Stop Running
#1 : 1
PWM Counter and clock prescaler Start Running
End of enumeration elements list.
CNTEN1 : PWM Channel 1 Counter Enable Bits
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Counter and clock prescaler Stop Running
#1 : 1
PWM Counter and clock prescaler Start Running
End of enumeration elements list.
CNTEN2 : PWM Channel 2 Counter Enable Bits
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Counter and clock prescaler Stop Running
#1 : 1
PWM Counter and clock prescaler Start Running
End of enumeration elements list.
CNTEN3 : PWM Channel 3 Counter Enable Bits
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Counter and clock prescaler Stop Running
#1 : 1
PWM Counter and clock prescaler Start Running
End of enumeration elements list.
CNTEN4 : PWM Channel 4 Counter Enable Bits
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Counter and clock prescaler Stop Running
#1 : 1
PWM Counter and clock prescaler Start Running
End of enumeration elements list.
CNTEN5 : PWM Channel 5 Counter Enable Bits
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Counter and clock prescaler Stop Running
#1 : 1
PWM Counter and clock prescaler Start Running
End of enumeration elements list.
PWM Capture Input Enable Register
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPINEN0 : PWM Channel 0 Capture Input Enable Bits
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#1 : 1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
CAPINEN1 : PWM Channel 1 Capture Input Enable Bits
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#1 : 1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
CAPINEN2 : PWM Channel 2 Capture Input Enable Bits
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#1 : 1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
CAPINEN3 : PWM Channel 3 Capture Input Enable Bits
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#1 : 1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
CAPINEN4 : PWM Channel 4 Capture Input Enable Bits
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#1 : 1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
CAPINEN5 : PWM Channel 5 Capture Input Enable Bits
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#1 : 1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
PWM Capture Control Register
address_offset : 0x204 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPEN0 : PWM Channel 0 Capture Function Enable Bits
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#1 : 1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
End of enumeration elements list.
CAPEN1 : PWM Channel 1 Capture Function Enable Bits
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#1 : 1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
End of enumeration elements list.
CAPEN2 : PWM Channel 2 Capture Function Enable Bits
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#1 : 1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
End of enumeration elements list.
CAPEN3 : PWM Channel 3 Capture Function Enable Bits
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#1 : 1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
End of enumeration elements list.
CAPEN4 : PWM Channel 4 Capture Function Enable Bits
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#1 : 1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
End of enumeration elements list.
CAPEN5 : PWM Channel 5 Capture Function Enable Bits
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#1 : 1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
End of enumeration elements list.
CAPINV0 : PWM Channel 0 Capture Inverter Enable Bits
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
CAPINV1 : PWM Channel 1 Capture Inverter Enable Bits
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
CAPINV2 : PWM Channel 2 Capture Inverter Enable Bits
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
CAPINV3 : PWM Channel 3 Capture Inverter Enable Bits
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
CAPINV4 : PWM Channel 4 Capture Inverter Enable Bits
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
CAPINV5 : PWM Channel 5 Capture Inverter Enable Bits
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
RCRLDEN0 : PWM Channel 0 Rising Capture Reload Enable Bits
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
RCRLDEN1 : PWM Channel 1 Rising Capture Reload Enable Bits
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
RCRLDEN2 : PWM Channel 2 Rising Capture Reload Enable Bits
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
RCRLDEN3 : PWM Channel 3 Rising Capture Reload Enable Bits
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
RCRLDEN4 : PWM Channel 4 Rising Capture Reload Enable Bits
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
RCRLDEN5 : PWM Channel 5 Rising Capture Reload Enable Bits
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
FCRLDEN0 : PWM Channel 0 Falling Capture Reload Enable Bits
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
FCRLDEN1 : PWM Channel 1 Falling Capture Reload Enable Bits
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
FCRLDEN2 : PWM Channel 2 Falling Capture Reload Enable Bits
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
FCRLDEN3 : PWM Channel 3 Falling Capture Reload Enable Bits
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
FCRLDEN4 : PWM Channel 4 Falling Capture Reload Enable Bits
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
FCRLDEN5 : PWM Channel 5 Falling Capture Reload Enable Bits
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
PWM Capture Status Register
address_offset : 0x208 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CRLIFOV0 : PWM Channel 0 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CRLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CRLIF.
bits : 0 - 0 (1 bit)
access : read-only
CRLIFOV1 : PWM Channel 1 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CRLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CRLIF.
bits : 1 - 1 (1 bit)
access : read-only
CRLIFOV2 : PWM Channel 2 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CRLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CRLIF.
bits : 2 - 2 (1 bit)
access : read-only
CRLIFOV3 : PWM Channel 3 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CRLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CRLIF.
bits : 3 - 3 (1 bit)
access : read-only
CRLIFOV4 : PWM Channel 4 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CRLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CRLIF.
bits : 4 - 4 (1 bit)
access : read-only
CRLIFOV5 : PWM Channel 5 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CRLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CRLIF.
bits : 5 - 5 (1 bit)
access : read-only
CFLIFOV0 : PWM Channel 0 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CFLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CFLIF.
bits : 8 - 8 (1 bit)
access : read-only
CFLIFOV1 : PWM Channel 1 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CFLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CFLIF.
bits : 9 - 9 (1 bit)
access : read-only
CFLIFOV2 : PWM Channel 2 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CFLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CFLIF.
bits : 10 - 10 (1 bit)
access : read-only
CFLIFOV3 : PWM Channel 3 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CFLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CFLIF.
bits : 11 - 11 (1 bit)
access : read-only
CFLIFOV4 : PWM Channel 4 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CFLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CFLIF.
bits : 12 - 12 (1 bit)
access : read-only
CFLIFOV5 : PWM Channel 5 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CFLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CFLIF.
bits : 13 - 13 (1 bit)
access : read-only
PWM Rising Capture Data Register 0
address_offset : 0x20C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RCAPDAT : PWM Rising Capture Data Register (Read Only)
When rising capture condition happened, the PWM counter value will be saved in this register.
bits : 0 - 15 (16 bit)
access : read-only
PWM Falling Capture Data Register 0
address_offset : 0x210 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FCAPDAT : PWM Falling Capture Data Register (Read Only)
When falling capture condition happened, the PWM counter value will be saved in this register.
bits : 0 - 15 (16 bit)
access : read-only
PWM Rising Capture Data Register 1
address_offset : 0x214 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Falling Capture Data Register 1
address_offset : 0x218 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Rising Capture Data Register 2
address_offset : 0x21C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Falling Capture Data Register 2
address_offset : 0x220 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Rising Capture Data Register 3
address_offset : 0x224 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Falling Capture Data Register 3
address_offset : 0x228 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Rising Capture Data Register 4
address_offset : 0x22C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Falling Capture Data Register 4
address_offset : 0x230 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Rising Capture Data Register 5
address_offset : 0x234 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Falling Capture Data Register 5
address_offset : 0x238 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM PDMA Control Register
address_offset : 0x23C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN0_1 : Channel 0/1 PDMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel 0/1 PDMA function Disabled
#1 : 1
Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory
End of enumeration elements list.
CAPMOD0_1 : Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reserved. Do not use
#01 : 1
PWM_RCAPDAT0/1
#10 : 2
PWM_FCAPDAT0/1
#11 : 3
Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1
End of enumeration elements list.
CAPORD0_1 : Capture Channel 0/1 Rising/Falling Order
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_FCAPDAT0/1 is the first captured data to memory
#1 : 1
PWM_RCAPDAT0/1 is the first captured data to memory
End of enumeration elements list.
CHSEL0_1 : Select Channel 0/1 to Do PDMA Transfer
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel0
#1 : 1
Channel1
End of enumeration elements list.
CHEN2_3 : Channel 2/3 PDMA Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel 2/3 PDMA function Disabled
#1 : 1
Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory
End of enumeration elements list.
CAPMOD2_3 : Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reserved. Do not use
#01 : 1
PWM_RCAPDAT2/3
#10 : 2
PWM_FCAPDAT2/3
#11 : 3
Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3
End of enumeration elements list.
CAPORD2_3 : Capture Channel 2/3 Rising/Falling Order
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_FCAPDAT2/3 is the first captured data to memory
#1 : 1
PWM_RCAPDAT2/3 is the first captured data to memory
End of enumeration elements list.
CHSEL2_3 : Select Channel 2/3 to Do PDMA Transfer
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel2
#1 : 1
Channel3
End of enumeration elements list.
CHEN4_5 : Channel 4/5 PDMA Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel 4/5 PDMA function Disabled
#1 : 1
Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory
End of enumeration elements list.
CAPMOD4_5 : Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reserved. Do not use
#01 : 1
PWM_RCAPDAT4/5
#10 : 2
PWM_FCAPDAT4/5
#11 : 3
Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5
End of enumeration elements list.
CAPORD4_5 : Capture Channel 4/5 Rising/Falling Order
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_FCAPDAT4/5 is the first captured data to memory
#1 : 1
PWM_RCAPDAT4/5 is the first captured data to memory
End of enumeration elements list.
CHSEL4_5 : Select Channel 4/5 to Do PDMA Transfer
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel4
#1 : 1
Channel5
End of enumeration elements list.
PWM Clear Counter Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTCLR0 : PWM Channel 0 Clear PWM Counter Control Bit
It is automatically cleared by hardware.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear 16-bit PWM counter to 0000H
End of enumeration elements list.
CNTCLR1 : PWM Channel 1 Clear PWM Counter Control Bit
It is automatically cleared by hardware.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear 16-bit PWM counter to 0000H
End of enumeration elements list.
CNTCLR2 : PWM Channel 2 Clear PWM Counter Control Bit
It is automatically cleared by hardware.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear 16-bit PWM counter to 0000H
End of enumeration elements list.
CNTCLR3 : PWM Channel 3 Clear PWM Counter Control Bit
It is automatically cleared by hardware.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear 16-bit PWM counter to 0000H
End of enumeration elements list.
CNTCLR4 : PWM Channel 4 Clear PWM Counter Control Bit
It is automatically cleared by hardware.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear 16-bit PWM counter to 0000H
End of enumeration elements list.
CNTCLR5 : PWM Channel 5 Clear PWM Counter Control Bit
It is automatically cleared by hardware.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear 16-bit PWM counter to 0000H
End of enumeration elements list.
PWM Capture Channel 01 PDMA Register
address_offset : 0x240 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPBUF : PWM Capture PDMA Register (Read Only)
This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.
bits : 0 - 15 (16 bit)
access : read-only
PWM Capture Channel 23 PDMA Register
address_offset : 0x244 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Capture Channel 45 PDMA Register
address_offset : 0x248 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Capture Interrupt Enable Register
address_offset : 0x250 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPRIEN0 : PWM Channel 0 Capture Rising Latch Interrupt Enable Bits
Note: When Capture with PDMA operating, CINTENR corresponding channel CAPRIEN must be disabled.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture rising edge latch interrupt Disabled
#1 : 1
Capture rising edge latch interrupt Enabled
End of enumeration elements list.
CAPRIEN1 : PWM Channel 1 Capture Rising Latch Interrupt Enable Bits
Note: When Capture with PDMA operating, CINTENR corresponding channel CAPRIEN must be disabled.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture rising edge latch interrupt Disabled
#1 : 1
Capture rising edge latch interrupt Enabled
End of enumeration elements list.
CAPRIEN2 : PWM Channel 2 Capture Rising Latch Interrupt Enable Bits
Note: When Capture with PDMA operating, CINTENR corresponding channel CAPRIEN must be disabled.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture rising edge latch interrupt Disabled
#1 : 1
Capture rising edge latch interrupt Enabled
End of enumeration elements list.
CAPRIEN3 : PWM Channel 3 Capture Rising Latch Interrupt Enable Bits
Note: When Capture with PDMA operating, CINTENR corresponding channel CAPRIEN must be disabled.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture rising edge latch interrupt Disabled
#1 : 1
Capture rising edge latch interrupt Enabled
End of enumeration elements list.
CAPRIEN4 : PWM Channel 4 Capture Rising Latch Interrupt Enable Bits
Note: When Capture with PDMA operating, CINTENR corresponding channel CAPRIEN must be disabled.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture rising edge latch interrupt Disabled
#1 : 1
Capture rising edge latch interrupt Enabled
End of enumeration elements list.
CAPRIEN5 : PWM Channel 5 Capture Rising Latch Interrupt Enable Bits
Note: When Capture with PDMA operating, CINTENR corresponding channel CAPRIEN must be disabled.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture rising edge latch interrupt Disabled
#1 : 1
Capture rising edge latch interrupt Enabled
End of enumeration elements list.
CAPFIEN0 : PWM Channel 0 Capture Falling Latch Interrupt Enable Bits
Note: When Capture with PDMA operating, CINTENR corresponding channel CAPFIEN must be disabled.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture falling edge latch interrupt Disabled
#1 : 1
Capture falling edge latch interrupt Enabled
End of enumeration elements list.
CAPFIEN1 : PWM Channel 1 Capture Falling Latch Interrupt Enable Bits
Note: When Capture with PDMA operating, CINTENR corresponding channel CAPFIEN must be disabled.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture falling edge latch interrupt Disabled
#1 : 1
Capture falling edge latch interrupt Enabled
End of enumeration elements list.
CAPFIEN2 : PWM Channel 2 Capture Falling Latch Interrupt Enable Bits
Note: When Capture with PDMA operating, CINTENR corresponding channel CAPFIEN must be disabled.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture falling edge latch interrupt Disabled
#1 : 1
Capture falling edge latch interrupt Enabled
End of enumeration elements list.
CAPFIEN3 : PWM Channel 3 Capture Falling Latch Interrupt Enable Bits
Note: When Capture with PDMA operating, CINTENR corresponding channel CAPFIEN must be disabled.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture falling edge latch interrupt Disabled
#1 : 1
Capture falling edge latch interrupt Enabled
End of enumeration elements list.
CAPFIEN4 : PWM Channel 4 Capture Falling Latch Interrupt Enable Bits
Note: When Capture with PDMA operating, CINTENR corresponding channel CAPFIEN must be disabled.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture falling edge latch interrupt Disabled
#1 : 1
Capture falling edge latch interrupt Enabled
End of enumeration elements list.
CAPFIEN5 : PWM Channel 5 Capture Falling Latch Interrupt Enable Bits
Note: When Capture with PDMA operating, CINTENR corresponding channel CAPFIEN must be disabled.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture falling edge latch interrupt Disabled
#1 : 1
Capture falling edge latch interrupt Enabled
End of enumeration elements list.
PWM Capture Interrupt Flag Register
address_offset : 0x254 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRLIF0 : PWM Channel 0 Capture Rising Latch Interrupt Flag
This bit is writing 1 to clear.
Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CRLIF1 : PWM Channel 1 Capture Rising Latch Interrupt Flag
This bit is writing 1 to clear.
Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CRLIF2 : PWM Channel 2 Capture Rising Latch Interrupt Flag
This bit is writing 1 to clear.
Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CRLIF3 : PWM Channel 3 Capture Rising Latch Interrupt Flag
This bit is writing 1 to clear.
Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CRLIF4 : PWM Channel 4 Capture Rising Latch Interrupt Flag
This bit is writing 1 to clear.
Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CRLIF5 : PWM Channel 5 Capture Rising Latch Interrupt Flag
This bit is writing 1 to clear.
Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CFLIF0 : PWM Channel 0 Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear.
Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
CFLIF1 : PWM Channel 1 Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear.
Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
CFLIF2 : PWM Channel 2 Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear.
Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
CFLIF3 : PWM Channel 3 Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear.
Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
CFLIF4 : PWM Channel 4 Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear.
Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
CFLIF5 : PWM Channel 5 Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear.
Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
PWM Load Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOAD0 : PWM Channel 0 Re-load PWM Comparator Register (CMPDAT) Control Bit
This bit is software write, hardware clear when current PWM period end.
Write Operation:
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
No load window is set
#1 : 1
Set load window of window loading mode.
Load window is set
End of enumeration elements list.
LOAD1 : PWM Channel 1 Re-load PWM Comparator Register (CMPDAT) Control Bit
This bit is software write, hardware clear when current PWM period end.
Write Operation:
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
No load window is set
#1 : 1
Set load window of window loading mode.
Load window is set
End of enumeration elements list.
LOAD2 : PWM Channel 2 Re-load PWM Comparator Register (CMPDAT) Control Bit
This bit is software write, hardware clear when current PWM period end.
Write Operation:
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
No load window is set
#1 : 1
Set load window of window loading mode.
Load window is set
End of enumeration elements list.
LOAD3 : PWM Channel 3 Re-load PWM Comparator Register (CMPDAT) Control Bit
This bit is software write, hardware clear when current PWM period end.
Write Operation:
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
No load window is set
#1 : 1
Set load window of window loading mode.
Load window is set
End of enumeration elements list.
LOAD4 : PWM Channel 4 Re-load PWM Comparator Register (CMPDAT) Control Bit
This bit is software write, hardware clear when current PWM period end.
Write Operation:
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
No load window is set
#1 : 1
Set load window of window loading mode.
Load window is set
End of enumeration elements list.
LOAD5 : PWM Channel 5 Re-load PWM Comparator Register (CMPDAT) Control Bit
This bit is software write, hardware clear when current PWM period end.
Write Operation:
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
No load window is set
#1 : 1
Set load window of window loading mode.
Load window is set
End of enumeration elements list.
PWM Period Register 0
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : PWM Period Register
Up-Count mode: In this mode, PWM counter counts from 0 to PERIOD, and restarts from 0.
Down-Count mode: In this mode, PWM counter counts from PERIOD to 0, and restarts from PERIOD.
bits : 0 - 15 (16 bit)
access : read-write
PWM PERIOD0 Buffer
address_offset : 0x304 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PBUF : PWM Period Register Buffer (Read Only)
Used as PERIOD active register.
bits : 0 - 15 (16 bit)
access : read-only
PWM PERIOD1 Buffer
address_offset : 0x308 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM PERIOD2 Buffer
address_offset : 0x30C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM PERIOD3 Buffer
address_offset : 0x310 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM PERIOD4 Buffer
address_offset : 0x314 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM PERIOD5 Buffer
address_offset : 0x318 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM CMPDAT0 Buffer
address_offset : 0x31C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMPBUF : PWM Comparator Register Buffer (Read Only)
Used as CMP active register.
bits : 0 - 15 (16 bit)
access : read-only
PWM CMPDAT1 Buffer
address_offset : 0x320 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM CMPDAT2 Buffer
address_offset : 0x324 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM CMPDAT3 Buffer
address_offset : 0x328 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM CMPDAT4 Buffer
address_offset : 0x32C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM CMPDAT5 Buffer
address_offset : 0x330 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM CLKPSC0_1 Buffer
address_offset : 0x334 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPSCBUF : PWM Counter Clock Pre-scale Buffer
Use as PWM counter clock pre-scare active register.
bits : 0 - 11 (12 bit)
access : read-only
PWM CLKPSC2_3 Buffer
address_offset : 0x338 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM CLKPSC4_5 Buffer
address_offset : 0x33C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Period Register 1
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM FTCMPDAT0_1 Buffer
address_offset : 0x340 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FTCMPBUF : PWM FTCMPDAT Buffer (Read Only)
Used as FTCMPDAT active register.
bits : 0 - 15 (16 bit)
access : read-only
PWM FTCMPDAT2_3 Buffer
address_offset : 0x344 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM FTCMPDAT4_5 Buffer
address_offset : 0x348 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM FTCMPDAT Indicator Register
address_offset : 0x34C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTCMU0 : PWM Channel 0 FTCMPDAT Up Indicator
bits : 0 - 0 (1 bit)
access : read-write
FTCMU2 : PWM Channel 2 FTCMPDAT Up Indicator
bits : 1 - 1 (1 bit)
access : read-write
FTCMU4 : PWM Channel 4 FTCMPDAT Up Indicator
bits : 2 - 2 (1 bit)
access : read-write
FTCMD0 : PWM Channel 0 FTCMPDAT Down Indicator
bits : 8 - 8 (1 bit)
access : read-write
FTCMD2 : PWM Channel 2 FTCMPDAT Down Indicator
bits : 9 - 9 (1 bit)
access : read-write
FTCMD4 : PWM Channel 4 FTCMPDAT Down Indicator
bits : 10 - 10 (1 bit)
access : read-write
PWM Period Register 2
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Period Register 3
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Control Register 1
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTTYPE0 : PWM Channel 0 Counter Behavior Type
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Up counter type (supports in capture mode)
#01 : 1
Down count type (supports in capture mode)
#10 : 2
Up-down counter type
#11 : 3
Reserved. Do not use
End of enumeration elements list.
CNTTYPE1 : PWM Channel 1 Counter Behavior Type
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Up counter type (supports in capture mode)
#01 : 1
Down count type (supports in capture mode)
#10 : 2
Up-down counter type
#11 : 3
Reserved. Do not use
End of enumeration elements list.
CNTTYPE2 : PWM Channel 2 Counter Behavior Type
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Up counter type (supports in capture mode)
#01 : 1
Down count type (supports in capture mode)
#10 : 2
Up-down counter type
#11 : 3
Reserved. Do not use
End of enumeration elements list.
CNTTYPE3 : PWM Channel 3 Counter Behavior Type
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Up counter type (supports in capture mode)
#01 : 1
Down count type (supports in capture mode)
#10 : 2
Up-down counter type
#11 : 3
Reserved. Do not use
End of enumeration elements list.
CNTTYPE4 : PWM Channel 4 Counter Behavior Type
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Up counter type (supports in capture mode)
#01 : 1
Down count type (supports in capture mode)
#10 : 2
Up-down counter type
#11 : 3
Reserved. Do not use
End of enumeration elements list.
CNTTYPE5 : PWM Channel 5 Counter Behavior Type
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Up counter type (supports in capture mode)
#01 : 1
Down count type (supports in capture mode)
#10 : 2
Up-down counter type
#11 : 3
Reserved. Do not use
End of enumeration elements list.
CNTMODE0 : PWM Channel 0 Counter Mode
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-reload mode
#1 : 1
One-shot mode
End of enumeration elements list.
CNTMODE1 : PWM Channel 1 Counter Mode
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-reload mode
#1 : 1
One-shot mode
End of enumeration elements list.
CNTMODE2 : PWM Channel 2 Counter Mode
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-reload mode
#1 : 1
One-shot mode
End of enumeration elements list.
CNTMODE3 : PWM Channel 3 Counter Mode
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-reload mode
#1 : 1
One-shot mode
End of enumeration elements list.
CNTMODE4 : PWM Channel 4 Counter Mode
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-reload mode
#1 : 1
One-shot mode
End of enumeration elements list.
CNTMODE5 : PWM Channel 5 Counter Mode
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-reload mode
#1 : 1
One-shot mode
End of enumeration elements list.
OUTMODE0 : PWM Channel 0 Output Mode
Note: When operating in group function, these bits must all set to the same mode.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM independent mode
#1 : 1
PWM complementary mode
End of enumeration elements list.
OUTMODE2 : PWM Channel 2 Output Mode
Note: When operating in group function, these bits must all set to the same mode.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM independent mode
#1 : 1
PWM complementary mode
End of enumeration elements list.
OUTMODE4 : PWM Channel 4 Output Mode
Note: When operating in group function, these bits must all set to the same mode.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM independent mode
#1 : 1
PWM complementary mode
End of enumeration elements list.
PWM Period Register 4
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Period Register 5
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 0
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP : PWM Comparator Register
CMP use to compare with CNTR to generate PWM waveform, interrupt and trigger EADC.
In independent mode, CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.
In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
bits : 0 - 15 (16 bit)
access : read-write
PWM Comparator Register 1
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 2
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 3
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 4
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 5
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Dead-time Control Register 0/1
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTCNT : Dead-time Counter (Write Protected)
The dead-time can be calculated from the following formula:
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 0 - 11 (12 bit)
access : read-write
DTEN : Enable Dead-time Insertion for PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protected)
Dead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dead-time insertion Disabled on the pin pair
#1 : 1
Dead-time insertion Enabled on the pin pair
End of enumeration elements list.
DTCKSEL : Dead-time Clock Select (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dead-time clock source from PWM_CLK
#1 : 1
Dead-time clock source from prescaler output
End of enumeration elements list.
PWM Dead-time Control Register 2/3
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Dead-time Control Register 4/5
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Synchronization Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHSEN0 : PWM Channel 0 SYNC Phase Enable Bits
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM counter disable to load PHS value
#1 : 1
PWM counter enable to load PHS value
End of enumeration elements list.
PHSEN2 : PWM Channel 2 SYNC Phase Enable Bits
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM counter disable to load PHS value
#1 : 1
PWM counter enable to load PHS value
End of enumeration elements list.
PHSEN4 : PWM Channel 4 SYNC Phase Enable Bits
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM counter disable to load PHS value
#1 : 1
PWM counter enable to load PHS value
End of enumeration elements list.
SINSRC0 : PWM Channel 0 PWM0_SYNC_IN Source Selection
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Synchronize source from SYNC_IN or SWSYNC
#01 : 1
Counter equal to 0
#10 : 2
Counter equal to PWM_CMPDATm, m denotes 1, 3, 5
#11 : 3
SYNC_OUT will not be generated
End of enumeration elements list.
SINSRC2 : PWM Channel 2 PWM0_SYNC_IN Source Selection
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Synchronize source from SYNC_IN or SWSYNC
#01 : 1
Counter equal to 0
#10 : 2
Counter equal to PWM_CMPDATm, m denotes 1, 3, 5
#11 : 3
SYNC_OUT will not be generated
End of enumeration elements list.
SINSRC4 : PWM Channel 4 PWM0_SYNC_IN Source Selection
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
Synchronize source from SYNC_IN or SWSYNC
#01 : 1
Counter equal to 0
#10 : 2
Counter equal to PWM_CMPDATm, m denotes 1, 3, 5
#11 : 3
SYNC_OUT will not be generated
End of enumeration elements list.
SNFLTEN : PWM0_SYNC_IN Noise Filter Enable Bits
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Noise filter of input pin PWM0_SYNC_IN is Disabled
#1 : 1
Noise filter of input pin PWM0_SYNC_IN is Enabled
End of enumeration elements list.
SFLTCSEL : SYNC Edge Detector Filter Clock Selection
bits : 17 - 19 (3 bit)
access : read-write
Enumeration:
#000 : 0
Filter clock = HCLK
#001 : 1
Filter clock = HCLK/2
#010 : 2
Filter clock = HCLK/4
#011 : 3
Filter clock = HCLK/8
#100 : 4
Filter clock = HCLK/16
#101 : 5
Filter clock = HCLK/32
#110 : 6
Filter clock = HCLK/64
#111 : 7
Filter clock = HCLK/128
End of enumeration elements list.
SFLTCNT : SYNC Edge Detector Filter Count
The register bits control the counter number of edge detector.
bits : 20 - 22 (3 bit)
access : read-write
SINPINV : SYNC Input Pin Inverse
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
The state of pin SYNC is passed to the negative edge detector
#1 : 1
The inversed state of pin SYNC is passed to the negative edge detector
End of enumeration elements list.
PHSDIR0 : PWM Channel 0 Phase Direction Control
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Control PWM counter count decrement after synchronizing
#1 : 1
Control PWM counter count increment after synchronizing
End of enumeration elements list.
PHSDIR2 : PWM Channel 2 Phase Direction Control
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Control PWM counter count decrement after synchronizing
#1 : 1
Control PWM counter count increment after synchronizing
End of enumeration elements list.
PHSDIR4 : PWM Channel 4 Phase Direction Control
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Control PWM counter count decrement after synchronizing
#1 : 1
Control PWM counter count increment after synchronizing
End of enumeration elements list.
PWM Counter Phase Register 0/1
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHS : PWM Synchronous Start Phase Bits
PHS determines the PWM synchronous start phase value. These bits only use in synchronous function.
bits : 0 - 15 (16 bit)
access : read-write
PWM Counter Phase Register 2/3
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Counter Phase Register 4/5
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Counter Register 0
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : PWM Data Register (Read Only)
User can monitor CNTR to know the current value in 16-bit period counter.
bits : 0 - 15 (16 bit)
access : read-only
DIRF : PWM Direction Indicator Flag (Read Only)
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Counter is Down count
#1 : 1
Counter is UP count
End of enumeration elements list.
PWM Counter Register 1
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Counter Register 2
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Counter Register 3
address_offset : 0x9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Counter Register 4
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Counter Register 5
address_offset : 0xA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Generation Register 0
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZPCTL0 : PWM Channel 0 Zero Point Control
PWM can control output level when PWM counter count to zero.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM zero point output Low
#10 : 2
PWM zero point output High
#11 : 3
PWM zero point output Toggle
End of enumeration elements list.
ZPCTL1 : PWM Channel 1 Zero Point Control
PWM can control output level when PWM counter count to zero.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM zero point output Low
#10 : 2
PWM zero point output High
#11 : 3
PWM zero point output Toggle
End of enumeration elements list.
ZPCTL2 : PWM Channel 2 Zero Point Control
PWM can control output level when PWM counter count to zero.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM zero point output Low
#10 : 2
PWM zero point output High
#11 : 3
PWM zero point output Toggle
End of enumeration elements list.
ZPCTL3 : PWM Channel 3 Zero Point Control
PWM can control output level when PWM counter count to zero.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM zero point output Low
#10 : 2
PWM zero point output High
#11 : 3
PWM zero point output Toggle
End of enumeration elements list.
ZPCTL4 : PWM Channel 4 Zero Point Control
PWM can control output level when PWM counter count to zero.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM zero point output Low
#10 : 2
PWM zero point output High
#11 : 3
PWM zero point output Toggle
End of enumeration elements list.
ZPCTL5 : PWM Channel 5 Zero Point Control
PWM can control output level when PWM counter count to zero.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM zero point output Low
#10 : 2
PWM zero point output High
#11 : 3
PWM zero point output Toggle
End of enumeration elements list.
PRDPCTL0 : PWM Channel 0 Period (Center) Point Control
PWM can control output level when PWM counter count to (PERIODn+1).
Note: This bit is center point control when PWM counter operating in up-down counter type.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM period (center) point output Low
#10 : 2
PWM period (center) point output High
#11 : 3
PWM period (center) point output Toggle
End of enumeration elements list.
PRDPCTL1 : PWM Channel 1 Period (Center) Point Control
PWM can control output level when PWM counter count to (PERIODn+1).
Note: This bit is center point control when PWM counter operating in up-down counter type.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM period (center) point output Low
#10 : 2
PWM period (center) point output High
#11 : 3
PWM period (center) point output Toggle
End of enumeration elements list.
PRDPCTL2 : PWM Channel 2 Period (Center) Point Control
PWM can control output level when PWM counter count to (PERIODn+1).
Note: This bit is center point control when PWM counter operating in up-down counter type.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM period (center) point output Low
#10 : 2
PWM period (center) point output High
#11 : 3
PWM period (center) point output Toggle
End of enumeration elements list.
PRDPCTL3 : PWM Channel 3 Period (Center) Point Control
PWM can control output level when PWM counter count to (PERIODn+1).
Note: This bit is center point control when PWM counter operating in up-down counter type.
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM period (center) point output Low
#10 : 2
PWM period (center) point output High
#11 : 3
PWM period (center) point output Toggle
End of enumeration elements list.
PRDPCTL4 : PWM Channel 4 Period (Center) Point Control
PWM can control output level when PWM counter count to (PERIODn+1).
Note: This bit is center point control when PWM counter operating in up-down counter type.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM period (center) point output Low
#10 : 2
PWM period (center) point output High
#11 : 3
PWM period (center) point output Toggle
End of enumeration elements list.
PRDPCTL5 : PWM Channel 5 Period (Center) Point Control
PWM can control output level when PWM counter count to (PERIODn+1).
Note: This bit is center point control when PWM counter operating in up-down counter type.
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM period (center) point output Low
#10 : 2
PWM period (center) point output High
#11 : 3
PWM period (center) point output Toggle
End of enumeration elements list.
PWM Generation Register 1
address_offset : 0xB4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPUCTL0 : PWM Channel 0 Compare Up Point Control
PWM can control output level when PWM counter up count to CMPDAT.
Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare up point output Low
#10 : 2
PWM compare up point output High
#11 : 3
PWM compare up point output Toggle
End of enumeration elements list.
CMPUCTL1 : PWM Channel 1 Compare Up Point Control
PWM can control output level when PWM counter up count to CMPDAT.
Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare up point output Low
#10 : 2
PWM compare up point output High
#11 : 3
PWM compare up point output Toggle
End of enumeration elements list.
CMPUCTL2 : PWM Channel 2 Compare Up Point Control
PWM can control output level when PWM counter up count to CMPDAT.
Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare up point output Low
#10 : 2
PWM compare up point output High
#11 : 3
PWM compare up point output Toggle
End of enumeration elements list.
CMPUCTL3 : PWM Channel 3 Compare Up Point Control
PWM can control output level when PWM counter up count to CMPDAT.
Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare up point output Low
#10 : 2
PWM compare up point output High
#11 : 3
PWM compare up point output Toggle
End of enumeration elements list.
CMPUCTL4 : PWM Channel 4 Compare Up Point Control
PWM can control output level when PWM counter up count to CMPDAT.
Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare up point output Low
#10 : 2
PWM compare up point output High
#11 : 3
PWM compare up point output Toggle
End of enumeration elements list.
CMPUCTL5 : PWM Channel 5 Compare Up Point Control
PWM can control output level when PWM counter up count to CMPDAT.
Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare up point output Low
#10 : 2
PWM compare up point output High
#11 : 3
PWM compare up point output Toggle
End of enumeration elements list.
CMPDCTL0 : PWM Channel 0 Compare Down Point Control
PWM can control output level when PWM counter down count to CMPDAT.
Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare down point output Low
#10 : 2
PWM compare down point output High
#11 : 3
PWM compare down point output Toggle
End of enumeration elements list.
CMPDCTL1 : PWM Channel 1 Compare Down Point Control
PWM can control output level when PWM counter down count to CMPDAT.
Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare down point output Low
#10 : 2
PWM compare down point output High
#11 : 3
PWM compare down point output Toggle
End of enumeration elements list.
CMPDCTL2 : PWM Channel 2 Compare Down Point Control
PWM can control output level when PWM counter down count to CMPDAT.
Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare down point output Low
#10 : 2
PWM compare down point output High
#11 : 3
PWM compare down point output Toggle
End of enumeration elements list.
CMPDCTL3 : PWM Channel 3 Compare Down Point Control
PWM can control output level when PWM counter down count to CMPDAT.
Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare down point output Low
#10 : 2
PWM compare down point output High
#11 : 3
PWM compare down point output Toggle
End of enumeration elements list.
CMPDCTL4 : PWM Channel 4 Compare Down Point Control
PWM can control output level when PWM counter down count to CMPDAT.
Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare down point output Low
#10 : 2
PWM compare down point output High
#11 : 3
PWM compare down point output Toggle
End of enumeration elements list.
CMPDCTL5 : PWM Channel 5 Compare Down Point Control
PWM can control output level when PWM counter down count to CMPDAT.
Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare down point output Low
#10 : 2
PWM compare down point output High
#11 : 3
PWM compare down point output Toggle
End of enumeration elements list.
PWM Mask Enable Register
address_offset : 0xB8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSKEN0 : PWM Channel 0 Mask Enable Bits
The PWM output signal will be masked when this bit is enabled.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output signal is non-masked
#1 : 1
PWM output signal is masked and output MSKDAT0 (PWM_MSK[0]) data
End of enumeration elements list.
MSKEN1 : PWM Channel 1 Mask Enable Bits
The PWM output signal will be masked when this bit is enabled and output MSKDAT1 (PWM_MSK[1]) data.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output signal is non-masked
#1 : 1
PWM output signal is masked and output MSKDAT1 (PWM_MSK[1]) data
End of enumeration elements list.
MSKEN2 : PWM Channel 2 Mask Enable Bits
The PWM output signal will be masked when this bit is enabled and output MSKDAT2 (PWM_MSK[2]) data.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output signal is non-masked
#1 : 1
PWM output signal is masked and output MSKDAT2 (PWM_MSK[2]) data
End of enumeration elements list.
MSKEN3 : PWM Channel 3 Mask Enable Bits
The PWM output signal will be masked when this bit is enabled and output MSKDAT3 (PWM_MSK[3]) data.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output signal is non-masked
#1 : 1
PWM output signal is masked and output MSKDAT3 (PWM_MSK[3]) data
End of enumeration elements list.
MSKEN4 : PWM Channel 4 Mask Enable Bits
The PWM output signal will be masked when this bit is enabled and output MSKDAT4 (PWM_MSK[4]) data.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output signal is non-masked
#1 : 1
PWM output signal is masked and output MSKDAT4 (PWM_MSK[4]) data
End of enumeration elements list.
MSKEN5 : PWM Channel 5 Mask Enable Bits
The PWM output signal will be masked when this bit is enabled and output MSKDAT5 (PWM_MSK[5]) data.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output signal is non-masked
#1 : 1
PWM output signal is masked and output MSKDAT5 (PWM_MSK[5]) data
End of enumeration elements list.
PWM Mask Data Register
address_offset : 0xBC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSKDAT0 : PWM Channel 0 Mask Data Bit
This bit control the state of output pin, if MSKEN0 (PWM_MSKEN[0]) is enabled.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to PWM0
#1 : 1
Output logic high to PWM0
End of enumeration elements list.
MSKDAT1 : PWM Channel 1 Mask Data Bit
This bit control the state of output pin, if MSKEN1 (PWM_MSKEN[1]) is enabled.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to PWM1
#1 : 1
Output logic high to PWM1
End of enumeration elements list.
MSKDAT2 : PWM Channel 2 Mask Data Bit
This bit control the state of output pin, if MSKEN2 (PWM_MSKEN[2]) is enabled.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to PWM2
#1 : 1
Output logic high to PWM2
End of enumeration elements list.
MSKDAT3 : PWM Channel 3 Mask Data Bit
This bit control the state of output pin, if MSKEN3 (PWM_MSKEN[3]) is enabled.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to PWM3
#1 : 1
Output logic high to PWM3
End of enumeration elements list.
MSKDAT4 : PWM Channel 4 Mask Data Bit
This bit control the state of output pin, if MSKEN4 (PWM_MSKEN[4]) is enabled.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to PWM4
#1 : 1
Output logic high to PWM4
End of enumeration elements list.
MSKDAT5 : PWM Channel 5 Mask Data Bit
This bit control the state of output pin, if MSKEN5 (PWM_MSKEN[5]) is enabled.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to PWM5
#1 : 1
Output logic high to PWM5
End of enumeration elements list.
PWM Software Control Synchronization Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWSYNC0 : PWM Channel 0 Software SYNC Function
When SINSRC0 (PWM_SYNC[9:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
bits : 0 - 0 (1 bit)
access : read-write
SWSYNC2 : PWM Channel 2 Software SYNC Function
When SINSRC2 (PWM_SYNC[11:10]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
bits : 1 - 1 (1 bit)
access : read-write
SWSYNC4 : PWM Channel 4 Software SYNC Function
When SINSRC4 (PWM_SYNC[13:12]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
bits : 2 - 2 (1 bit)
access : read-write
PWM Brake Noise Filter Register
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRK0NFEN : PWM Brake 0 Noise Filter Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Noise filter of PWM Brake 0 Disabled
#1 : 1
Noise filter of PWM Brake 0 Enabled
End of enumeration elements list.
BRK0NFSEL : Brake 0 Edge Detector Filter Clock Selection
bits : 1 - 3 (3 bit)
access : read-write
Enumeration:
#000 : 0
Filter clock = HCLK
#001 : 1
Filter clock = HCLK/2
#010 : 2
Filter clock = HCLK/4
#011 : 3
Filter clock = HCLK/8
#100 : 4
Filter clock = HCLK/16
#101 : 5
Filter clock = HCLK/32
#110 : 6
Filter clock = HCLK/64
#111 : 7
Filter clock = HCLK/128
End of enumeration elements list.
BRK0FCNT : Brake 0 Edge Detector Filter Count
The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT.
bits : 4 - 6 (3 bit)
access : read-write
BRK0PINV : Brake 0 Pin Inverse
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The state of pin PWM0_BRAKE0 is passed to the negative edge detector
#1 : 1
The inversed state of pin PWM0_BRAKE1 is passed to the negative edge detector
End of enumeration elements list.
BRK1NFEN : PWM Brake 1 Noise Filter Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Noise filter of PWM Brake 1 Disabled
#1 : 1
Noise filter of PWM Brake 1 Enabled
End of enumeration elements list.
BRK1NFSEL : Brake 1 Edge Detector Filter Clock Selection
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
#000 : 0
Filter clock = HCLK
#001 : 1
Filter clock = HCLK/2
#010 : 2
Filter clock = HCLK/4
#011 : 3
Filter clock = HCLK/8
#100 : 4
Filter clock = HCLK/16
#101 : 5
Filter clock = HCLK/32
#110 : 6
Filter clock = HCLK/64
#111 : 7
Filter clock = HCLK/128
End of enumeration elements list.
BRK1FCNT : Brake 1 Edge Detector Filter Count
The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT.
bits : 12 - 14 (3 bit)
access : read-write
BRK1PINV : Brake 1 Pin Inverse
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The state of pin PWM0_BRAKE1 is passed to the negative edge detector
#1 : 1
The inversed state of pin PWM0_BRAKE1 is passed to the negative edge detector
End of enumeration elements list.
PWM System Fail Brake Control Register
address_offset : 0xC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSSBRKEN : Clock Security System Detection Trigger PWM Brake Function 0 Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake Function triggered by CSS detection Disabled
#1 : 1
Brake Function triggered by CSS detection Enabled
End of enumeration elements list.
BODBRKEN : Brown-out Detection Trigger PWM Brake Function 0 Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake Function triggered by BOD Disabled
#1 : 1
Brake Function triggered by BOD Enabled
End of enumeration elements list.
RAMBRKEN : SRAM Parity Error Detection Trigger PWM Brake Function 0 Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake Function triggered by SRAM parity error detection Disabled
#1 : 1
Brake Function triggered by SRAM parity error detection Enabled
End of enumeration elements list.
CORBRKEN : Core Lockup Detection Trigger PWM Brake Function 0 Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake Function triggered by Core lockup detection Disabled
#1 : 1
Brake Function triggered by Core lockup detection Enabled
End of enumeration elements list.
PWM Brake Edge Detect Control Register 0/1
address_offset : 0xC8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRKP0EEN : Enable PWM0_BRAKE0 Pin As Edge-detect Brake Source (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0_BRAKE0 pin as edge-detect brake source Disabled
#1 : 1
PWM0_BRAKE0 pin as edge-detect brake source Enabled
End of enumeration elements list.
BRKP1EEN : Enable PWM0_BRAKE1 Pin As Edge-detect Brake Source (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0_BRAKE1 pin as edge-detect brake source Disabled
#1 : 1
PWM0_BRAKE1 pin as edge-detect brake source Enabled
End of enumeration elements list.
SYSEBEN : Enable System Fail As Edge-detect Brake Source (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
System Fail condition as edge-detect brake source Disabled
#1 : 1
System Fail condition as edge-detect brake source Enabled
End of enumeration elements list.
BRKP0LEN : Enable BKP0 Pin As Level-detect Brake Source (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0_BRAKE0 pin as level-detect brake source Disabled
#1 : 1
PWM0_BRAKE0 pin as level-detect brake source Enabled
End of enumeration elements list.
BRKP1LEN : Enable BKP1 Pin As Level-detect Brake Source (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0_BRAKE1 pin as level-detect brake source Disabled
#1 : 1
PWM0_BRAKE1 pin as level-detect brake source Enabled
End of enumeration elements list.
SYSLBEN : Enable System Fail As Level-detect Brake Source (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
System Fail condition as level-detect brake source Disabled
#1 : 1
System Fail condition as level-detect brake source Enabled
End of enumeration elements list.
BRKAEVEN : PWM Brake Action Select for Even Channel (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
PWM0 brake event will not affect even channels output
#01 : 1
PWM even channel output tri-state when PWM0 brake event happened
#10 : 2
PWM even channel output low level when PWM0 brake event happened
#11 : 3
PWM even channel output high level when PWM0 brake event happened
End of enumeration elements list.
BRKAODD : PWM Brake Action Select for Odd Channel (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
PWM0 brake event will not affect odd channels output
#01 : 1
PWM odd channel output tri-state when PWM0 brake event happened
#10 : 2
PWM odd channel output low level when PWM0 brake event happened
#11 : 3
PWM odd channel output high level when PWM0 brake event happened
End of enumeration elements list.
EADCEBEN : Enable ADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
EADCRM as edge-detect brake source Disabled
#1 : 1
EADCRM as edge-detect brake source Enabled
End of enumeration elements list.
EADCLBEN : Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
EADCRM as level-detect brake source Disabled
#1 : 1
EADCRM as level-detect brake source Enabled
End of enumeration elements list.
PWM Brake Edge Detect Control Register 2/3
address_offset : 0xCC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Brake Edge Detect Control Register 4/5
address_offset : 0xD0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Pin Polar Inverse Register
address_offset : 0xD4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PINV0 : PWM Channel 0 PIN Polar Inverse Control
The register controls polarity state of PWM output.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output polar inverse Disabled
#1 : 1
PWM output polar inverse Enabled
End of enumeration elements list.
PINV1 : PWM Channel 1 PIN Polar Inverse Control
The register controls polarity state of PWM output.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output polar inverse Disabled
#1 : 1
PWM output polar inverse Enabled
End of enumeration elements list.
PINV2 : PWM Channel 2 PIN Polar Inverse Control
The register controls polarity state of PWM output.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output polar inverse Disabled
#1 : 1
PWM output polar inverse Enabled
End of enumeration elements list.
PINV3 : PWM Channel 3 PIN Polar Inverse Control
The register controls polarity state of PWM output.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output polar inverse Disabled
#1 : 1
PWM output polar inverse Enabled
End of enumeration elements list.
PINV4 : PWM Channel 4 PIN Polar Inverse Control
The register controls polarity state of PWM output.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output polar inverse Disabled
#1 : 1
PWM output polar inverse Enabled
End of enumeration elements list.
PINV5 : PWM Channel 5 PIN Polar Inverse Control
The register controls polarity state of PWM output.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output polar inverse Disabled
#1 : 1
PWM output polar inverse Enabled
End of enumeration elements list.
PWM Output Enable Register
address_offset : 0xD8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POEN0 : PWM Channel 0 Pin Output Enable Bits
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM pin at tri-state
#1 : 1
PWM pin in output mode
End of enumeration elements list.
POEN1 : PWM Channel 1 Pin Output Enable Bits
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM pin at tri-state
#1 : 1
PWM pin in output mode
End of enumeration elements list.
POEN2 : PWM Channel 2 Pin Output Enable Bits
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM pin at tri-state
#1 : 1
PWM pin in output mode
End of enumeration elements list.
POEN3 : PWM Channel 3 Pin Output Enable Bits
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM pin at tri-state
#1 : 1
PWM pin in output mode
End of enumeration elements list.
POEN4 : PWM Channel 4 Pin Output Enable Bits
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM pin at tri-state
#1 : 1
PWM pin in output mode
End of enumeration elements list.
POEN5 : PWM Channel 5 Pin Output Enable Bits
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM pin at tri-state
#1 : 1
PWM pin in output mode
End of enumeration elements list.
PWM Software Brake Control Register
address_offset : 0xDC Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BRKETRG0 : PWM Pair 0 Edge Brake Software Trigger (Write Only) (Write Protected)
Write 1 to this bit will trigger edge brake, and set BRKEIF0 to 1 in PWM_INTSTS1 register.
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : write-only
BRKETRG2 : PWM Pair 2 Edge Brake Software Trigger (Write Only) (Write Protected)
Write 1 to this bit will trigger edge brake, and set BRKEIF2 to 1 in PWM_INTSTS1 register.
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : write-only
BRKETRG4 : PWM Pair 4 Edge Brake Software Trigger (Write Only) (Write Protected)
Write 1 to this bit will trigger edge brake, and set BRKEIF4 to 1 in PWM_INTSTS1 register.
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : write-only
BRKLTRG0 : PWM Pair 0 Level Brake Software Trigger (Write Only) (Write Protected)
Write 1 to this bit will trigger level brake, and set BRKLIF0 to 1 in PWM_INTSTS1 register.
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : write-only
BRKLTRG2 : PWM Pair 2 Level Brake Software Trigger (Write Only) (Write Protected)
Write 1 to this bit will trigger level brake, and set BRKLIF2 to 1 in PWM_INTSTS1 register.
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : write-only
BRKLTRG4 : PWM Pair 4 Level Brake Software Trigger (Write Only) (Write Protected)
Write 1 to this bit will trigger level brake, and set BRKLIF4 to 1 in PWM_INTSTS1 register.
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 10 - 10 (1 bit)
access : write-only
PWM Interrupt Enable Register 0
address_offset : 0xE0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZIEN0 : PWM Channel 0 Zero Point Interrupt Enable Bits
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zero point interrupt Disabled
#1 : 1
Zero point interrupt Enabled
End of enumeration elements list.
ZIEN1 : PWM Channel 1 Zero Point Interrupt Enable Bits
Note: This channel will read always 0 at complementary mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zero point interrupt Disabled
#1 : 1
Zero point interrupt Enabled
End of enumeration elements list.
ZIEN2 : PWM Channel 2 Zero Point Interrupt Enable Bits
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zero point interrupt Disabled
#1 : 1
Zero point interrupt Enabled
End of enumeration elements list.
ZIEN3 : PWM Channel 3 Zero Point Interrupt Enable Bits
Note: This channel will read always 0 at complementary mode.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zero point interrupt Disabled
#1 : 1
Zero point interrupt Enabled
End of enumeration elements list.
ZIEN4 : PWM Channel 4 Zero Point Interrupt Enable Bits
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zero point interrupt Disabled
#1 : 1
Zero point interrupt Enabled
End of enumeration elements list.
ZIEN5 : PWM Channel 5 Zero Point Interrupt Enable Bits
Note: This channel will read always 0 at complementary mode.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zero point interrupt Disabled
#1 : 1
Zero point interrupt Enabled
End of enumeration elements list.
PIEN0 : PWM Channel 0 Period Point Interrupt Enable Bits
Note: When up-down counter type period point means center point.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Period point interrupt Disabled
#1 : 1
Period point interrupt Enabled
End of enumeration elements list.
PIEN1 : PWM Channel 1 Period Point Interrupt Enable Bits
Note1: When up-down counter type period point means center point.
Note2: This channels will read always 0 at complementary mode.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Period point interrupt Disabled
#1 : 1
Period point interrupt Enabled
End of enumeration elements list.
PIEN2 : PWM Channel 2 Period Point Interrupt Enable Bits
Note: When up-down counter type period point means center point.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Period point interrupt Disabled
#1 : 1
Period point interrupt Enabled
End of enumeration elements list.
PIEN3 : PWM Channel 3 Period Point Interrupt Enable Bits
Note1: When up-down counter type period point means center point.
Note2: This channels will read always 0 at complementary mode.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Period point interrupt Disabled
#1 : 1
Period point interrupt Enabled
End of enumeration elements list.
PIEN4 : PWM Channel 4 Period Point Interrupt Enable Bits
Note: When up-down counter type period point means center point.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Period point interrupt Disabled
#1 : 1
Period point interrupt Enabled
End of enumeration elements list.
PIEN5 : PWM Channel 5 Period Point Interrupt Enable Bits
Note1: When up-down counter type period point means center point.
Note2: This channels will read always 0 at complementary mode.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Period point interrupt Disabled
#1 : 1
Period point interrupt Enabled
End of enumeration elements list.
CMPUIEN0 : PWM Channel 0 Compare Up Count Interrupt Enable Bits
Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPUIEN1 : PWM Channel 1 Compare Up Count Interrupt Enable Bits
Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPUIEN2 : PWM Channel 2 Compare Up Count Interrupt Enable Bits
Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPUIEN3 : PWM Channel 3 Compare Up Count Interrupt Enable Bits
Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPUIEN4 : PWM Channel 4 Compare Up Count Interrupt Enable Bits
Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPUIEN5 : PWM Channel 5 Compare Up Count Interrupt Enable Bits
Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPDIEN0 : PWM Channel 0 Compare Down Count Interrupt Enable Bits
Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
CMPDIEN1 : PWM Channel 1 Compare Down Count Interrupt Enable Bits
Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
CMPDIEN2 : PWM Channel 2 Compare Down Count Interrupt Enable Bits
Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
CMPDIEN3 : PWM Channel 3 Compare Down Count Interrupt Enable Bits
Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
CMPDIEN4 : PWM Channel 4 Compare Down Count Interrupt Enable Bits
Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
CMPDIEN5 : PWM Channel 5 Compare Down Count Interrupt Enable Bits
Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
PWM Interrupt Enable Register 1
address_offset : 0xE4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRKEIEN0_1 : PWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge-detect Brake interrupt for channel0/1 Disabled
#1 : 1
Edge-detect Brake interrupt for channel0/1 Enabled
End of enumeration elements list.
BRKEIEN2_3 : PWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge-detect Brake interrupt for channel2/3 Disabled
#1 : 1
Edge-detect Brake interrupt for channel2/3 Enabled
End of enumeration elements list.
BRKEIEN4_5 : PWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge-detect Brake interrupt for channel4/5 Disabled
#1 : 1
Edge-detect Brake interrupt for channel4/5 Enabled
End of enumeration elements list.
BRKLIEN0_1 : PWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Level-detect Brake interrupt for channel0/1 Disabled
#1 : 1
Level-detect Brake interrupt for channel0/1 Enabled
End of enumeration elements list.
BRKLIEN2_3 : PWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Level-detect Brake interrupt for channel2/3 Disabled
#1 : 1
Level-detect Brake interrupt for channel2/3 Enabled
End of enumeration elements list.
BRKLIEN4_5 : PWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Level-detect Brake interrupt for channel4/5 Disabled
#1 : 1
Level-detect Brake interrupt for channel4/5 Enabled
End of enumeration elements list.
PWM Interrupt Flag Register 0
address_offset : 0xE8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZIF0 : PWM Channel 0 Zero Point Interrupt Flag
This bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero.
bits : 0 - 0 (1 bit)
access : read-write
ZIF1 : PWM Channel 1 Zero Point Interrupt Flag
This bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero.
bits : 1 - 1 (1 bit)
access : read-write
ZIF2 : PWM Channel 2 Zero Point Interrupt Flag
This bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero.
bits : 2 - 2 (1 bit)
access : read-write
ZIF3 : PWM Channel 3 Zero Point Interrupt Flag
This bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero.
bits : 3 - 3 (1 bit)
access : read-write
ZIF4 : PWM Channel 4 Zero Point Interrupt Flag
This bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero.
bits : 4 - 4 (1 bit)
access : read-write
ZIF5 : PWM Channel 5 Zero Point Interrupt Flag
This bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero.
bits : 5 - 5 (1 bit)
access : read-write
PIF0 : PWM Channel 0 Period Point Interrupt Flag
This bit is set by hardware when PWM counter reaches PWM_PERIOD0, software can write 1 to clear this bit to zero..
bits : 8 - 8 (1 bit)
access : read-write
PIF1 : PWM Channel 1 Period Point Interrupt Flag
This bit is set by hardware when PWM counter reaches PWM_PERIOD1, software can write 1 to clear this bit to zero.
bits : 9 - 9 (1 bit)
access : read-write
PIF2 : PWM Channel 2 Period Point Interrupt Flag
This bit is set by hardware when PWM counter reaches PWM_PERIOD2, software can write 1 to clear this bit to zero.
bits : 10 - 10 (1 bit)
access : read-write
PIF3 : PWM Channel 3 Period Point Interrupt Flag
This bit is set by hardware when PWM counter reaches PWM_PERIOD3, software can write 1 to clear this bit to zero.
bits : 11 - 11 (1 bit)
access : read-write
PIF4 : PWM Channel 4 Period Point Interrupt Flag
This bit is set by hardware when PWM counter reaches PWM_PERIOD4, software can write 1 to clear this bit to zero.
bits : 12 - 12 (1 bit)
access : read-write
PIF5 : PWM Channel 5 Period Point Interrupt Flag
This bit is set by hardware when PWM counter reaches PWM_PERIOD5, software can write 1 to clear this bit to zero.
bits : 13 - 13 (1 bit)
access : read-write
CMPUIF0 : PWM Channel 0 Compare Up Count Interrupt Flag
Flag is set by hardware when PWM counter up count and reaches PWM_CMPDAT0, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
bits : 16 - 16 (1 bit)
access : read-write
CMPUIF1 : PWM Channel 1 Compare Up Count Interrupt Flag
Flag is set by hardware when PWM counter up count and reaches PWM_CMPDAT1, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
bits : 17 - 17 (1 bit)
access : read-write
CMPUIF2 : PWM Channel 2 Compare Up Count Interrupt Flag
Flag is set by hardware when PWM counter up count and reaches PWM_CMPDAT2, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
bits : 18 - 18 (1 bit)
access : read-write
CMPUIF3 : PWM Channel 3 Compare Up Count Interrupt Flag
Flag is set by hardware when PWM counter up count and reaches PWM_CMPDAT3, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
bits : 19 - 19 (1 bit)
access : read-write
CMPUIF4 : PWM Channel 4 Compare Up Count Interrupt Flag
Flag is set by hardware when PWM counter up count and reaches PWM_CMPDAT4, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
bits : 20 - 20 (1 bit)
access : read-write
CMPUIF5 : PWM Channel 5 Compare Up Count Interrupt Flag
Flag is set by hardware when PWM counter up count and reaches PWM_CMPDAT5, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
bits : 21 - 21 (1 bit)
access : read-write
CMPDIF0 : PWM Channel 0 Compare Down Count Interrupt Flag
Flag is set by hardware when PWM counter down count and reaches PWM_CMPDAT0, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
bits : 24 - 24 (1 bit)
access : read-write
CMPDIF1 : PWM Channel 1 Compare Down Count Interrupt Flag
Flag is set by hardware when PWM counter down count and reaches PWM_CMPDAT1, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
bits : 25 - 25 (1 bit)
access : read-write
CMPDIF2 : PWM Channel 2 Compare Down Count Interrupt Flag
Flag is set by hardware when PWM counter down count and reaches PWM_CMPDAT2, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
bits : 26 - 26 (1 bit)
access : read-write
CMPDIF3 : PWM Channel 3 Compare Down Count Interrupt Flag
Flag is set by hardware when PWM counter down count and reaches PWM_CMPDAT3, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
bits : 27 - 27 (1 bit)
access : read-write
CMPDIF4 : PWM Channel 4 Compare Down Count Interrupt Flag
Flag is set by hardware when PWM counter down count and reaches PWM_CMPDAT4, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
bits : 28 - 28 (1 bit)
access : read-write
CMPDIF5 : PWM Channel 4 Compare Down Count Interrupt Flag
Flag is set by hardware when PWM counter down count and reaches PWM_CMPDAT5, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
bits : 29 - 29 (1 bit)
access : read-write
PWM Interrupt Flag Register 1
address_offset : 0xEC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRKEIF0 : PWM Channel 0 Edge-detect Brake Interrupt Flag (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 0 edge-detect brake event do not happened
#1 : 1
When PWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKEIF1 : PWM Channel 1 Edge-detect Brake Interrupt Flag (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 1 edge-detect brake event do not happened
#1 : 1
When PWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKEIF2 : PWM Channel 2 Edge-detect Brake Interrupt Flag (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 2 edge-detect brake event do not happened
#1 : 1
When PWM channel 2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKEIF3 : PWM Channel 3 Edge-detect Brake Interrupt Flag (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 3 edge-detect brake event do not happened
#1 : 1
When PWM channel 3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKEIF4 : PWM Channel 4 Edge-detect Brake Interrupt Flag (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 4 edge-detect brake event do not happened
#1 : 1
When PWM channel 4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKEIF5 : PWM Channel 5 Edge-detect Brake Interrupt Flag (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 5 edge-detect brake event do not happened
#1 : 1
When PWM channel 5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKLIF0 : PWM Channel 0 Level-detect Brake Interrupt Flag (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 0 level-detect brake event do not happened
#1 : 1
When PWM channel 0 level-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKLIF1 : PWM Channel 1 Level-detect Brake Interrupt Flag (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 1 level-detect brake event do not happened
#1 : 1
When PWM channel 1 level-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKLIF2 : PWM Channel 2 Level-detect Brake Interrupt Flag (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 2 level-detect brake event do not happened
#1 : 1
When PWM channel 2 level-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKLIF3 : PWM Channel 3 Level-detect Brake Interrupt Flag (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 3 level-detect brake event do not happened
#1 : 1
When PWM channel 3 level-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKLIF4 : PWM Channel 4 Level-detect Brake Interrupt Flag (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 4 level-detect brake event do not happened
#1 : 1
When PWM channel 4 level-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKLIF5 : PWM Channel 5 Level-detect Brake Interrupt Flag (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 5 level-detect brake event do not happened
#1 : 1
When PWM channel 5 level-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKESTS0 : PWM Channel 0 Edge-detect Brake Status
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 0 edge-detect brake state is released
#1 : 1
When PWM channel 0 edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel 0 at brake state, writing 1 to clear
End of enumeration elements list.
BRKESTS1 : PWM Channel 1 Edge-detect Brake Status
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 1 edge-detect brake state is released
#1 : 1
When PWM channel 1 edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel 1 at brake state, writing 1 to clear
End of enumeration elements list.
BRKESTS2 : PWM Channel 2 Edge-detect Brake Status
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 2 edge-detect brake state is released
#1 : 1
When PWM channel 2 edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel 2 at brake state, writing 1 to clear
End of enumeration elements list.
BRKESTS3 : PWM Channel 3 Edge-detect Brake Status
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 3 edge-detect brake state is released
#1 : 1
When PWM channel 3 edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel 3 at brake state, writing 1 to clear
End of enumeration elements list.
BRKESTS4 : PWM Channel 4 Edge-detect Brake Status
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 4 edge-detect brake state is released
#1 : 1
When PWM channel 4 edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel 4 at brake state, writing 1 to clear
End of enumeration elements list.
BRKESTS5 : PWM Channel 5 Edge-detect Brake Status
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 5 edge-detect brake state is released
#1 : 1
When PWM channel 5 edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel 5 at brake state, writing 1 to clear
End of enumeration elements list.
BRKLSTS0 : PWM Channel 0 Level-detect Brake Status (Read Only)
Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM channel 0 level-detect brake state is released
#1 : 1
When PWM channel 0 level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel 0 at brake state
End of enumeration elements list.
BRKLSTS1 : PWM Channel 1 Level-detect Brake Status (Read Only)
Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM channel 1 level-detect brake state is released
#1 : 1
When PWM channel 1 level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel 1 at brake state
End of enumeration elements list.
BRKLSTS2 : PWM Channel 2 Level-detect Brake Status (Read Only)
Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM channel 2 level-detect brake state is released
#1 : 1
When PWM channel 2 level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel 2 at brake state
End of enumeration elements list.
BRKLSTS3 : PWM Channel 3 Level-detect Brake Status (Read Only)
Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM channel 3 level-detect brake state is released
#1 : 1
When PWM channel 3 level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel 3 at brake state
End of enumeration elements list.
BRKLSTS4 : PWM Channel 4 Level-detect Brake Status (Read Only)
Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM channel 4 level-detect brake state is released
#1 : 1
When PWM channel 4 level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel 4 at brake state
End of enumeration elements list.
BRKLSTS5 : PWM Channel 5 Level-detect Brake Status (Read Only)
Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM channel 5 level-detect brake state is released
#1 : 1
When PWM channel 5 level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel 5 at brake state
End of enumeration elements list.
PWM Trigger EADC Source Select Register 0
address_offset : 0xF8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSEL0 : PWM_CH0 Trigger EADC Source Select
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM_CH0 zero point
#0001 : 1
PWM_CH0 period point
#0010 : 2
PWM_CH0 zero or period point
#0011 : 3
PWM_CH0 up-count CMPDAT point
#0100 : 4
PWM_CH0 down-count CMPDAT point
#0101 : 5
PWM_CH1 zero point
#0110 : 6
PWM_CH1 period point
#0111 : 7
PWM_CH1 zero or period point
#1000 : 8
PWM_CH1 up-count CMPDAT point
#1001 : 9
PWM_CH1 down-count CMPDAT point
#1010 : 10
PWM_CH0 up-count free CMPDAT point
#1011 : 11
PWM_CH0 down-count free CMPDAT point
#1100 : 12
PWM_CH2 up-count free CMPDAT point
#1101 : 13
PWM_CH2 down-count free CMPDAT point
#1110 : 14
PWM_CH4 up-count free CMPDAT point
#1111 : 15
PWM_CH4 down-count free CMPDAT point
End of enumeration elements list.
TRGEN0 : PWM_CH0 Trigger EADC enable bit
bits : 7 - 7 (1 bit)
access : read-write
TRGSEL1 : PWM_CH1 Trigger EADC Source Select
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM_CH0 zero point
#0001 : 1
PWM_CH0 period point
#0010 : 2
PWM_CH0 zero or period point
#0011 : 3
PWM_CH0 up-count CMPDAT point
#0100 : 4
PWM_CH0 down-count CMPDAT point
#0101 : 5
PWM_CH1 zero point
#0110 : 6
PWM_CH1 period point
#0111 : 7
PWM_CH1 zero or period point
#1000 : 8
PWM_CH1 up-count CMPDAT point
#1001 : 9
PWM_CH1 down-count CMPDAT point
#1010 : 10
PWM_CH0 up-count free CMPDAT point
#1011 : 11
PWM_CH0 down-count free CMPDAT point
#1100 : 12
PWM_CH2 up-count free CMPDAT point
#1101 : 13
PWM_CH2 down-count free CMPDAT point
#1110 : 14
PWM_CH4 up-count free CMPDAT point
#1111 : 15
PWM_CH4 down-count free CMPDAT point
End of enumeration elements list.
TRGEN1 : PWM_CH1 Trigger EADC enable bit
bits : 15 - 15 (1 bit)
access : read-write
TRGSEL2 : PWM_CH2 Trigger EADC Source Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM_CH2 zero point
#0001 : 1
PWM_CH2 period point
#0010 : 2
PWM_CH2 zero or period point
#0011 : 3
PWM_CH2 up-count CMPDAT point
#0100 : 4
PWM_CH2 down-count CMPDAT point
#0101 : 5
PWM_CH3 zero point
#0110 : 6
PWM_CH3 period point
#0111 : 7
PWM_CH3 zero or period point
#1000 : 8
PWM_CH3 up-count CMPDAT point
#1001 : 9
PWM_CH3 down-count CMPDAT point
#1010 : 10
PWM_CH0 up-count free CMPDAT point
#1011 : 11
PWM_CH0 down-count free CMPDAT point
#1100 : 12
PWM_CH2 up-count free CMPDAT point
#1101 : 13
PWM_CH2 down-count free CMPDAT point
#1110 : 14
PWM_CH4 up-count free CMPDAT point
#1111 : 15
PWM_CH4 down-count free CMPDAT point
End of enumeration elements list.
TRGEN2 : PWM_CH2 Trigger EADC enable bit
bits : 23 - 23 (1 bit)
access : read-write
TRGSEL3 : PWM_CH3 Trigger EADC Source Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM_CH2 zero point
#0001 : 1
PWM_CH2 period point
#0010 : 2
PWM_CH2 zero or period point
#0011 : 3
PWM_CH2 up-count CMPDAT point
#0100 : 4
PWM_CH2 down-count CMPDAT point
#0101 : 5
PWM_CH3 zero point
#0110 : 6
PWM_CH3 period point
#0111 : 7
PWM_CH3 zero or period point
#1000 : 8
PWM_CH3 up-count CMPDAT point
#1001 : 9
PWM_CH3 down-count CMPDAT point
#1010 : 10
PWM_CH0 up-count free CMPDAT point
#1011 : 11
PWM_CH0 down-count free CMPDAT point
#1100 : 12
PWM_CH2 up-count free CMPDAT point
#1101 : 13
PWM_CH2 down-count free CMPDAT point
#1110 : 14
PWM_CH4 up-count free CMPDAT point
#1111 : 15
PWM_CH4 down-count free CMPDAT point
End of enumeration elements list.
TRGEN3 : PWM_CH3 Trigger EADC enable bit
bits : 31 - 31 (1 bit)
access : read-write
PWM Trigger EADC Source Select Register 1
address_offset : 0xFC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSEL4 : PWM_CH4 Trigger EADC Source Select
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM_CH4 zero point
#0001 : 1
PWM_CH4 period point
#0010 : 2
PWM_CH4 zero or period point
#0011 : 3
PWM_CH4 up-count CMPDAT point
#0100 : 4
PWM_CH4 down-count CMPDAT point
#0101 : 5
PWM_CH5 zero point
#0110 : 6
PWM_CH5 period point
#0111 : 7
PWM_CH5 zero or period point
#1000 : 8
PWM_CH5 up-count CMPDAT point
#1001 : 9
PWM_CH5 down-count CMPDAT point
#1010 : 10
PWM_CH0 up-count free CMPDAT point
#1011 : 11
PWM_CH0 down-count free CMPDAT point
#1100 : 12
PWM_CH2 up-count free CMPDAT point
#1101 : 13
PWM_CH2 down-count free CMPDAT point
#1110 : 14
PWM_CH4 up-count free CMPDAT point
#1111 : 15
PWM_CH4 down-count free CMPDAT point
End of enumeration elements list.
TRGEN4 : PWM_CH4 Trigger EADC enable bit
bits : 7 - 7 (1 bit)
access : read-write
TRGSEL5 : PWM_CH5 Trigger EADC Source Select
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM_CH4 zero point
#0001 : 1
PWM_CH4 period point
#0010 : 2
PWM_CH4 zero or period point
#0011 : 3
PWM_CH4 up-count CMPDAT point
#0100 : 4
PWM_CH4 down-count CMPDAT point
#0101 : 5
PWM_CH5 zero point
#0110 : 6
PWM_CH5 period point
#0111 : 7
PWM_CH5 zero or period point
#1000 : 8
PWM_CH5 up-count CMPDAT point
#1001 : 9
PWM_CH5 down-count CMPDAT point
#1010 : 10
PWM_CH0 up-count free CMPDAT point
#1011 : 11
PWM_CH0 down-count free CMPDAT point
#1100 : 12
PWM_CH2 up-count free CMPDAT point
#1101 : 13
PWM_CH2 down-count free CMPDAT point
#1110 : 14
PWM_CH4 up-count free CMPDAT point
#1111 : 15
PWM_CH4 down-count free CMPDAT point
End of enumeration elements list.
TRGEN5 : PWM_CH5 Trigger EADC enable bit
bits : 15 - 15 (1 bit)
access : read-write
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