\n
address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
WDT Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTCNT : Reset WDT Up Counter (Write Protected)
Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note2: This bit will be automatically cleared by hardware.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset the internal 18-bit WDT up counter value
End of enumeration elements list.
RSTEN : WDT Time-out Reset Enable Control (Write Protected)
Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
WDT time-out reset function Disabled
#1 : 1
WDT time-out reset function Enabled
End of enumeration elements list.
RSTF : WDT Time-out Reset Flag
This bit indicates the system has been reset by WDT time-out reset or not.
Note: This bit is cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
WDT time-out reset did not occur
#1 : 1
WDT time-out reset occurred
End of enumeration elements list.
IF : WDT Time-out Interrupt Flag
This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval
Note: This bit is cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
WDT time-out interrupt did not occur
#1 : 1
WDT time-out interrupt occurred
End of enumeration elements list.
WKEN : WDT Time-out Wake-up Function Control (Write Protected)
If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz internal low speed RC oscillator (LIRC) or LXT.
Note3: The reset value of this bit is 0.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Wake-up trigger event Disabled if WDT time-out interrupt signal generated
#1 : 1
Wake-up trigger event Enabled if WDT time-out interrupt signal generated
End of enumeration elements list.
WKF : WDT Time-out Wake-up Flag (Write Protected)
This bit indicates the interrupt wake-up flag status of WDT
Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note2: This bit is cleared by writing 1 to it.
Note3: The reset value of this bit is 0.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
WDT does not cause chip wake-up
#1 : 1
Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated
End of enumeration elements list.
INTEN : WDT Time-out Interrupt Enable Control (Write Protected)
If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note2: The reset value of this bit is 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
WDT time-out interrupt Disabled
#1 : 1
WDT time-out interrupt Enabled
End of enumeration elements list.
WDTEN : WDT Enable Control (Write Protected)
Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111, this bit is forced as 1 and user cannot change this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
WDT Disabled (This action will reset the internal up counter value)
#1 : 1
WDT Enabled
End of enumeration elements list.
TOUTSEL : WDT Time-out Interval Selection (Write Protected)
These three bits select the time-out interval period for the WDT.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
24 * WDT_CLK
#001 : 1
26 * WDT_CLK
#010 : 2
28 * WDT_CLK
#011 : 3
210 * WDT_CLK
#100 : 4
212 * WDT_CLK
#101 : 5
214 * WDT_CLK
#110 : 6
216 * WDT_CLK
#111 : 7
218 * WDT_CLK
End of enumeration elements list.
ICEDEBUG : ICE Debug Mode Acknowledge Disable Control (Write Protected)
WDT up counter will keep going no matter CPU is held by ICE or not.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode acknowledgement affects WDT counting
#1 : 1
ICE debug mode acknowledgement Disabled
End of enumeration elements list.
WDT Alternative Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTDSEL : WDT Reset Delay Selection (Write Protected)
When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened. User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.
Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note2: This register will be reset to 0 if WDT time-out reset happened.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
WDT Reset Delay Period is 1026 * WDT_CLK
#01 : 1
WDT Reset Delay Period is 130 * WDT_CLK
#10 : 2
WDT Reset Delay Period is 18 * WDT_CLK
#11 : 3
WDT Reset Delay Period is 3 * WDT_CLK
End of enumeration elements list.
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