Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
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ADC Data Register 0 for Sample Module 0
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : ADC Conversion Result
This field contains 12 bits conversion result.
When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].
When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12].
bits : 0 - 15 (16 bit)
access : read-only
OV : Overrun Flag
If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1.
Note: It is cleared by hardware after EADC_DAT register is read.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data in RESULT[11:0] is recent conversion result
#1 : 1
Data in RESULT[11:0] is overwrite
End of enumeration elements list.
VALID : Valid Flag
This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read.
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data in RESULT[11:0] bits is not valid
#1 : 1
Data in RESULT[11:0] bits is valid
End of enumeration elements list.
ADC Data Register 4 for Sample Module 4
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Double Data Register 0 for Sample Module 0
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : ADC Conversion Results
This field contains 12 bits conversion results.
When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].
When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12].
bits : 0 - 15 (16 bit)
access : read-only
OV : Overrun Flag
If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1. It is cleared by hardware after EADC_DDAT register is read.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result
#1 : 1
Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite
End of enumeration elements list.
VALID : Valid Flag
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
Double data in RESULT (EADC_DDATn[15:0]) is not valid
#1 : 1
Double data in RESULT (EADC_DDATn[15:0]) is valid
End of enumeration elements list.
ADC Double Data Register 1 for Sample Module 1
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Double Data Register 2 for Sample Module 2
address_offset : 0x108 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Double Data Register 3 for Sample Module 3
address_offset : 0x10C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Power Management Register
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWUPRDY : ADC Power-up Sequence Completed and Ready for Conversion(Read Only)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
ADC is not ready for conversion may be in power down state or in the progress of start up
#1 : 1
ADC is ready for conversion
End of enumeration elements list.
PWUCALEN : Power Up Calibration Function Enable Control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the function of calibration at power up
#1 : 1
Enable the function of calibration at power up
End of enumeration elements list.
PWDMOD : ADC Power-down Mode
Set this bit fields to select ADC Power-down mode when system power-down.
Note: Different PWDMOD has different power down/up sequence, in order to avoid ADC powering up with wrong sequence user must keep PWMOD consistent each time in power down and start up.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
ADC Deep Power-down mode
#01 : 1
ADC Power down
#10 : 2
ADC Standby mode
#11 : 3
ADC Deep Power-down mode
End of enumeration elements list.
LDOSUT : ADC Internal LDO Start-up Time
bits : 8 - 19 (12 bit)
access : read-write
ADC Data Register 5 for Sample Module 5
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 6 for Sample Module 6
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 7 for Sample Module 7
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 8 for Sample Module 8
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Channel Switch Presetting Control Register
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHSPC : ADC Channel Switch Presetting Control
Note: For EADC converting multi-channel input signal, please set 0x21 to CHSPC
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0x00 : 0
No channel switch presetting function
0x21 : 33
Enable switch presetting. Channel switch is preset 1 EADC clock before the end of conversion, then switched when end of conversion
End of enumeration elements list.
ADC Data Register 9 for Sample Module 9
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 10 for Sample Module 10
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 11 for Sample Module 11
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 12 for Sample Module 12
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 1 for Sample Module 1
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC PDMA Current Transfer Data Register
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CURDAT : ADC PDMA Current Transfer Data Register (Read Only)
bits : 0 - 12 (13 bit)
access : read-only
ADC Control Register
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCEN : ADC Converter Enable Bit
Note: Before starting ADC conversion function, this bit should be set to 1. Clear it to 0 to disable ADC converter analog circuit power consumption.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled EADC
#1 : 1
Enabled EADC
End of enumeration elements list.
ADCRST : ADC Converter Control Circuits Reset
Note: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Cause ADC control circuits reset to initial state, but not change the ADC registers value
End of enumeration elements list.
ADCIEN0 : Specific Sample Module ADC ADINT0 Interrupt Enable Bit
The ADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module ADC conversion. If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Specific sample module ADC ADINT0 interrupt function Disabled
#1 : 1
Specific sample module ADC ADINT0 interrupt function Enabled
End of enumeration elements list.
ADCIEN1 : Specific Sample Module ADC ADINT1 Interrupt Enable Bit
The ADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module ADC conversion. If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Specific sample module ADC ADINT1 interrupt function Disabled
#1 : 1
Specific sample module ADC ADINT1 interrupt function Enabled
End of enumeration elements list.
ADCIEN2 : Specific Sample Module ADC ADINT2 Interrupt Enable Bit
The ADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module ADC conversion. If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Specific sample module ADC ADINT2 interrupt function Disabled
#1 : 1
Specific sample module ADC ADINT2 interrupt function Enabled
End of enumeration elements list.
ADCIEN3 : Specific Sample Module ADC ADINT3 Interrupt Enable Bit
The ADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module ADC conversion. If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Specific sample module ADC ADINT3 interrupt function Disabled
#1 : 1
Specific sample module ADC ADINT3 interrupt function Enabled
End of enumeration elements list.
RESSEL : Resolution Selection
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
6-bit. ADC result will put at RESULT (EADC_ DATn [5:0])
#01 : 1
8-bit. ADC result will put at RESULT (EADC_ DATn [7:0])
#10 : 2
10-bit. ADC result will put at RESULT (EADC_ DATn [9:0])
#11 : 3
12-bit. ADC result will put at RESULT (EADC_ DATn [11:0])
End of enumeration elements list.
DMOF : ADC Differential Input Mode Output Format
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~12) with unsigned format
#1 : 1
ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~12) with 2'complement format
End of enumeration elements list.
PDMAEN : PDMA Transfer Enable Bit
When ADC conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 12) register, user can enable this bit to generate a PDMA data transfer request.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA data transfer Disabled
#1 : 1
PDMA data transfer Enabled
End of enumeration elements list.
ADC Sample Module Software Start Register
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWTRG : ADC Sample Module 0~12 Software Force to Start ADC Conversion
Note: After write this register to start ADC conversion, the EADC_PENDSTS register will show which sample module will conversion. If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
bits : 0 - 12 (13 bit)
access : write-only
Enumeration:
0 : 0
No effect
1 : 1
Cause an ADC conversion when the priority is given to sample module
End of enumeration elements list.
ADC Start of Conversion Pending Flag Register
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STPF : ADC Sample Module 0~12 Start of Conversion Pending Flag
Read:
bits : 0 - 12 (13 bit)
access : read-write
Enumeration:
0 : 0
There is no pending conversion for sample module
1 : 1
Sample module ADC start of conversion is pending.
clear pending flag and cancel the conversion for sample module
End of enumeration elements list.
ADC Sample Module Start of Conversion Overrun Flag Register
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPOVF : ADC SAMPLE0~12 Overrun Flag
Note: This bit is cleared by writing 1 to it.
bits : 0 - 12 (13 bit)
access : read-write
Enumeration:
0 : 0
No sample module event overrun
1 : 1
Indicates a new sample module event is generated while an old one event is pending
End of enumeration elements list.
ADC Data Register 2 for Sample Module 2
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Sample Module 0 Control Register
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHSEL : ADC Sample Module Channel Selection
bits : 0 - 3 (4 bit)
access : read-write
EXTREN : ADC External Trigger Rising Edge Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising edge Disabled when ADC selects EADC0_ST as trigger source
#1 : 1
Rising edge Enabled when ADC selects EADC0_ST as trigger source
End of enumeration elements list.
EXTFEN : ADC External Trigger Falling Edge Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling edge Disabled when ADC selects EADC0_ST as trigger source
#1 : 1
Falling edge Enabled when ADC selects EADC0_ST as trigger source
End of enumeration elements list.
TRGDLYDIV : ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection
Trigger delay clock frequency:
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
ADC_CLK/1
#01 : 1
ADC_CLK/2
#10 : 2
ADC_CLK/4
#11 : 3
ADC_CLK/16
End of enumeration elements list.
TRGDLYCNT : ADC Sample Module Start of Conversion Trigger Delay Time
bits : 8 - 15 (8 bit)
access : read-write
TRGSEL : ADC Sample Module Start of Conversion Trigger Source Selection
bits : 16 - 20 (5 bit)
access : read-write
INTPOS : Interrupt Flag Position Select
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion
#1 : 1
Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion
End of enumeration elements list.
DBMEN : Double Buffer Mode Enable Bit
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample has one sample result register. (default)
#1 : 1
Sample has two sample result registers
End of enumeration elements list.
EXTSMPT : ADC Sampling Time Extend
When ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend ADC sampling time after trigger source is coming to get enough sampling time.
The range of start delay time is from 0~255 ADC clock.
bits : 24 - 31 (8 bit)
access : read-write
ADC Sample Module 1 Control Register
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Sample Module 2 Control Register
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Sample Module 3 Control Register
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Sample Module 4 Control Register
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHSEL : ADC Sample Module Channel Selection
bits : 0 - 3 (4 bit)
access : read-write
EXTREN : ADC External Trigger Rising Edge Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising edge Disabled when ADC selects EADC0_ST as trigger source
#1 : 1
Rising edge Enabled when ADC selects EADC0_ST as trigger source
End of enumeration elements list.
EXTFEN : ADC External Trigger Falling Edge Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling edge Disabled when ADC selects EADC0_ST as trigger source
#1 : 1
Falling edge Enabled when ADC selects EADC0_ST as trigger source
End of enumeration elements list.
TRGDLYDIV : ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection
Trigger delay clock frequency:
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
ADC_CLK/1
#01 : 1
ADC_CLK/2
#10 : 2
ADC_CLK/4
#11 : 3
ADC_CLK/16
End of enumeration elements list.
TRGDLYCNT : ADC Sample Module Start of Conversion Trigger Delay Time
bits : 8 - 15 (8 bit)
access : read-write
TRGSEL : ADC Sample Module Start of Conversion Trigger Source Selection
bits : 16 - 20 (5 bit)
access : read-write
INTPOS : Interrupt Flag Position Select
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion
#1 : 1
Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion
End of enumeration elements list.
EXTSMPT : ADC Sampling Time Extend
When ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend ADC sampling time after trigger source is coming to get enough sampling time.
The range of start delay time is from 0~255 ADC clock.
bits : 24 - 31 (8 bit)
access : read-write
ADC Sample Module 5 Control Register
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Sample Module 6 Control Register
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Sample Module 7 Control Register
address_offset : 0x9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Sample Module 8 Control Register
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Sample Module 9 Control Register
address_offset : 0xA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Sample Module 10 Control Register
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Sample Module 11 Control Register
address_offset : 0xAC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Sample Module 12 Control Register
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 3 for Sample Module 3
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Interrupt 0 Source Enable Control Register.
address_offset : 0xD0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPLIE0 : Sample Module 0 Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 0 interrupt Disabled
#1 : 1
Sample Module 0 interrupt Enabled
End of enumeration elements list.
SPLIE1 : Sample Module 1 Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 1 interrupt Disabled
#1 : 1
Sample Module 1 interrupt Enabled
End of enumeration elements list.
SPLIE2 : Sample Module 2 Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 2 interrupt Disabled
#1 : 1
Sample Module 2 interrupt Enabled
End of enumeration elements list.
SPLIE3 : Sample Module 3 Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 3 interrupt Disabled
#1 : 1
Sample Module 3 interrupt Enabled
End of enumeration elements list.
SPLIE4 : Sample Module 4 Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 4 interrupt Disabled
#1 : 1
Sample Module 4 interrupt Enabled
End of enumeration elements list.
SPLIE5 : Sample Module 5 Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 5 interrupt Disabled
#1 : 1
Sample Module 5 interrupt Enabled
End of enumeration elements list.
SPLIE6 : Sample Module 6 Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 6 interrupt Disabled
#1 : 1
Sample Module 6 interrupt Enabled
End of enumeration elements list.
SPLIE7 : Sample Module 7 Interrupt Enable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 7 interrupt Disabled
#1 : 1
Sample Module 7 interrupt Enabled
End of enumeration elements list.
SPLIE8 : Sample Module 8 Interrupt Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 8 interrupt Disabled
#1 : 1
Sample Module 8 interrupt Enabled
End of enumeration elements list.
SPLIE9 : Sample Module 9 Interrupt Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 9 interrupt Disabled
#1 : 1
Sample Module 9 interrupt Enabled
End of enumeration elements list.
SPLIE10 : Sample Module 10 Interrupt Enable Bit
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 10 interrupt Disabled
#1 : 1
Sample Module 10 interrupt Enabled
End of enumeration elements list.
SPLIE11 : Sample Module 11 Interrupt Enable Bit
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 11 interrupt Disabled
#1 : 1
Sample Module 11 interrupt Enabled
End of enumeration elements list.
SPLIE12 : Sample Module 12 Interrupt Enable Bit
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 12 interrupt Disabled
#1 : 1
Sample Module 12 interrupt Enabled
End of enumeration elements list.
ADC Interrupt 1 Source Enable Control Register.
address_offset : 0xD4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Interrupt 2 Source Enable Control Register.
address_offset : 0xD8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Interrupt 3 Source Enable Control Register.
address_offset : 0xDC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Result Compare Register 0
address_offset : 0xE0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMPEN : ADC Result Compare Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare Disabled
#1 : 1
Compare Enabled
End of enumeration elements list.
ADCMPIE : ADC Result Compare Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare function interrupt Disabled
#1 : 1
Compare function interrupt Enabled
End of enumeration elements list.
CMPCOND : Compare Condition
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set the compare condition as that when a 12-bit ADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one
#1 : 1
Set the compare condition as that when a 12-bit ADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one
End of enumeration elements list.
CMPSPL : Compare Sample Module Selection
bits : 3 - 7 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Sample Module 0 conversion result EADC_DAT0 is selected to be compared
#00001 : 1
Sample Module 1 conversion result EADC_DAT1 is selected to be compared
#00010 : 2
Sample Module 2 conversion result EADC_DAT2 is selected to be compared
#00011 : 3
Sample Module 3 conversion result EADC_DAT3 is selected to be compared
#00100 : 4
Sample Module 4 conversion result EADC_DAT4 is selected to be compared
#00101 : 5
Sample Module 5 conversion result EADC_DAT5 is selected to be compared
#00110 : 6
Sample Module 6 conversion result EADC_DAT6 is selected to be compared
#00111 : 7
Sample Module 7 conversion result EADC_DAT7 is selected to be compared
#01000 : 8
Sample Module 8 conversion result EADC_DAT8 is selected to be compared
#01001 : 9
Sample Module 9 conversion result EADC_DAT9 is selected to be compared
#01010 : 10
Sample Module 10 conversion result EADC_DAT10 is selected to be compared
#01011 : 11
Sample Module 11 conversion result EADC_DAT11 is selected to be compared
#01100 : 12
Sample Module 12 conversion result EADC_DAT12 is selected to be compared
End of enumeration elements list.
CMPMCNT : Compare Match Count
bits : 8 - 11 (4 bit)
access : read-write
CMPWEN : Compare Window Mode Enable Bit
Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched. ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched
#1 : 1
ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched. ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched
End of enumeration elements list.
CMPDAT : Comparison Data
The 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software.
bits : 16 - 27 (12 bit)
access : read-write
ADC Result Compare Register 1
address_offset : 0xE4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Result Compare Register 2
address_offset : 0xE8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Result Compare Register 3
address_offset : 0xEC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Status Register 0
address_offset : 0xF0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALID : EADC_DAT0~12 Data Valid Flag
bits : 0 - 12 (13 bit)
access : read-only
OV : EADC_DAT0~12 Overrun Flag
bits : 16 - 28 (13 bit)
access : read-only
ADC Status Register 2
address_offset : 0xF8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADIF0 : ADC ADINT0 Interrupt Flag
Note1: This bit is cleared by writing 1 to it.
Note2:This bit indicates whether an ADC conversion of specific sample module has been completed
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ADINT0 interrupt pulse received
#1 : 1
ADINT0 interrupt pulse has been received
End of enumeration elements list.
ADIF1 : ADC ADINT1 Interrupt Flag
Note1: This bit is cleared by writing 1 to it.
Note2:This bit indicates whether an ADC conversion of specific sample module has been completed
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ADINT1 interrupt pulse received
#1 : 1
ADINT1 interrupt pulse has been received
End of enumeration elements list.
ADIF2 : ADC ADINT2 Interrupt Flag
Note1: This bit is cleared by writing 1 to it.
Note2:This bit indicates whether an ADC conversion of specific sample module has been completed
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ADINT2 interrupt pulse received
#1 : 1
ADINT2 interrupt pulse has been received
End of enumeration elements list.
ADIF3 : ADC ADINT3 Interrupt Flag
Note1: This bit is cleared by writing 1 to it.
Note2:This bit indicates whether an ADC conversion of specific sample module has been completed
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ADINT3 interrupt pulse received
#1 : 1
ADINT3 interrupt pulse has been received
End of enumeration elements list.
ADCMPF0 : ADC Compare 0 Flag
When the specific sample module ADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.
Note: This bit is cleared by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in EADC_DAT does not meet EADC_CMP0 register setting
#1 : 1
Conversion result in EADC_DAT meets EADC_CMP0 register setting
End of enumeration elements list.
ADCMPF1 : ADC Compare 1 Flag
When the specific sample module ADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.
Note: This bit is cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in EADC_DAT does not meet EADC_CMP1 register setting
#1 : 1
Conversion result in EADC_DAT meets EADC_CMP1 register setting
End of enumeration elements list.
ADCMPF2 : ADC Compare 2 Flag
When the specific sample module ADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.
Note: This bit is cleared by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in EADC_DAT does not meet EADC_CMP2 register setting
#1 : 1
Conversion result in EADC_DAT meets EADC_CMP2 register setting
End of enumeration elements list.
ADCMPF3 : ADC Compare 3 Flag
When the specific sample module ADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.
Note: This bit is cleared by writing 1 to it.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in EADC_DAT does not meet EADC_CMP3 register setting
#1 : 1
Conversion result in EADC_DAT meets EADC_CMP3 register setting
End of enumeration elements list.
ADOVIF0 : ADC ADINT0 Interrupt Flag Overrun
Note: This bit is cleared by writing 1 to it.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADINT0 interrupt flag is not overwritten to 1
#1 : 1
ADINT0 interrupt flag is overwritten to 1
End of enumeration elements list.
ADOVIF1 : ADC ADINT1 Interrupt Flag Overrun
Note: This bit is cleared by writing 1 to it.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADINT1 interrupt flag is not overwritten to 1
#1 : 1
ADINT1 interrupt flag is overwritten to 1
End of enumeration elements list.
ADOVIF2 : ADC ADINT2 Interrupt Flag Overrun
Note: This bit is cleared by writing 1 to it.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADINT2 interrupt flag is not overwritten to 1
#1 : 1
ADINT2 interrupt flag is s overwritten to 1
End of enumeration elements list.
ADOVIF3 : ADC ADINT3 Interrupt Flag Overrun
Note: This bit is cleared by writing 1 to it.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADINT3 interrupt flag is not overwritten to 1
#1 : 1
ADINT3 interrupt flag is overwritten to 1
End of enumeration elements list.
ADCMPO0 : ADC Compare 0 Output Status(Read Only)
The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status.
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
Conversion result in EADC_DAT less than CMPDAT0 setting
#1 : 1
Conversion result in EADC_DAT great than or equal CMPDAT0 setting
End of enumeration elements list.
ADCMPO1 : ADC Compare 1 Output Status(Read Only)
The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status.
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
#0 : 0
Conversion result in EADC_DAT less than CMPDAT1 setting
#1 : 1
Conversion result in EADC_DAT great than or equal CMPDAT1 setting
End of enumeration elements list.
ADCMPO2 : ADC Compare 2 Output Status(Read Only)
The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status.
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
Conversion result in EADC_DAT less than CMPDAT2 setting
#1 : 1
Conversion result in EADC_DAT great than or equal CMPDAT2 setting
End of enumeration elements list.
ADCMPO3 : ADC Compare 3 Output Status(Read Only)
The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status.
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
Conversion result in EADC_DAT less than CMPDAT3 setting
#1 : 1
Conversion result in EADC_DAT great than or equal CMPDAT3 setting
End of enumeration elements list.
CHANNEL : Current Conversion Channel(Read Only)
bits : 16 - 20 (5 bit)
access : read-only
BUSY : Busy/Idle(Read Only)
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
#0 : 0
EADC is in idle state
#1 : 1
EADC is busy at conversion
End of enumeration elements list.
ADOVIF : All ADC Interrupt Flag Overrun Bits Check (Read Only)
Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1.
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1
#1 : 1
Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1
End of enumeration elements list.
STOVF : for All ADC Sample Module Start of Conversion Overrun Flags Check(Read Only)
Note: This bit will keep 1 when any SPOVFn Flag is equal to 1.
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1
#1 : 1
Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1
End of enumeration elements list.
AVALID : for All Sample Module ADC Result Data Register EADC_DAT Data Valid Flag Check(Read Only)
Note: This bit will keep 1 when any VALIDn Flag is equal to 1.
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
#0 : 0
None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1
#1 : 1
Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1
End of enumeration elements list.
AOV : for All Sample Module ADC Result Data Register Overrun Flags Check (Read Only)
Note: This bit will keep 1 when any Ovn Flag is equal to 1.
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
#0 : 0
None of sample module data register overrun flag Ovn (EADC_DATn[16]) is set to 1
#1 : 1
Any one of sample module data register overrun flag Ovn (EADC_DATn[16]) is set to 1
End of enumeration elements list.
ADC Status Register 3
address_offset : 0xFC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CURSPL : ADC Current Sample Module
This register show the current ADC is controlled by which sample module control logic modules.
If the ADC is Idle, this bit filed will set to 0x1F.
This is a read only register.
bits : 0 - 4 (5 bit)
access : read-only
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