Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :
DMIC Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN0 : Channel 0 Enable Bit
Set this bit to 1 to enable DMIC channel 0 operation.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel 0 Disabled
#1 : 1
Channel 0 Enabled
End of enumeration elements list.
CHEN1 : Channel 1 Enable Bit
Set this bit to 1 to enable DMIC channel 1 operation.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel 1 Disabled
#1 : 1
Channel 1 Enabled
End of enumeration elements list.
CHEN2 : Channel 2 Enable Bit
Set this bit to 1 to enable DMIC channel 2 operation.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel 2 Disabled
#1 : 1
Channel 2 Enabled
End of enumeration elements list.
CHEN3 : Channel 3 Enable Bit
Set this bit to 1 to enable DMIC channel 3 operation.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel 3 Disabled
#1 : 1
Channel 3 Enabled
End of enumeration elements list.
OSR : OSR Setting
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 0
Down sample 32
#001 : 1
Down sample 64
#010 : 2
Down sample 128
#011 : 3
Down sample 256
#100 : 4
Down sample 100 or 50
End of enumeration elements list.
LCHEDGE01 : Channel 01 Data Latch Edge
The data of DMIC channel 0 and channel 1 is latched on DMIC_DATA0 pin. This bit is used to select the data of DMIC channel 0 and channel 1 is latched on rising or falling edge of DMIC_CLK (DMIC bus clock).
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The data of channel 0 is latched on falling edge of DMIC_CLK. The data of channel 1 is latched on rising edge of DMIC_CLK
#1 : 1
The data of channel 0 is latched on rising edge of DMIC_CLK. The data of channel 1 is latched on falling edge of DMIC_CLK
End of enumeration elements list.
LCHEDGE23 : Channel 23 Data Latch Edge
The data of DMIC channel 2 and channel 3 is latched on DMIC_DATA1 pin. This bit is used to select the data of DMIC channel 2 and channel 3 is latched on rising or falling edge of DMIC_CLK (DMIC bus clock).
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The data of channel 2 is latched on falling edge of DMIC_CLK. The data of channel 3 is latched on rising edge of DMIC_CLK
#1 : 1
The data of channel 2 is latched on rising edge of DMIC_CLK. The data of channel 3 is latched on falling edge of DMIC_CLK
End of enumeration elements list.
DMIC FIFO Data Output Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FIFO : FIFO Data Output Register
DMIC contains 32 words (32x32 bit) data buffer for data receive. A read to this register pushes data out from FIFO data buffer and decrements the read pointer. This is the address that PDMA reads audio data from. The remaining data word number is indicated by FIFOPTR (DMIC_STATUS[8:4]).
bits : 0 - 23 (24 bit)
access : write-only
DMIC Clock Divider Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCLKDIV : Divider to generate the DMIC Working Main Clock
The value in this field is the frequency divider for generating the DMIC working main clock. The frequency is obtained according to the following equation.
where F_DMIC_CLK_SRC is the frequency of DMIC module clock source, which is defined in the clock control register DMICSEL (CLK_CLKSEL2[11:10]) and F_DMIC_MCLK is the frequency of DMIC working main clock (DMIC_MCLK).
bits : 0 - 7 (8 bit)
access : read-write
MCLKDIV : Divider to generate the DMIC Bus Clock
The value in this field is the frequency divider for generating the DMIC bus clock. The frequency is obtained according to the following equation.
where F_DMIC_MCLK is the frequency of DMIC working main clock (DMIC_MCLK) and F_DMIC_CLK is the frequency of DMIC bus clock (DMIC_CLK).
bits : 8 - 15 (8 bit)
access : read-write
TH : FIFO Threshold Level
If the valid data count of the FIFO data buffer is more than or equal to TH (DMIC_DIV[20:16]) setting, the THIF (DMIC_STATUS[2]) bit will set to 1, else the THIF (DMIC_STATUS[2]) bit will be cleared to 0.
bits : 16 - 20 (5 bit)
access : read-write
THIE : FIFO Threshold Interrupt
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
FIFO threshold interrupt Disabled
#1 : 1
FIFO threshold interrupt Enabled
End of enumeration elements list.
FCLR : FIFO Clear
Note 1: To clear the FIFO, need to write FCLR (DMIC_DIV[23:22]) to 11b, and can read the EMPTY (DMIC_STATUS[1]) bit to make sure that the FIFO has been cleared.
Note 2: This field is auto cleared by hardware.
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#11 : 3
Clear the FIFO
End of enumeration elements list.
DMIC Status Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FULL : FIFO Full Indicator (Read Only)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
FIFO is not full
#1 : 1
FIFO is full
End of enumeration elements list.
EMPTY : FIFO Empty Indicator (Read Only)
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
FIFO is not empty
#1 : 1
FIFO is empty
End of enumeration elements list.
THIF : FIFO Threshold Interrupt Status (Read Only)
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
The valid data count within the FIFO data buffer is less than the setting value of TH (DMIC_DIV[20:16])
#1 : 1
The valid data count within the FIFO data buffer is more than or equal to the setting value of TH (DMIC_DIV[20:16])
End of enumeration elements list.
FIFOPTR : FIFO Pointer (Read Only)
The FULL (DMIC_STATUS[0]) and FIFOPTR (DMIC_STATUS[8:4]) indicates the field that the valid data count within the DMIC FIFO buffer.
The maximum value shown in FIFOPTR (DMIC_STATUS[8:4]) is 31. When the using level of DMIC FIFO buffer equal to 32, The FULL (DMIC_STATUS[0]) is set to 1.
bits : 4 - 8 (5 bit)
access : read-only
DMIC PDMA Control Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMAEN : PDMA Transfer Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA data transfer Disabled
#1 : 1
PDMA data transfer Enabled
End of enumeration elements list.
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