\n
address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection :
VAD SINC Filter Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINCOSR : VAD SINC Filter OSR Setting
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
000 : 0
Down sample 48
001 : 1
Down sample 64
010 : 10
Down sample 96
End of enumeration elements list.
DATAOFF : VAD Sending Data to SRAM Control
When the ACTIVE (VAD_STATUS0[31]) goes high, the data will be transferred to SRAM to store which can be used for keyword detection later. After some time, if user needs to stop sending data to SRAM, write this bit to 1.
bits : 28 - 28 (1 bit)
access : read-write
SW : VAD Path Switch Control
After the ACTIVE(VAD_STATUS0[31]) goes high, it will automatically switch to the DMIC path. When the CPU is entering idle mode, write 1 to switch back to the VAD path.
Note 1: After switch back VAD path, user need to set this bit to 0.
Note 2: User need to set DMIC_CTL[3:0] to 1 and clear ACTIVE (VAD_STATUS0[31]) before set this bit 1.
bits : 29 - 29 (1 bit)
access : read-write
ACTCL : VAD Active Flag Clear
Note: After ACTIVE(VAD_STATUS0[31]) is cleared, user need to set set this bit to 0.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear ACTIVE(VAD_STATUS0[31])
End of enumeration elements list.
VADEN : VAD Enable Control
Note 1: When set this bit to 1, CHEN0 (DMIC_CTL[0]) will be set to 1 and CHEN1 (DMIC_CTL[1]), CHEN2 (DMIC_CTL[2]) and CHEN3 (DMIC_CTL[3]) will be set to 0 automatically.
Note 2: When set this bit to 1, DMIC_CLK is generated by VAD module.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
VAD Disabled
#1 : 1
VAD Enabled
End of enumeration elements list.
VAD Control Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STAT : Short Term Power Attack Time
Slow attack (e.g., 0x99): slow responding to voice, but more stable.
Fast attack (e.g., 0xCC): fast responding to voice, but more sensitive to other sounds.
Suggested default attack time setting: Long term power attack time (0x5), Short term power attack time (0xAA).
The Short Term Power , in order to detect the instant power of the voices, requires faster attack time, while Long Term Power , in order to get the averaged power of the background environment, requires slower attack time to maintain its stability. So the Short term power attack time should be always bigger than the Long term power attack time.
bits : 0 - 7 (8 bit)
access : read-write
LTAT : Long Term Power Attack Time
Slow attack (e.g., 0x5): less sensitive to environment change.
Fast attack (e.g., 0x8): more sensitive to environment change.
bits : 16 - 19 (4 bit)
access : read-write
VAD Control Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STTHREHWM : Short Term Power Threshold Upper Limit
To check if the incoming signal is big enough to be ready for VAD activation.
bits : 0 - 15 (16 bit)
access : read-write
STTHRELWM : Short Term Power Threshold Lower Limit
To check if the incoming signal is small enough so that VAD status can be terminated.
bits : 16 - 31 (16 bit)
access : read-write
VAD Control Register 2
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTTHRE : Long Term Power Threshold
To check the background energy, also serve as the lower limit of long term power. When the long term power value is lower than the threshold, it will be set to the threshold value for VAD decision.
bits : 16 - 31 (16 bit)
access : read-write
VAD Control Register 3
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEVTHRE : Deviation Threshold
To check if the incoming signal is substantially bigger than its background. This may work to exclude breath sound as it is slowly varying, but not other sounds (e.g., footsteps, hand claps) with sudden amplitude increase.
Small: easy to trigger, good for far-field pick-up, but requiring quiet environment.
Large: good for handheld applications, but requiring louder voice to trigger.
bits : 0 - 15 (16 bit)
access : read-write
HOT : Hang Over time
Hang Over time setting, means how many clocks (CLKSD) of the ACTIVE (VAD_STATUS0[31]) staying high when the calculation is no longer bigger than the threshold
bits : 16 - 31 (16 bit)
access : read-write
VAD Status Read-back Register 0
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STP : Short Term Signal Power (Read Only)
This field shows the short term signal power value.
bits : 0 - 15 (16 bit)
access : read-only
ACTIVE : VAD Activation Flag (Read Only)
When the voice active event occurs, this bit will be set to 1.
Note: When wake-up from idle mode, user need to set CHENn DMIC_CTL[3:0] for DMIC path normal operation.
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
No effect
#1 : 1
Voice detected
End of enumeration elements list.
VAD Status Read-back Register 1
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DEV : Deviation (Read Only)
This field shows deviation of the Long Term Signal Power and Short Term Signal Power.
bits : 0 - 15 (16 bit)
access : read-only
LTP : Long Term Signal Power (Read Only)
This field shows the long term signal power value.
bits : 16 - 31 (16 bit)
access : read-only
VAD Biquad Filter Control Register 0
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BIQA1 : VAD Biquad Filter Coefficient
Biquad Filter Coefficient a1, in 3 intergers + 13 fractional bits
bits : 0 - 15 (16 bit)
access : read-write
BIQA2 : VAD Biquad Filter Coefficient
Biquad Filter Coefficient a2, in 3 intergers + 13 fractional bits.
bits : 16 - 31 (16 bit)
access : read-write
VAD Biquad Filter Control Register 1
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BIQB0 : VAD Biquad Filter Coefficient
Biquad Filter Coefficient b0, in 3 intergers + 13 fractional bits.
bits : 0 - 15 (16 bit)
access : read-write
BIQB1 : VAD Biquad Filter Coefficient
Biquad Filter Coefficient b1, in 3 intergers + 13 fractional bits.
bits : 16 - 31 (16 bit)
access : read-write
VAD Biquad Filter Control Register 2
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BIQB2 : VAD Biquad Filter Coefficient
Biquad Filter Coefficient b2, in 3 intergers + 13 fractional bits.
bits : 0 - 15 (16 bit)
access : read-write
BIQEN : VAD Biquad Filter Enable Bit
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
VAD Biquad Filter Disabled
#1 : 1
VAD Biquad Filter Enabled
End of enumeration elements list.
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