SYS_PDID (PDID)

SYS_IPRST2 (IPRST2)

SYS_REGLCTL (REGLCTL)

SYS_RCADJ (RCADJ)

SYS_BODCTL (BODCTL)

SYS_USBPHY (USBPHY)

SYS_GPA_MFPL (GPA_MFPL)

SYS_GPA_MFPH (GPA_MFPH)

SYS_GPB_MFPL (GPB_MFPL)

SYS_GPB_MFPH (GPB_MFPH)

SYS_RSTSTS (RSTSTS)

SYS_GPC_MFPL (GPC_MFPL)

SYS_AHBMCTL (AHBMCTL)

SYS_GPC_MFPH (GPC_MFPH)

SYS_GPD_MFPL (GPD_MFPL)

SYS_GPD_MFPH (GPD_MFPH)

SYS_UCID0 (UCID0)

SYS_UCID1 (UCID1)

SYS_UCID2 (UCID2)

SYS_UCID3 (UCID3)

SYS_IPRST0 (IPRST0)

SYS_DSPCTL (DSPCTL)

SYS_IPRST1 (IPRST1)

SYS_P2PNTFY0 (P2PNTFY0)

SYS_P2PSTS0 (P2PSTS0)

SYS_P2PNTFY1 (P2PNTFY1)

SYS_P2PSTS1 (P2PSTS1)

SYS_IRCTCTL (IRCTCTL)

SYS_IRCTIEN (IRCTIEN)

SYS_IRCTISTS (IRCTISTS)

PDID : Part Device Identification Number (Read Only) This register reflects device part number code. Software can read this register to identify which device is used.
bits : 0 - 31 (32 bit)
access : read-only

DPWMRST : DPWM Controller Reset
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0RST : PWM0 Controller Reset
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REGLCTL : Register Lock Control Code (Write Only) Some registers have a write-protection function. To write to these registers, this write protection must be by writing the sequence value '59h', '16h', '88h' to this address. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protected registers can be write accessed. Register Lock Control Disable Index (Read Only) The Protected registers are: SYS_IPRST0: address 0x4000_0008 SYS_BODCTL: address 0x4000_0018 SYS_PORCTL: address 0x4000_0024 SYS_USBPHY: address 0x4000_002C SYS_DSPCTL: address 0x4000_00A4 SYS_PTPNTFY0: address 0x4000_00E0 SYS_PTPNTFY1: address 0x4000_00E8 CLK_PWRCTL: address 0x4000_0200 (bit[6] is not protected for power-down wake-up interrupt clear) CLK_APBCLK0 [0]: address 0x4000_0208 (bit[0] is watchdog clock enable) CLK_CLKSEL0: address 0x4000_0210 (for HCLK and CPU STCLK clock source select) CLK_CLKSEL1 [1:0]: address 0x4000_0214 (for watchdog clock source select) CLK_CLKSEL1 [31:30]: address 0x4000_0214 (for window watchdog clock source select) CLK_CLKDSTS: address 0x4000_0274 NMIEN: address 0x4000_0300 OMC_ISPCTL: address 0x4000_C000 (ISP Control register) OMC_ISPTRG: address 0x4000_C010 (ISP Trigger Control register) OMC_ISPSTS: address 0x4000_C040 WDT_CTL: address 0x4004_0000 AHBMCTL: address 0x4000_0400 CLK_PLLCTL: address 0x4000_0240 PWM_CTL0: address 0x4005_8000 PWM_DTCTL0_1: address 0x4005_8070 PWM_DTCTL2_3: address 0x4005_8074 PWM_DTCTL4_5: address 0x4005_8078
bits : 0 - 7 (8 bit)
access : write-only

Enumeration:

End of enumeration elements list.

RCADJ : RC48M Trim Value (Write Protect) This bit is the protected bit, which means programming it needs to write '59h', '16h', '88h' to address 0x5000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address SYS_BA+0x100. This field reflects the HIRC trim value. Software can update HIRC trim value by writing this field. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 9 (10 bit)
access : read-write

BODEN : Brown-out Detector Enable Bit (Write Protected) The default value is set by user configuration block register CBODEN (CONFIG0 [19]). Note 1: The reset value of SYS_BODCTL[0] is determined by user configuration block. Note 2: Brown-out detector can only work when both BODEN(SYS_BODCTL[0]) and LVREN(SYS_BODCTL[7]) are set to 1. Note 3: LIRC must be enabled. Note 4: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODRSTEN : Brown-out Reset Enable Bit (Write Protected) The default value is set by user configuration block register CBORST(CONFIG0[20]) bit . Note 1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. BOD interrupt will latch until BODEN is set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). Note 2: The reset value of SYS_BODCTL[3] is determined by user configuration block. Note 3: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODIF : Brown-out Detector Interrupt Flag Note: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODLPM : Brown-out Detector Low Power Mode (Write Protected) Note1: The low power mode can reduce the current to about 1/10 but slow the BOD response. Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODOUT : Brown-out Detector Output Status The detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function is disabled and this bit will be 0.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVREN : Low Voltage Reset Enable Bit (Write Protected) The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODDGSEL : Brown-out Detector Output De-glitch Time Select (Write Protected) Note: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVRDGSEL : LVR Output De-glitch Time Select (Write Protected) Note: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODVL : Brown-out Detector Threshold Voltage Selection (Write Protected) The default value is set by user configuration block register CBOV (CONFIG0 [23:21]). Note: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USBEN : USB PHY Enable (Write Protect) This bit is used to enable/disable USB PHY function.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA0MFP : PA.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PA1MFP : PA.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PA2MFP : PA.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PA3MFP : PA.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PA4MFP : PA.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PA5MFP : PA.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PA6MFP : PA.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PA7MFP : PA.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PA8MFP : PA.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PA9MFP : PA.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PA10MFP : PA.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PA11MFP : PA.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PA12MFP : PA.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PA13MFP : PA.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PA14MFP : PA.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PA15MFP : PA.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PB0MFP : PB.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PB1MFP : PB.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PB2MFP : PB.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PB3MFP : PB.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PB4MFP : PB.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PB5MFP : PB.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PB6MFP : PB.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PB7MFP : PB.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PB8MFP : PB.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PB10MFP : PB.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PB11MFP : PB.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PB12MFP : PB.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PB13MFP : PB.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PB14MFP : PB.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PB15MFP : PB.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PORF : POR Reset Flag The POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINRF : NRESET Pin Reset Flag The nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTRF : WDT Reset Flag The WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. Note1: Write 1 to clear this bit to 0. Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVRF : LVR Reset Flag The LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODRF : BOD Reset Flag The BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSRF : System Reset Flag The system reset flag is set by the 'Reset Signal' from the Cortex-M0 Core to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PMURF : PMU Reset Flag Note: Write 1 to clear this bit to 0.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPURF : CPU Reset Flag The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 Core and OTP Memory Controller (OMC). Note: Write 1 to clear this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPULKRF : CPU Lockup Reset Flag Note: Write 1 to clear this bit to 0. Note: when ICE is connected, CPU lockup event sets this flag to 1 but will not reset chip.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PC0MFP : PC.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PC1MFP : PC.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PC2MFP : PC.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PC3MFP : PC.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PC4MFP : PC.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PC5MFP : PC.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PC6MFP : PC.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PC7MFP : PC.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

INTACTEN : Highest AHB Bus Priority of Cortex M0 Core Enable Bit (Write Protected) Enable Cortex-M0 Core With Highest AHB Bus Priority In AHB Bus Matrix Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PC8MFP : PC.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PC9MFP : PC.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PC10MFP : PC.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PC11MFP : PC.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PC12MFP : PC.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PC13MFP : PC.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PC14MFP : PC.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PC15MFP : PC.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PD0MFP : PD.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PD1MFP : PD.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PD2MFP : PD.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PD3MFP : PD.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PD4MFP : PD.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PD5MFP : PD.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PD6MFP : PD.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PD7MFP : PD.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PD8MFP : PD.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PD9MFP : PD.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PD10MFP : PD.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PD11MFP : PD.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PD12MFP : PD.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PD13MFP : PD.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PD14MFP : PD.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PD15MFP : PD.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

UCID : Unique Customer ID 0 (Read Only) This register reflects unique customer ID 0.
bits : 0 - 31 (32 bit)
access : read-only

UCID : Unique Customer ID 1 (Read Only) This register reflects unique customer ID 1.
bits : 0 - 31 (32 bit)
access : read-only

UCID : Unique Customer ID 2 (Read Only) This register reflects unique customer ID 2.
bits : 0 - 31 (32 bit)
access : read-only

UCID : Unique Customer ID 3 (Read Only) This register reflects unique customer ID 3.
bits : 0 - 31 (32 bit)
access : read-only

CHIPRST : Chip One-shot Reset (Write Protected) Setting this bit will reset the whole chip, including Processor core and all peripherals this bit will automatically return to 0 after the 2 clock cycles. The CHIPRST is same as the POR reset, all the chip controllers are reset and the chip settings from user configuration block are also reloaded. About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2 Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPURST : Processor Core One-shot Reset (Write Protected) Setting this bit will only reset the processor core and OTP Memory Controller(OMC) this bit will automatically return to 0 after the 2 clock cycles. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMARST : PDMA Controller Reset (Write Protected) Setting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRCRST : CRC Calculation Controller Reset (Write Protected) Set this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to set this bit to 0 to release from the reset state. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRPTRST : CRYPTO Controller Reset (Write Protect) Setting this bit to 1 will generate a reset signal to the CRYPTO controller. User needs to set this bit to 0 to release from the reset state. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPIMRST : SPIM Controller Reset (Write Protected) Setting this bit to 1 will generate a reset signal to the SPIM controller. User needs to set this bit to 0 to release from the reset sate. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DSPRST : DSP Reset Control (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RUNSTALL : DSP RunStall Control (Write Protected)
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OCDRESET : DSP OCDHaltOnReset Control (Write Protected) Note : This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MCUHALTEN : MCU Halt Control (Write Protected) Enable DSP halt MCU when DSP at break status MCU should also at debugging status Note : This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIORST : GPIO Controller Reset
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0RST : Timer0 Controller Reset
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1RST : Timer1 Controller Reset
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2RST : Timer2 Controller Reset
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR3RST : Timer3 Controller Reset
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C0RST : I2C0 Controller Reset
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C1RST : I2C1 Controller Reset
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI0RST : SPI0 Controller Reset
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI2RST : SPI2 Controller Reset
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMICRST : DMIC Controller Reset
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART0RST : UART0 Controller Reset
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART1RST : UART1 Controller Reset
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USBDRST : USBD Controller Reset
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2S0RST : I2S0 Controller Reset
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2S1RST : I2S1 Controller Reset
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HIRCCKF : HIRC Clock Filter Enable Bit
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P2PNTFY : Processor to Proccessor Notification Flag (Write Protect) Each bit in this field represent a notification flag a Sending Processor can set in order to generate a P2P0_INT at the Receiving Processor. Write operation: Engineering note: When reading this register the value will be a mirrored value of SYS_P2PSTS0. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P2PSTS : Processor to Proccessor Notification Status (Write Protect) A Receiving Processor SW can read this register in order to determin which notification flag was set by the Sending Processor. Each bit in this register reflects a notification. Writing operation If any bit in this register is 1, P2P0_INT will be asserted.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P2PNTFY : Processor to Proccessor Notification Flag (Write Protect) Each bit in this field represent a notification flag a Sending Processor can set in order to generate a P2P1_INT at the Receiving Processor. Write operation: Engineering note: When reading this register the value will be a mirrored value of SYS_P2PSTS1. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P2PSTS : Processor to Proccessor Notification Status (Write Protect) A Receiving Processor SW can read this register in order to determin which notification flag was set by the Sending Processor. Each bit in this register reflects a notification. Writing operation If any bit in this register is 1, P2P1_INT will be asserted.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQSEL : Trim Frequency Selection This field indicates the target frequency of 48 MHz and 49.152 MHz internal high speed RC oscillator (HIRC) auto trim. During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LOOPSEL : Trim Calculation Loop Selection This field defines that trim value calculation is based on how many reference clocks. Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RETRYCNT : Trim Value Update Limitation Count This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. Once the HIRC locked, the internal trim value update counter will be reset. If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CESTOPEN : Clock Error Stop Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REFCKSEL : Reference Clock Selection
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TFAILIEN : Trim Failure Interrupt Enable Bit This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]). If this bit is high and TFAILIF(SYS_IRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKEIEN : Clock Error Interrupt Enable Bit This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. If this bit is set to1, and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQLOCK : HIRC Frequency Lock Status This bit indicates the HIRC frequency is locked. This is a status bit and doesn't trigger any interrupt Write 1 to clear this to 0. This bit will be set automatically, if the frequecy is lock and the RC_TRIM is enabled.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TFAILIF : Trim Failure Interrupt Status This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_iRCTCTL[1:0]) will be cleared to 00 by hardware automatically. If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKERRIF : Clock Error Interrupt Status When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1. If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.