\n

INT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :

address_offset : 0x10 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :

address_offset : 0x84 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

Registers

INT_MNMIEN (MNMIEN)

INT_DNMIEN (DNMIEN)

INT_DNMISTS (DNMISTS)

INT_DINTEN (DINTEN)

INT_MNMISTS (MNMISTS)

INT_MINTEN (MINTEN)

INT_MIRQ (MIRQ)

INT_DIRQ (DIRQ)


INT_MNMIEN (MNMIEN)

MCU NMI Source Interrupt Enable Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_MNMIEN INT_MNMIEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BODINT IRCINT PWRWUINT CLKFAIL XCLKFAIL RTCINT EINT0 EINT1 UART0INT UART1INT

BODINT : BOD NMI Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

BOD NMI source Disabled

#1 : 1

BOD NMI source Enabled

End of enumeration elements list.

IRCINT : IRC TRIM NMI Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

IRC TRIM NMI source Disabled

#1 : 1

IRC TRIM NMI source Enabled

End of enumeration elements list.

PWRWUINT : Power-down Mode Wake-up NMI Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Power-down mode wake-up NMI source Disabled

#1 : 1

Power-down mode wake-up NMI source Enabled

End of enumeration elements list.

CLKFAIL : Clock Fail Detected NMI Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock fail detected interrupt NMI source Disabled

#1 : 1

Clock fail detected interrupt NMI source Enabled

End of enumeration elements list.

XCLKFAIL : MCLK Input Fail Detected NMI Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

MCLK input fail detected interrupt NMI source Disabled

#1 : 1

MCLK input fail detected interrupt NMI source Enabled

End of enumeration elements list.

RTCINT : RTC NMI Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

RTC NMI source Disabled

#1 : 1

RTC NMI source Enabled

End of enumeration elements list.

EINT0 : External Interrupt 0 NMI Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

External interrupt 0 NMI source Disabled

#1 : 1

External interrupt 0 NMI source Enabled

End of enumeration elements list.

EINT1 : External Interrupt 1 NMI Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

External interrupt 1 NMI source Disabled

#1 : 1

External interrupt 1 NMI source Enabled

End of enumeration elements list.

UART0INT : UART0 NMI Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART0 NMI source Disabled

#1 : 1

UART0 NMI source Enabled

End of enumeration elements list.

UART1INT : UART1 NMI Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART1 NMI source Disabled

#1 : 1

UART1 NMI source Enabled

End of enumeration elements list.


INT_DNMIEN (DNMIEN)

DSP NMI Source Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_DNMIEN INT_DNMIEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BODINT IRCINT PWRWUINT CLKFAIL XCLKFAIL RTCINT EINT0 EINT1 UART0INT UART1INT

BODINT : BOD NMI Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

BOD NMI source Disabled

#1 : 1

BOD NMI source Enabled

End of enumeration elements list.

IRCINT : IRC TRIM NMI Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

IRC TRIM NMI source Disabled

#1 : 1

IRC TRIM NMI source Enabled

End of enumeration elements list.

PWRWUINT : Power-down Mode Wake-up NMI Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Power-down mode wake-up NMI source Disabled

#1 : 1

Power-down mode wake-up NMI source Enabled

End of enumeration elements list.

CLKFAIL : Clock Fail Detected NMI Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock fail detected interrupt NMI source Disabled

#1 : 1

Clock fail detected interrupt NMI source Enabled

End of enumeration elements list.

XCLKFAIL : MCLK Input Fail Detected NMI Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

MCLK input fail detected interrupt NMI source Disabled

#1 : 1

MCLK input fail detected interrupt NMI source Enabled

End of enumeration elements list.

RTCINT : RTC NMI Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

RTC NMI source Disabled

#1 : 1

RTC NMI source Enabled

End of enumeration elements list.

EINT0 : External Interrupt 0 NMI Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

External interrupt 0 NMI source Disabled

#1 : 1

External interrupt 0 NMI source Enabled

End of enumeration elements list.

EINT1 : External Interrupt 1 NMI Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

External interrupt 1 NMI source Disabled

#1 : 1

External interrupt 1 NMI source Enabled

End of enumeration elements list.

UART0INT : UART0 NMI Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART0 NMI source Disabled

#1 : 1

UART0 NMI source Enabled

End of enumeration elements list.

UART1INT : UART1 NMI Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART1 NMI source Disabled

#1 : 1

UART1 NMI source Enabled

End of enumeration elements list.


INT_DNMISTS (DNMISTS)

DSP NMI Source Interrupt Status Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INT_DNMISTS INT_DNMISTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BODINT IRCINT PWRWUINT CLKFAIL XCLKFAIL RTCINT EINT0 EINT1 UART0INT UART1INT

BODINT : BOD Interrupt Flag (Read Only)
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

BOD interrupt is deasserted

#1 : 1

BOD interrupt is asserted

End of enumeration elements list.

IRCINT : IRC TRIM Interrupt Flag (Read Only)
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

HIRC TRIM interrupt is deasserted

#1 : 1

HIRC TRIM interrupt is asserted

End of enumeration elements list.

PWRWUINT : Power-down Mode Wake-up Interrupt Flag (Read Only)
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Power-down mode wake-up interrupt is deasserted

#1 : 1

Power-down mode wake-up interrupt is asserted

End of enumeration elements list.

CLKFAIL : Clock Fail Detected Interrupt Flag (Read Only)
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Clock fail detected interrupt is deasserted

#1 : 1

Clock fail detected interrupt is asserted

End of enumeration elements list.

XCLKFAIL : XCLK Fail Detected Interrupt Flag (Read Only)
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

MCLK input fail detected interrupt is deasserted

#1 : 1

MCLK input fail detected interrupt is asserted

End of enumeration elements list.

RTCINT : RTC Interrupt Flag (Read Only)
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

RTC interrupt is deasserted

#1 : 1

RTC interrupt is asserted

End of enumeration elements list.

EINT0 : External Interrupt 0 Interrupt Flag (Read Only)
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

#0 : 0

External Interrupt 0 interrupt is deasserted

#1 : 1

External Interrupt 0 interrupt is asserted

End of enumeration elements list.

EINT1 : External Interrupt 1 Interrupt Flag (Read Only)
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

#0 : 0

External Interrupt 1 interrupt is deasserted

#1 : 1

External Interrupt 1 interrupt is asserted

End of enumeration elements list.

UART0INT : UART0 Interrupt Flag (Read Only)
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

#0 : 0

UART0 interrupt is deasserted

#1 : 1

UART0 interrupt is asserted

End of enumeration elements list.

UART1INT : UART1 Interrupt Flag (Read Only)
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

#0 : 0

UART1 interrupt is deasserted

#1 : 1

UART1 interrupt is asserted

End of enumeration elements list.


INT_DINTEN (DINTEN)

DSP Interrupt Source Enable Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_DINTEN INT_DINTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPAEN GPBEN GPCEN GPDEN WDTEN WWDTEN IRCEN CLKFEN XCLKFEN PWRWUEN BODEN PWM0P0EN PWM0P1EN PWM0P2EN DMICEN VADEN

GPAEN : GPA DSP Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPA DSP Interrupt source Disabled

#1 : 1

GPA DSP Interrupt source Enabled

End of enumeration elements list.

GPBEN : GPB DSP Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPB DSP Interrupt source Disabled

#1 : 1

GPB DSP Interrupt source Enabled

End of enumeration elements list.

GPCEN : GPC DSP Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPC DSP Interrupt source Disabled

#1 : 1

GPC DSP Interrupt source Enabled

End of enumeration elements list.

GPDEN : GPD DSP Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPD DSP Interrupt source Disabled

#1 : 1

GPD DSP Interrupt source Enabled

End of enumeration elements list.

WDTEN : WDT DSP Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

WDT DSP Interrupt source Disabled

#1 : 1

WDT DSP Interrupt source Enabled

End of enumeration elements list.

WWDTEN : WWDT DSP Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

WWDT DSP Interrupt source Disabled

#1 : 1

WWDT DSP Interrupt source Enabled

End of enumeration elements list.

IRCEN : IRC DSP Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

IRC DSP Interrupt source Disabled

#1 : 1

IRC DSP Interrupt source Enabled

End of enumeration elements list.

CLKFEN : CLKFAIL DSP Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

CLKFAIL DSP Interrupt source Disabled

#1 : 1

CLKFAIL DSP Interrupt source Enabled

End of enumeration elements list.

XCLKFEN : XCLKFAIL DSP Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

XCLKFAIL DSP Interrupt source Disabled

#1 : 1

XCLKFAIL DSP Interrupt source Enabled

End of enumeration elements list.

PWRWUEN : PWRWU DSP Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWRWU DSP Interrupt source Disabled

#1 : 1

PWRWU DSP Interrupt source Enabled

End of enumeration elements list.

BODEN : BOD DSP Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

BOD DSP Interrupt source Disabled

#1 : 1

BOD DSP Interrupt source Enabled

End of enumeration elements list.

PWM0P0EN : PWM0_P0 DSP Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0_P0 DSP Interrupt source Disabled

#1 : 1

PWM0_P0 DSP Interrupt source Enabled

End of enumeration elements list.

PWM0P1EN : PWM0_P1 DSP Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0_P1 DSP Interrupt source Disabled

#1 : 1

PWM0_P1 DSP Interrupt source Enabled

End of enumeration elements list.

PWM0P2EN : PWM0_P2 DSP Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0_P2 DSP Interrupt source Disabled

#1 : 1

PWM0_P2 DSP Interrupt source Enabled

End of enumeration elements list.

DMICEN : DMIC DSP Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMIC DSP Interrupt source Disabled

#1 : 1

DMIC DSP Interrupt source Enabled

End of enumeration elements list.

VADEN : VAD DSP Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

VAD DSP Interrupt source Disabled

#1 : 1

VAD DSP Interrupt source Enabled

End of enumeration elements list.


INT_MNMISTS (MNMISTS)

MCU NMI Source Interrupt Status Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INT_MNMISTS INT_MNMISTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BODINT IRCINT PWRWUINT CLKFAIL XCLKFAIL RTCINT EINT0 EINT1 UART0INT UART1INT

BODINT : BOD Interrupt Flag (Read Only)
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

BOD interrupt is deasserted

#1 : 1

BOD interrupt is asserted

End of enumeration elements list.

IRCINT : IRC TRIM Interrupt Flag (Read Only)
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

HIRC TRIM interrupt is deasserted

#1 : 1

HIRC TRIM interrupt is asserted

End of enumeration elements list.

PWRWUINT : Power-down Mode Wake-up Interrupt Flag (Read Only)
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Power-down mode wake-up interrupt is deasserted

#1 : 1

Power-down mode wake-up interrupt is asserted

End of enumeration elements list.

CLKFAIL : Clock Fail Detected Interrupt Flag (Read Only)
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Clock fail detected interrupt is deasserted

#1 : 1

Clock fail detected interrupt is asserted

End of enumeration elements list.

XCLKFAIL : XCLK Fail Detected Interrupt Flag (Read Only)
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

MCLK input fail detected interrupt is deasserted

#1 : 1

MCLK input fail detected interrupt is asserted

End of enumeration elements list.

RTCINT : RTC Interrupt Flag (Read Only)
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

RTC interrupt is deasserted

#1 : 1

RTC interrupt is asserted

End of enumeration elements list.

EINT0 : External Interrupt 0 Interrupt Flag (Read Only)
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

#0 : 0

External Interrupt 0 interrupt is deasserted

#1 : 1

External Interrupt 0 interrupt is asserted

End of enumeration elements list.

EINT1 : External Interrupt 1 Interrupt Flag (Read Only)
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

#0 : 0

External Interrupt 1 interrupt is deasserted

#1 : 1

External Interrupt 1 interrupt is asserted

End of enumeration elements list.

UART0INT : UART0 Interrupt Flag (Read Only)
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

#0 : 0

UART0 interrupt is deasserted

#1 : 1

UART0 interrupt is asserted

End of enumeration elements list.

UART1INT : UART1 Interrupt Flag (Read Only)
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

#0 : 0

UART1 interrupt is deasserted

#1 : 1

UART1 interrupt is asserted

End of enumeration elements list.


INT_MINTEN (MINTEN)

MCU Interrupt Source Enable Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_MINTEN INT_MINTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTEN WWDTEN IRCEN CLKFEN XCLKFEN PWRWUEN BODEN PWM0P0EN PWM0P1EN PWM0P2EN DMICEN VADEN

WDTEN : WDT MCU Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

WDT MCU Interrupt source Disabled

#1 : 1

WDT MCU Interrupt source Enabled

End of enumeration elements list.

WWDTEN : WWDT MCU Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

WWDT MCU Interrupt source Disabled

#1 : 1

WWDT MCU Interrupt source Enabled

End of enumeration elements list.

IRCEN : IRC MCU Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

IRC MCU Interrupt source Disabled

#1 : 1

IRC MCU Interrupt source Enabled

End of enumeration elements list.

CLKFEN : CLKFAIL MCU Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

CLKFAIL MCU Interrupt source Disabled

#1 : 1

CLKFAIL MCU Interrupt source Enabled

End of enumeration elements list.

XCLKFEN : XCLKFAIL MCU Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

XCLKFAIL MCU Interrupt source Disabled

#1 : 1

XCLKFAIL MCU Interrupt source Enabled

End of enumeration elements list.

PWRWUEN : PWRWU MCU Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWRWU MCU Interrupt source Disabled

#1 : 1

PWRWU MCU Interrupt source Enabled

End of enumeration elements list.

BODEN : BOD MCU Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

BOD MCU Interrupt source Disabled

#1 : 1

BOD MCU Interrupt source Enabled

End of enumeration elements list.

PWM0P0EN : PWM0_P0 MCU Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0_P0 MCU Interrupt source Disabled

#1 : 1

PWM0_P0 MCU Interrupt source Enabled

End of enumeration elements list.

PWM0P1EN : PWM0_P1 MCU Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0_P1 MCU Interrupt source Disabled

#1 : 1

PWM0_P1 MCU Interrupt source Enabled

End of enumeration elements list.

PWM0P2EN : PWM0_P2 MCU Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0_P2 MCU Interrupt source Disabled

#1 : 1

PWM0_P2 MCU Interrupt source Enabled

End of enumeration elements list.

DMICEN : DMIC MCU Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMIC MCU Interrupt source Disabled

#1 : 1

DMIC MCU Interrupt source Enabled

End of enumeration elements list.

VADEN : VAD MCU Interrupt Source Enable (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

VAD MCU Interrupt source Disabled

#1 : 1

VAD MCU Interrupt source Enabled

End of enumeration elements list.


INT_MIRQ (MIRQ)

MCU Interrupt Request Source Register
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_MIRQ INT_MIRQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ

IRQ : MCU IRQ Source Register The INT_MIRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to MCU.
bits : 0 - 31 (32 bit)
access : read-write


INT_DIRQ (DIRQ)

DSP Interrupt Request Source Register
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_DIRQ INT_DIRQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ

IRQ : DSP IRQ Source Register The INT_DIRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to DSP.
bits : 0 - 25 (26 bit)
access : read-write



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