Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x34 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x50 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x60 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x70 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x90 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection :
System Power-down Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTEN : HXT Enable Bit (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
External high speed crystal (HXT) Disabled
#1 : 1
External high speed crystal (HXT) Enabled
End of enumeration elements list.
LXTEN : LXT Enable Bit (Write Protected)
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: The reset value of this bit is 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
External low speed crystal (LXT) Disabled
#1 : 1
External low speed crystal (LXT) Enabled
End of enumeration elements list.
HIRCEN : HIRC Enable Bit (Write Protected)
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: The reset value of this bit is 1.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal high speed RC oscillator (HIRC) Disabled
#1 : 1
Internal high speed RC oscillator (HIRC) Enabled
End of enumeration elements list.
LIRCEN : LIRC Enable Bit (Write Protected)
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: The reset value of this bit is 1.
Note 3: The value of this bit must be kept 1.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal low speed RC oscillator (LIRC) Disabled
#1 : 1
Internal low speed RC oscillator (LIRC) Enabled
End of enumeration elements list.
PDWKDLY : Enable the Wake-up Delay Counter (Write Protected)
When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
The delayed clock cycle is 4096 clock cycles when chip works at external high speed crystal oscillator (HXT), and 128 clock cycles when chip works at internal high speed RC oscillator (HIRC).
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock cycles delay Disabled
#1 : 1
Clock cycles delay Enabled
End of enumeration elements list.
PDWKIEN : Power-down Mode Wake-up Interrupt Enable Bit (Write Protected)
Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high.
Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Power-down mode wake-up interrupt Disabled
#1 : 1
Power-down mode wake-up interrupt Enabled
End of enumeration elements list.
PDWKIF : Power-down Mode Wake-up Interrupt Status
Set by 'Power-down wake-up event', it indicates that resume from Power-down mode'
The flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter.
Note1: Write 1 to clear the bit to 0.
Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
bits : 6 - 6 (1 bit)
access : read-write
PDEN : System Power-down Enable (Write Protected)
When this bit is set to 1, Power-down mode is enabled and chip
keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.
When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down.
In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode.
In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip will not enter Power-down mode after CPU sleep command WFI
#1 : 1
Chip enters Power-down mode after CPU sleep command WFI
End of enumeration elements list.
PDWTCPU : this Bit Control the Power-down Entry Condition (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#1 : 1
Chip enters Power-down mode when the both PDWTCPU and PDEN bits are set to 1 and CPU runs WFI instruction
End of enumeration elements list.
HXTGAIN : HXT Gain Control Bit (Write Protected)
This is a protected register. Please refer to open lock sequence to program it.
Gain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled, crystal will consume more power than gain control off.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
HXT frequency is lower than from 8 MHz
#01 : 1
HXT frequency is from 8 MHz to 12 MHz
#10 : 2
HXT frequency is from 12 MHz to 16 MHz
#11 : 3
HXT frequency is higher than 16 MHz
End of enumeration elements list.
HXTSELTYP : HXT Crystal Type Select Bit (Write Protected)
This is a protected register. Please refer to open lock sequence to program it.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Select INV type
#1 : 1
Select GM type
End of enumeration elements list.
HXTTBEN : HXT Crystal TURBO Mode (Write Protected)
This is a protected register. Please refer to open lock sequence to program it.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
HXT Crystal TURBO mode disabled
#1 : 1
HXT Crystal TURBO mode enabled
End of enumeration elements list.
Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLKSEL : HCLK Clock Source Selection (Write Protected)
Before clock switching, the related clock sources (both pre-select and new-select) must be turned on and stable flag must be 1.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from HXT
#001 : 1
Clock source from LXT
#010 : 2
Clock source from PLL
#011 : 3
Clock source from LIRC
#111 : 7
Clock source from HIRC
End of enumeration elements list.
STCLKSEL : SysTick Clock Source Selection (Write Protected)
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from HXT
#001 : 1
Clock source from LXT
#010 : 2
Clock source from HXT/2
#011 : 3
Clock source from HCLK/2
#111 : 7
Clock source from HIRC/2
End of enumeration elements list.
HIRCFSEL : Internal High Speed RC Oscillator Frequency Selection. (Write Protect)
Determines which trim setting to use for internal high speed RC oscillator.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
49.152 MHz
#1 : 1
48.0 MHz
End of enumeration elements list.
Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTSEL : Watchdog Timer Clock Source Selection (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reserved. Do not use
#01 : 1
Clock source from external low speed crystal oscillator (LXT)
#10 : 2
Clock source from HCLK/2048
#11 : 3
Clock source from internal low speed RC oscillator (LIRC)
End of enumeration elements list.
TMR0SEL : TIMER0 Clock Source Selection
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from external low speed crystal oscillator (LXT)
#010 : 2
Clock source from PCLK0
#011 : 3
Clock source from external clock TM0 pin
#101 : 5
Clock source from internal low speed RC oscillator (LIRC)
#111 : 7
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
TMR1SEL : TIMER1 Clock Source Selection
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from external low speed crystal oscillator (LXT)
#010 : 2
Clock source from PCLK0
#011 : 3
Clock source from external clock TM1 pin
#101 : 5
Clock source from internal low speed RC oscillator (LIRC)
#111 : 7
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
TMR2SEL : TIMER2 Clock Source Selection
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from external low speed crystal oscillator (LXT)
#010 : 2
Clock source from PCLK1
#011 : 3
Clock source from external clock TM2 pin
#101 : 5
Clock source from internal low speed RC oscillator (LIRC)
#111 : 7
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
TMR3SEL : TIMER3 Clock Source Selection
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from external low speed crystal oscillator (LXT)
#010 : 2
Clock source from PCLK1
#011 : 3
Clock source from external clock TM3 pin
#101 : 5
Clock source from internal low speed RC oscillator (LIRC)
#111 : 7
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
UART0SEL : UART0 Clock Source Selection
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from external low speed crystal oscillator (LXT)
#11 : 3
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
UART1SEL : UART1 Clock Source Selection
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from external low speed crystal oscillator (LXT)
#11 : 3
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
CLKOSEL : Clock Divider Clock Source Selection
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external high speed crystal oscillator (HXT)
#01 : 1
Clock source from external low speed crystal oscillator (LXT)
#10 : 2
Clock source from HCLK
#11 : 3
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
WWDTSEL : Window Watchdog Timer Clock Source Selection
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#10 : 2
Clock source from HCLK/2048
#11 : 3
Clock source from internal low speed RC oscillator (LIRC)
End of enumeration elements list.
Clock Source Select Control Register 2
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM0SEL : PWM0 Clock Source Selection
The peripheral clock source of PWM0 is defined by PWM0SEL.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from PLL
#1 : 1
Clock source from PCLK0
End of enumeration elements list.
SPI0SEL : SPI0 Clock Source Selection
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from PCLK0
#11 : 3
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
SPI2SEL : SPI2 Clock Source Selection
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from PLL
#010 : 2
Clock source from PCLK0
#011 : 3
Clock source from internal high speed RC oscillator (HIRC)
#100 : 4
Clock source from Clock Doubler output (XCLK)
#101 : 5
Clock source from external pin MCLKI
End of enumeration elements list.
DMICSEL : DMIC Clock Source Selection
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from PLL
#010 : 2
Clock source from PCLK1
#011 : 3
Clock source from internal high speed RC oscillator (HIRC)
#100 : 4
Clock source from Clock Doubler output (XCLK)
#101 : 5
Clock source from external pin MCLKI
End of enumeration elements list.
DPWMSEL : DPWM Clock Source Selection
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from PLL
#010 : 2
Clock source from PCLK0
#011 : 3
Clock source from internal high speed RC oscillator (HIRC)
#100 : 4
Clock source from Clock Doubler output (XCLK)
#101 : 5
Clock source from external pin MCLKI
End of enumeration elements list.
Clock Source Select Control Register 3
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTCSEL : RTC Clock Source Selection
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from external low speed crystal oscillator (LXT)
#1 : 1
Clock source from internal low speed RC oscillator (LIRC)
End of enumeration elements list.
XCLKSEL : Clcok Doubler Source Selection
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from MCLK input (MCLKI)
#01 : 1
Clock source from BCLK of I2S0 (I2S0_BCLK)
#10 : 2
Clock source from BCLK of I2S1 (I2S1_BCLK)
#11 : 3
Clock source from BCLK of SPI2/I2S (SPI2_CLK)
End of enumeration elements list.
I2S0SEL : I2S0 Clock Source Selection
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from PLL
#010 : 2
Clock source from PCLK0
#011 : 3
Clock source from internal high speed RC oscillator (HIRC)
#100 : 4
Clock source from Clock Doubler output (XCLK)
#101 : 5
Clock source from external pin MCLKI
End of enumeration elements list.
I2S1SEL : I2S1 Clock Source Selection
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from PLL
#010 : 2
Clock source from PCLK1
#011 : 3
Clock source from internal high speed RC oscillator (HIRC)
#100 : 4
Clock source from Clock Doubler output (XCLK)
#101 : 5
Clock source from external pin MCLKI
End of enumeration elements list.
Clock Divider Number Register 0
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLKDIV : HCLK Clock Divide Number From HCLK Clock Source
bits : 0 - 3 (4 bit)
access : read-write
USBDIV : USB Clock Divide Number From PLL Clock
bits : 4 - 7 (4 bit)
access : read-write
UART0DIV : UART0 Clock Divide Number From UART0 Clock Source
bits : 8 - 11 (4 bit)
access : read-write
UART1DIV : UART1 Clock Divide Number From UART1 Clock Source
bits : 12 - 15 (4 bit)
access : read-write
DSPCLKDIV : DSPCLK Clock Divide Number From DSPCLK Clock Source
bits : 24 - 27 (4 bit)
access : read-write
Clock Source Select Control Register 4
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBSEL : USB Clock Source Selection
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from internal high speed RC oscillator (HIRC)
#1 : 1
Clock source from PLL
End of enumeration elements list.
APB Clock Divider Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APB0DIV : APB0 Clock Divider
APB0 clock can be divided from HCLK
Note: When the clock frequency of HCLK greater than 75 MHz, the value of APB1DIV (CLK_PCLKDIV[6:4]) and APB0DIV(CLK_PCLKDIV[2:0]) must be greater than 0.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
PCLK0 = HCLK
#001 : 1
PCLK0 = 1/2 HCLK
#010 : 2
PCLK0 = 1/4 HCLK
#011 : 3
PCLK0 = 1/8 HCLK
#100 : 4
PCLK0 = 1/16 HCLK
End of enumeration elements list.
APB1DIV : APB1 Clock Divider
APB1 clock can be divided from HCLK
Note: When the clock frequency of HCLK greater than 75 MHz, the value of APB1DIV (CLK_PCLKDIV[6:4]) and APB0DIV(CLK_PCLKDIV[2:0]) must be greater than 0.
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 0
PCLK1 = HCLK
#001 : 1
PCLK1 = 1/2 HCLK
#010 : 2
PCLK1 = 1/4 HCLK
#011 : 3
PCLK1 = 1/8 HCLK
#100 : 4
PCLK1 = 1/16 HCLK
End of enumeration elements list.
AHB Devices Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMACKEN : PDMA Controller Clock Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA peripheral clock Disabled
#1 : 1
PDMA peripheral clock Enabled
End of enumeration elements list.
ISPCKEN : Flash ISP Controller Clock Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash ISP peripheral clock Disabled
#1 : 1
Flash ISP peripheral clock Enabled
End of enumeration elements list.
DSPCKEN : DSP Clock Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
DSP clock Disabled
#1 : 1
DSP clock Enabled
End of enumeration elements list.
CRCCKEN : CRC Generator Controller Clock Enable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
CRC peripheral clock Disabled
#1 : 1
CRC peripheral clock Enabled
End of enumeration elements list.
CRPTCKEN : Cryptographic Accelerator Clock Enable Bit
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Cryptographic controller clock Disabled
#1 : 1
Cryptographic controller clock Enabled
End of enumeration elements list.
SPIMCKEN : SPIM Controller Clock Enable Bit
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPIM controller clock Disabled
#1 : 1
SPIM controller clock Enabled
End of enumeration elements list.
OMCIDLE : OTP Memory Controller Clock Enable Bit in IDLE Mode
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
OMC clock Disabled when chip is under IDLE mode
#1 : 1
OMC clock Enabled when chip is under IDLE mode
End of enumeration elements list.
PLL Control Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FBDIV : PLL Feedback Divider Control (Write Protected)
Refer to the formulas below the table.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 8 (9 bit)
access : read-write
INDIV : PLL Input Divider Control (Write Protected)
Refer to the formulas below the table.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 9 - 13 (5 bit)
access : read-write
OUTDIV : PLL Output Divider Control (Write Protected)
Refer to the formulas below the table.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 14 - 15 (2 bit)
access : read-write
PD : Power-down Mode (Write Protected)
If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL is in normal mode
#1 : 1
PLL is in Power-down mode (default)
End of enumeration elements list.
BP : PLL Bypass Control (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL is in normal mode (default)
#1 : 1
PLL clock output is same as PLL input clock FIN
End of enumeration elements list.
OE : PLL OE (FOUT Enable) Pin Control (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL FOUT Enabled
#1 : 1
PLL FOUT is fixed low
End of enumeration elements list.
PLLSRC : PLL Source Clock Selection (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
#00 : 0
PLL source clock from external high-speed crystal oscillator (HXT)
#01 : 1
PLL source clock from internal high-speed oscillator (HIRC)
#10 : 2
PLL source clock from clock doubler output (XCLK)
#11 : 3
Reserved. Do not use
End of enumeration elements list.
LKSEL : PLL Lock Selection (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Refer to STBSEL
#1 : 1
Refer to PLL macro lock signal
End of enumeration elements list.
STBSEL : PLL Stable Counter Selection (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12 MHz)
#1 : 1
PLL stable time is 44000 PLL source clock (suitable for source clock is larger than 12 MHz)
End of enumeration elements list.
Clock Status Monitor Register
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HXTSTB : HXT Clock Source Stable Flag (Read Only)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
External high speed crystal oscillator (HXT) clock is not stable or disabled
#1 : 1
External high speed crystal oscillator (HXT) clock is stable and enabled
End of enumeration elements list.
LXTSTB : LXT Clock Source Stable Flag (Read Only)
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
External low speed crystal oscillator (LXT) clock is not stable or disabled
#1 : 1
External low speed crystal oscillator (LXT) clock is stabled and enabled
End of enumeration elements list.
PLLSTB : Internal PLL Clock Source Stable Flag (Read Only)
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal PLL clock is not stable or disabled
#1 : 1
Internal PLL clock is stable and enabled
End of enumeration elements list.
LIRCSTB : LIRC Clock Source Stable Flag (Read Only)
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal low speed RC oscillator (LIRC) clock is not stable or disabled
#1 : 1
Internal low speed RC oscillator (LIRC) clock is stable and enabled
End of enumeration elements list.
HIRCSTB : HIRC Clock Source Stable Flag (Read Only)
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal high speed RC oscillator (HIRC) clock is not stable or disabled
#1 : 1
Internal high speed RC oscillator (HIRC) clock is stable and enabled
End of enumeration elements list.
XCLKSTB : XCLK Clock Source Stable Flag (Read Only)
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Clcok doubler (XCLK) clock is not stable or disabled
#1 : 1
Clcok doubler (XCLK) clock is stable and enabled
End of enumeration elements list.
CLKSFAIL : Clock Switching Fail Flag (Read Only)
This bit is updated when software switches system clock source (CLK_CLKSEL0[2:0]). If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Clock switching success
#1 : 1
Clock switching failure
End of enumeration elements list.
Clock Output Control Register
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQSEL : Clock Output Frequency Selection
The formula of output frequency is
Fin is the input clock frequency.
Fout is the frequency of divider output clock.
N is the 4-bit value of FREQSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write
CLKOEN : Clock Output Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Output function Disabled
#1 : 1
Clock Output function Enabled
End of enumeration elements list.
DIV1EN : Clock Output Divide One Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Output will output clock with source frequency divided by FREQSEL
#1 : 1
Clock Output will output clock with source frequency
End of enumeration elements list.
CLK1HZEN : Clock Output 1Hz Enable Bit
Note: RTC IP need to be enabled.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
1 Hz clock output for RTC frequency compensation Disabled
#1 : 1
1 Hz clock output for RTC frequency compensation Enabled
End of enumeration elements list.
Clock Doubler Output Control Register
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XCLKMUL : Clock doubler Output Frequency Multiplication
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Output frequency multiply by 1 (Bypass)
#01 : 1
Output frequency multiply by 2
#10 : 2
Output frequency multiply by 4
#11 : 3
Output frequency multiply by 8
End of enumeration elements list.
XCLKEN : XCLK Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock doubler (XCLK) Disabled
#1 : 1
Clock doubler (XCLK) Enabled
End of enumeration elements list.
Clock Fail Detector Control Register
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTFDEN : HXT Clock Fail Detector Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
External high speed crystal oscillator (HXT) clock fail detector Disabled
#1 : 1
External high speed crystal oscillator (HXT) clock fail detector Enabled
End of enumeration elements list.
HXTFIEN : HXT Clock Fail Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
External high speed crystal oscillator (HXT) clock fail interrupt Disabled
#1 : 1
External high speed crystal oscillator (HXT) clock fail interrupt Enabled
End of enumeration elements list.
XCLKFDEN : XCLK Clock Fail Detector Enable Bit
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock doubler clock (XCLK) fail detector Disabled
#1 : 1
Clock doubler clock (XCLK) fail detector Enabled
End of enumeration elements list.
XCLKFIEN : XCLK Clock Fail Interrupt Enable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock doubler clock (XCLK) fail interrupt Disabled
#1 : 1
Clock doubler clock (XCLK) fail interrupt Enabled
End of enumeration elements list.
LXTFDEN : LXT Clock Fail Detector Enable Bit
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
External low speed crystal oscillator (LXT) clock fail detector Disabled
#1 : 1
External low speed crystal oscillator (LXT) clock fail detector Enabled
End of enumeration elements list.
LXTFIEN : LXT Clock Fail Interrupt Enable Bit
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
External low speed crystal oscillator (LXT) clock fail interrupt Disabled
#1 : 1
External low speed crystal oscillator (LXT) clock fail interrupt Enabled
End of enumeration elements list.
HXTFQDEN : HXT Clock Frequency Monitor Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
External high speed crystal oscillator (HXT) clock frequency Range Detector Disabled
#1 : 1
External high speed crystal oscillator (HXT) clock frequency Range Detector Enabled
End of enumeration elements list.
HXTFQIEN : HXT Clock Frequency Range Detector Interrupt Enable Bit
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
External high speed crystal oscillator (HXT) clock frequency Range Detector fail interrupt Disabled
#1 : 1
External high speed crystal oscillator (HXT) clock frequency Range Detector fail interrupt Enabled
End of enumeration elements list.
Clock Fail Detector Status Register
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTFIF : HXT Clock Fail Interrupt Flag
Note: Write 1 to clear the bit to 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
External high speed crystal oscillator (HXT) clock is normal
#1 : 1
External high speed crystal oscillator (HXT) clock stops
End of enumeration elements list.
LXTFIF : LXT Clock Fail Interrupt Flag
Note: Write 1 to clear the bit to 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
External low speed crystal oscillator (LXT) clock is normal
#1 : 1
External low speed crystal oscillator (LXT) stops
End of enumeration elements list.
XCLKFIF : XCLK Clock Fail Interrupt Flag
Note: Write 1 to clear the bit to 0.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock doubler clock (XCLK) clock is normal
#1 : 1
Clock doubler clock (XCLK) stops
End of enumeration elements list.
HXTFQIF : HXT Clock Frequency Range Detector Interrupt Flag
Note: Write 1 to clear the bit to 0.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
External high speed crystal oscillator (HXT) clock frequency is normal
#1 : 1
External high speed crystal oscillator (HXT) clock frequency is abnormal
End of enumeration elements list.
Clock Frequency Range Detector Upper Boundary Register
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPERBD : HXT Clock Frequency Range Detector Upper Boundary Value
The bits define the maximum value of frequency range detector window.
The HXT detected frequency value is 512 * (the frequency of HXT / the frequency of HIRC)
If the HXT detected frequency value higher than this maximum frequency value (UPERBD), the HXT Clock Frequency Range Detector Interrupt Flag (HXTFQIF(CLK_CLKDSTS[8])) will set to 1.
bits : 0 - 9 (10 bit)
access : read-write
Clock Frequency Range Detector Lower Boundary Register
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOWERBD : HXT Clock Frequency Range Detector Lower Boundary Value
The bits define the minimum value of frequency range detector window.
The HXT detected frequency value is 512 * (the frequency of HXT / the frequency of HIRC)
If the HXT detected frequency value lower than this minimum frequency value (LOWERBD), the HXT Clock Frequency Range Detector Interrupt Flag (HXTFQIF(CLK_CLKDSTS[8])) will set to 1.
bits : 0 - 9 (10 bit)
access : read-write
APB Devices Clock Enable Control Register 0
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTCKEN : Watchdog Timer Clock Enable Bit (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Watchdog timer clock Disabled
#1 : 1
Watchdog timer clock Enabled
End of enumeration elements list.
RTCCKEN : Real-time-clock APB Interface Clock Enable Bit
This bit is used to control the RTC APB clock only. The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8]). It can be selected to 32.768 kHz external low speed crystal or 10 kHz internal low speed RC oscillator (LIRC).
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC clock Disabled
#1 : 1
RTC clock Enabled
End of enumeration elements list.
TMR0CKEN : Timer0 Clock Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer0 clock Disabled
#1 : 1
Timer0 clock Enabled
End of enumeration elements list.
TMR1CKEN : Timer1 Clock Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer1 clock Disabled
#1 : 1
Timer1 clock Enabled
End of enumeration elements list.
TMR2CKEN : Timer2 Clock Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer2 clock Disabled
#1 : 1
Timer2 clock Enabled
End of enumeration elements list.
TMR3CKEN : Timer3 Clock Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer3 clock Disabled
#1 : 1
Timer3 clock Enabled
End of enumeration elements list.
CLKOCKEN : CLKO Clock Enable Bit
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
CLKO clock Disabled
#1 : 1
CLKO clock Enabled
End of enumeration elements list.
I2C0CKEN : I2C0 Clock Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C0 clock Disabled
#1 : 1
I2C0 clock Enabled
End of enumeration elements list.
I2C1CKEN : I2C1 Clock Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C1 clock Disabled
#1 : 1
I2C1 clock Enabled
End of enumeration elements list.
SPI0CKEN : SPI0 Clock Enable Bit
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI0 clock Disabled
#1 : 1
SPI0 clock Enabled
End of enumeration elements list.
SPI2CKEN : SPI2 Clock Enable Bit
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI2 clock Disabled
#1 : 1
SPI2 clock Enabled
End of enumeration elements list.
DMICCKEN : DMIC Clock Enable Bit
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMIC clock Disabled
#1 : 1
DMIC clock Enabled
End of enumeration elements list.
UART0CKEN : UART0 Clock Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0 clock Disabled
#1 : 1
UART0 clock Enabled
End of enumeration elements list.
UART1CKEN : UART1 Clock Enable Bit
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART1 clock Disabled
#1 : 1
UART1 clock Enabled
End of enumeration elements list.
USBDCKEN : USB Device Clock Enable Bit
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB Device clock Disabled
#1 : 1
USB Device clock Enabled
End of enumeration elements list.
I2S0CKEN : I2S0 Clock Enable Bit
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2S0 Clock Disabled
#1 : 1
I2S0 Clock Enabled
End of enumeration elements list.
I2S1CKEN : I2S1 Clock Enable Bit
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2S1 Clock Disabled
#1 : 1
I2S1 Clock Enabled
End of enumeration elements list.
Power Manager Control Register
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMSEL : Power-down Mode Selection (Write Protected)
This is a protected register. Please refer to open lock sequence to program it.
These bits control chip power-down mode grade selection when CPU execute WFI/WFE instruction.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Power-down mode is selected. (PD)
#001 : 1
Low leakage Power-down mode is selected (LLPD)
#010 : 2
Reserved. Do not use
#011 : 3
Reserved. Do not use
#100 : 4
Standby Power-down mode 0 is selected (SPD0) (SRAM retention)
#101 : 5
Standby Power-down mode 1 is selected (SPD1)
#110 : 6
Deep Power-down mode is selected (DPD)
#111 : 7
Reserved. Do not use
End of enumeration elements list.
WKTMREN : Wake-up Timer Enable (Write Protected)
This is a protected register. Please refer to open lock sequence to program it.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Wake-up timer disable at DPD/SPD mode
#1 : 1
Wake-up timer enabled at DPD/SPD mode
End of enumeration elements list.
WKTMRIS : Wake-up Timer Time-out Interval Select (Write Protected)
This is a protected register. Please refer to open lock sequence to program it.
These bits control wake-up timer time-out interval when chip at DPD/SPD mode.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
#000 : 0
Time-out interval is 128 LIRC clocks (About 12.8 ms)
#001 : 1
Time-out interval is 256 LIRC clocks (About 25.6 ms)
#010 : 2
Time-out interval is 512 LIRC clocks (About 51.2 ms)
#011 : 3
Time-out interval is 1024 LIRC clocks (About 102.4ms)
#100 : 4
Time-out interval is 4096 LIRC clocks (About 409.6ms)
#101 : 5
Time-out interval is 8192 LIRC clocks (About 819.2ms)
#110 : 6
Time-out interval is 16384 LIRC clocks (About 1638.4ms)
#111 : 7
Time-out interval is 65536 LIRC clocks (About 6553.6ms)
End of enumeration elements list.
WKPINEN : Wake-up Pin Enable (Write Protected)
This is a protected register. Please refer to open lock sequence to program it.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Wake-up pin disable at Deep Power-down mode
#01 : 1
Wake-up pin rising edge enabled at Deep Power-down mode
#10 : 2
Wake-up pin falling edge enabled at Deep Power-down mode
#11 : 3
Wake-up pin both edge enabled at Deep Power-down mode
End of enumeration elements list.
VADWKEN : VAD Standby Power-down Mode Wake-up Enable (Write Protected)
This is a protected register. Please refer to open lock sequence to program it.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
VAD wake-up disable at Standby Power-down mode
#1 : 1
VAD wake-up enabled at Standby Power-down mode
End of enumeration elements list.
RTCWKEN : RTC Wake-up Enable Bit (Write Protected)
This is a protected register. Please refer to open lock sequence to program it.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC wake-up disable at Standby Power-down mode
#1 : 1
RTC wake-up enabled at Standby Power-down mode
End of enumeration elements list.
HIRCPDEN : HIRC Enable Control in Power-down Mode (Write Protected)
This is a protected register. Please refer to open lock sequence to program it.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
HIRC disable at Power-down mode
#1 : 1
HIRC enabled at Power-down mode except DPD mode
End of enumeration elements list.
Power Manager Status Register
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORWK : Power-on-reset Wake-up Flag (Read Only)
This flag indicates that wakeup of device was requested with a power-on reset. This flag is cleared when DPD mode is entered.
bits : 0 - 0 (1 bit)
access : read-only
PINWK : Pin Wake-up Flag (Read Only)
This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PA.15). This flag is cleared when DPD mode is entered.
bits : 1 - 1 (1 bit)
access : read-only
DPD_TMRWK : DPD Mode Wake-up Timer Wake-up Flag (Read Only)
This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by wakeup timer time-out. This flag is cleared when DPD mode is entered.
bits : 2 - 2 (1 bit)
access : read-only
LVRWK : LVR Wake-up Flag (Read Only)
This flag indicates that wakeup of device from Standby Power-down mode was requested with a LVR happened. This flag is cleared when SPD mode is entered.
bits : 3 - 3 (1 bit)
access : read-only
BODWK : BOD Wake-up Flag (Read Only)
This flag indicates that wakeup of device from Standby Power-down mode was requested with a BOD happened. This flag is cleared when SPD mode is entered.
bits : 4 - 4 (1 bit)
access : read-only
RTCWK : RTC Wake-up Flag (Read Only)
This flag indicates that wakeup of device from Standby Power-down mode was requested with a RTC alarm or tick time happened. This flag is cleared when SPD mode is entered.
bits : 5 - 5 (1 bit)
access : read-only
SPD_TMRWK : SPD Mode Wake-up Timer Wake-up Flag (Read Only)
This flag indicates that wake-up of chip was requested by wakeup timer time-out. This flag is cleared when SPD mode is entered.
bits : 6 - 6 (1 bit)
access : read-only
DPD_RSTWK : DPD Mode Reset Wake-up Flag (Read Only)
This flag indicates that wakeup of device was requested with a reset. This flag is cleared when DPD mode is entered.
bits : 7 - 7 (1 bit)
access : read-only
GPAWK : GPA Wake-up Flag (Read Only)
This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPA group pins. This flag is cleared when SPD mode is entered.
bits : 8 - 8 (1 bit)
access : read-only
GPBWK : GPB Wake-up Flag (Read Only)
This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPB group pins. This flag is cleared when SPD mode is entered.
bits : 9 - 9 (1 bit)
access : read-only
GPCWK : GPC Wake-up Flag (Read Only)
This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPC group pins. This flag is cleared when SPD mode is entered.
bits : 10 - 10 (1 bit)
access : read-only
GPDWK : GPD Wake-up Flag (Read Only)
This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPD group pins. This flag is cleared when SPD mode is entered.
bits : 11 - 11 (1 bit)
access : read-only
VADWK : VAD Wake-up Flag (Read Only)
This flag indicates that wakeup of device from Standby Power-down mode was requested with a VAD happened. This flag is cleared when SPD mode is entered.
bits : 13 - 13 (1 bit)
access : read-only
CLRWK : Clear Wake-up Flag
Note: This bit is auto cleared by hardware.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No clear
#1 : 1
Clear all wake-up flag
End of enumeration elements list.
Chip LDO Control Register
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVEN : LDO over Drive Enable Bit
Note1: CPU can run up to 200 MHz only when OVEN set to 1.
Note2: If OVEN and LPEN are set to 1 at the same time, LDO over drive will be enabled.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
LDO keep standard voltage operating
#1 : 1
LDO over drive voltage operating
End of enumeration elements list.
Standby Power-down Wake-up De-bounce Control Register
address_offset : 0x9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWKDBCLKSEL : Standby Power-down Wake-up De-bounce Sampling Cycle Selection
Note: De-bounce counter clock source is the internal low speed RC oscillator (LIRC).
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
Sample wake-up input once per 1 clocks
#0001 : 1
Sample wake-up input once per 2 clocks
#0010 : 2
Sample wake-up input once per 4 clocks
#0011 : 3
Sample wake-up input once per 8 clocks
#0100 : 4
Sample wake-up input once per 16 clocks
#0101 : 5
Sample wake-up input once per 32 clocks
#0110 : 6
Sample wake-up input once per 64 clocks
#0111 : 7
Sample wake-up input once per 128 clocks
#1000 : 8
Sample wake-up input once per 256 clocks
#1001 : 9
Sample wake-up input once per 2*256 clocks
#1010 : 10
Sample wake-up input once per 4*256 clocks
#1011 : 11
Sample wake-up input once per 8*256 clocks
#1100 : 12
Sample wake-up input once per 16*256 clocks
#1101 : 13
Sample wake-up input once per 32*256 clocks
#1110 : 14
Sample wake-up input once per 64*256 clocks
#1111 : 15
Sample wake-up input once per 128*256 clocks.
End of enumeration elements list.
GPA Standby Power-down Wakeup Control Register
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKEN : Standby Power-down Pin Wake-up Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PA group pin wake-up function disabled
#1 : 1
PA group pin wake-up function enabled
End of enumeration elements list.
PRWKEN : Pin Rising Edge Wake-up Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PA group pin rising edge wake-up function disabled
#1 : 1
PA group pin rising edge wake-up function enabled
End of enumeration elements list.
PFWKEN : Pin Falling Edge Wake-up Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PA group pin falling edge wake-up function disabled
#1 : 1
PA group pin falling edge wake-up function enabled
End of enumeration elements list.
WKPSEL : PA Standby Power-down Wake-up Pin Select
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PA.0 wake-up function enabled
#0001 : 1
PA.1 wake-up function enabled
#0010 : 2
PA.2 wake-up function enabled
#0011 : 3
PA.3 wake-up function enabled
#0100 : 4
PA.4 wake-up function enabled
#0101 : 5
PA.5 wake-up function enabled
#0110 : 6
PA.6 wake-up function enabled
#0111 : 7
PA.7 wake-up function enabled
#1000 : 8
PA.8 wake-up function enabled
#1001 : 9
PA.9 wake-up function enabled
#1010 : 10
PA.10 wake-up function enabled
#1011 : 11
PA.11 wake-up function enabled
#1100 : 12
PA.12 wake-up function enabled
#1101 : 13
PA.13 wake-up function enabled
#1110 : 14
PA.14 wake-up function enabled
#1111 : 15
PA.15 wake-up function enabled
End of enumeration elements list.
DBEN : PA Input Signal De-bounce Enable Bit
The DBEN bit is used to enable the de-bounce function for each corresponding I/O. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. The de-bounce clock source is the internal low speed RC oscillator.
The de-bounce function is valid only for edge triggered.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Standby power-down wake-up pin De-bounce function disable
#1 : 1
Standby power-down wake-up pin De-bounce function enable
End of enumeration elements list.
GPB Standby Power-down Wakeup Control Register
address_offset : 0xA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKEN : Standby Power-down Pin Wake-up Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PB group pin wake-up function disabled
#1 : 1
PB group pin wake-up function enabled
End of enumeration elements list.
PRWKEN : Pin Rising Edge Wake-up Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PB group pin rising edge wake-up function disabled
#1 : 1
PB group pin rising edge wake-up function enabled
End of enumeration elements list.
PFWKEN : Pin Falling Edge Wake-up Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PB group pin falling edge wake-up function disabled
#1 : 1
PB group pin falling edge wake-up function enabled
End of enumeration elements list.
WKPSEL : PB Standby Power-down Wake-up Pin Select
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PB.0 wake-up function enabled
#0001 : 1
PB.1 wake-up function enabled
#0010 : 2
PB.2 wake-up function enabled
#0011 : 3
PB.3 wake-up function enabled
#0100 : 4
PB.4 wake-up function enabled
#0101 : 5
PB.5 wake-up function enabled
#0110 : 6
PB.6 wake-up function enabled
#0111 : 7
PB.7 wake-up function enabled
#1000 : 8
PB.8 wake-up function enabled
#1010 : 10
PB.10 wake-up function enabled
#1011 : 11
PB.11 wake-up function enabled
#1100 : 12
PB.12 wake-up function enabled
#1101 : 13
PB.13 wake-up function enabled
#1110 : 14
PB.14 wake-up function enabled
#1111 : 15
PB.15 wake-up function enabled
End of enumeration elements list.
DBEN : PB Input Signal De-bounce Enable Bit
The DBEN bit is used to enable the de-bounce function for each corresponding I/O. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. The de-bounce clock source is the internal low speed RC oscillator.
The de-bounce function is valid only for edge triggered.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Standby power-down wake-up pin De-bounce function disable
#1 : 1
Standby power-down wake-up pin De-bounce function enable
End of enumeration elements list.
GPC Standby Power-down Wakeup Control Register
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKEN : Standby Power-down Pin Wake-up Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PC group pin wake-up function disabled
#1 : 1
PC group pin wake-up function enabled
End of enumeration elements list.
PRWKEN : Pin Rising Edge Wake-up Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PC group pin rising edge wake-up function disabled
#1 : 1
PC group pin rising edge wake-up function enabled
End of enumeration elements list.
PFWKEN : Pin Falling Edge Wake-up Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PC group pin falling edge wake-up function disabled
#1 : 1
PC group pin falling edge wake-up function enabled
End of enumeration elements list.
WKPSEL : PC Standby Power-down Wake-up Pin Select
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PC.0 wake-up function enabled
#0001 : 1
PC.1 wake-up function enabled
#0010 : 2
PC.2 wake-up function enabled
#0011 : 3
PC.3 wake-up function enabled
#0100 : 4
PC.4 wake-up function enabled
#0101 : 5
PC.5 wake-up function enabled
#0110 : 6
PC.6 wake-up function enabled
#0111 : 7
PC.7 wake-up function enabled
#1000 : 8
PC.8 wake-up function enabled
#1001 : 9
PC.9 wake-up function enabled
#1010 : 10
PC.10 wake-up function enabled
#1011 : 11
PC.11 wake-up function enabled
#1100 : 12
PC.12 wake-up function enabled
#1101 : 13
PC.13 wake-up function enabled
#1110 : 14
PC.14 wake-up function enabled
#1111 : 15
PC.15 wake-up function enabled
End of enumeration elements list.
DBEN : PC Input Signal De-bounce Enable Bit
The DBEN bit is used to enable the de-bounce function for each corresponding I/O. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. The de-bounce clock source is the internal low speed RC oscillator.
The de-bounce function is valid only for edge triggered.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Standby power-down wake-up pin De-bounce function disable
#1 : 1
Standby power-down wake-up pin De-bounce function enable
End of enumeration elements list.
GPD Standby Power-down Wakeup Control Register
address_offset : 0xAC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKEN : Standby Power-down Pin Wake-up Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PD group pin wake-up function disabled
#1 : 1
PD group pin wake-up function enabled
End of enumeration elements list.
PRWKEN : Pin Rising Edge Wake-up Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PD group pin rising edge wake-up function disabled
#1 : 1
PD group pin rising edge wake-up function enabled
End of enumeration elements list.
PFWKEN : Pin Falling Edge Wake-up Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PD group pin falling edge wake-up function disabled
#1 : 1
PD group pin falling edge wake-up function enabled
End of enumeration elements list.
WKPSEL : PD Standby Power-down Wake-up Pin Select
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PD.0 wake-up function enabled
#0001 : 1
PD.1 wake-up function enabled
#0010 : 2
PD.2 wake-up function enabled
#0011 : 3
PD.3 wake-up function enabled
#0100 : 4
PD.4 wake-up function enabled
#0101 : 5
PD.5 wake-up function enabled
#0110 : 6
PD.6 wake-up function enabled
#0111 : 7
PD.7 wake-up function enabled
#1000 : 8
PD.8 wake-up function enabled
#1001 : 9
PD.9 wake-up function enabled
#1010 : 10
PD.10 wake-up function enabled
#1011 : 11
PD.11 wake-up function enabled
#1100 : 12
PD.12 wake-up function enabled
#1101 : 13
PD.13 wake-up function enabled
#1110 : 14
PD.14 wake-up function enabled
#1111 : 15
PD.15 wake-up function enabled
End of enumeration elements list.
DBEN : PD Input Signal De-bounce Enable Bit
The DBEN bit is used to enable the de-bounce function for each corresponding I/O. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. The de-bounce clock source is the internal low speed RC oscillator.
The de-bounce function is valid only for edge triggered.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Standby power-down wake-up pin De-bounce function disable
#1 : 1
Standby power-down wake-up pin De-bounce function enable
End of enumeration elements list.
GPIO Standby Power-down Control Register
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOHR : GPIO Hold Release
When GPIO enter standby power-down mode, all I/O status are hold to keep normal operating status. After chip was waked up from standby power-down mode, the I/O are still keep hold status until user set this bit to release I/O hold status.
This bit is auto cleared by hardware.
bits : 0 - 0 (1 bit)
access : read-write
APB Devices Clock Enable Control Register 1
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPWMCKEN : DPWM Clock Enable Bit
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
DPWM clock Disabled
#1 : 1
DPWM clock Enabled
End of enumeration elements list.
PWM0CKEN : PWM0 Clock Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0 clock Disabled
#1 : 1
PWM0 clock Enabled
End of enumeration elements list.
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