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OMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

Registers

OMC_ISPCTL (ISPCTL)

OMC_ISPTRG (ISPTRG)

OMC_ISPADDR (ISPADDR)

OMC_ISPSTS (ISPSTS)

OMC_ISPDAT (ISPDAT)

OMC_ISPCMD (ISPCMD)


OMC_ISPCTL (ISPCTL)

ISP Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OMC_ISPCTL OMC_ISPCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISPEN ISPFF

ISPEN : ISP Enable Bit (Write Protected) ISP function enable bit. Set this bit to enable ISP function.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

ISP function Disabled

#1 : 1

ISP function Enabled

End of enumeration elements list.

ISPFF : ISP Fail Flag (Write Protected) This bit is set by hardware when a triggered ISP meets any of the following conditions: (1) Destination address is illegal, such as over an available range. (2) Invalid ISP commands. (3) Program command at the address which is already programmed. Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: This bit needs to be cleared by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-write


OMC_ISPTRG (ISPTRG)

ISP Trigger Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OMC_ISPTRG OMC_ISPTRG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISPGO

ISPGO : ISP Start Trigger (Write Protected) Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

ISP operation is finished

#1 : 1

ISP is progressed

End of enumeration elements list.


OMC_ISPADDR (ISPADDR)

ISP Address Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OMC_ISPADDR OMC_ISPADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISPADDR

ISPADDR : ISP Address ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. For CRC32 Checksum Calculation command, this field is the OTP starting address for checksum calculation, 32 bytes alignment is necessary for CRC32 checksum calculation. For 32-bit Program, ISP address needs word alignment (4-byte).
bits : 0 - 31 (32 bit)
access : read-write


OMC_ISPSTS (ISPSTS)

ISP Status Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OMC_ISPSTS OMC_ISPSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISPBUSY ISPFF VECMAP

ISPBUSY : ISP Busy Flag (Read Only) This bit is the mirror of ISPGO (OMC_ISPTRG[0]).
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

ISP operation is finished

#1 : 1

ISP is progressed

End of enumeration elements list.

ISPFF : ISP Fail Flag (Read Only) This bit is the mirror of ISPFF(OMC_ISPCTL[6]), it needs to be cleared by writing 1 to OMC_ISPCTL[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions: (1) Destination address is illegal, such as over an available range. (2) Invalid ISP commands. (3) Program command at the address which is already programmed.
bits : 6 - 6 (1 bit)
access : read-only

VECMAP : Vector Page Mapping Address (Read Only) The current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[20:0], 9'h000} ~ {VECMAP[20:0], 9'h1FF}
bits : 9 - 29 (21 bit)
access : read-only


OMC_ISPDAT (ISPDAT)

ISP Data Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OMC_ISPDAT OMC_ISPDAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISPDAT

ISPDAT : ISP Data Write data to this register before ISP program operation. Read data from this register after ISP read operation.
bits : 0 - 31 (32 bit)
access : read-write


OMC_ISPCMD (ISPCMD)

ISP Command Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OMC_ISPCMD OMC_ISPCMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD

CMD : ISP Command ISP command table is shown below: The other commands are invalid. Note: The supply voltage of VDD must be higher than 2.5V for OTP programming.
bits : 0 - 6 (7 bit)
access : read-write

Enumeration:

0x00 : 0

32-Bit Read

0x04 : 4

Read Unique ID

0x0b : 11

Read Company ID

0x0c : 12

Read Device ID

0x0d : 13

Read Checksum

0x21 : 33

32-bit Program

0x2d : 45

Run Checksum Calculation

0x2e : 46

Vector Remap

End of enumeration elements list.



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