PDMA_DSCT0_CTL (DSCT0_CTL)

PDMA_DSCT1_CTL (DSCT1_CTL)

PDMA_CURSCAT0 (CURSCAT0)

PDMA_CURSCAT1 (CURSCAT1)

PDMA_CURSCAT2 (CURSCAT2)

PDMA_CURSCAT3 (CURSCAT3)

PDMA_CURSCAT4 (CURSCAT4)

PDMA_CURSCAT5 (CURSCAT5)

PDMA_CURSCAT6 (CURSCAT6)

PDMA_CURSCAT7 (CURSCAT7)

PDMA_CURSCAT8 (CURSCAT8)

PDMA_CURSCAT9 (CURSCAT9)

PDMA_CURSCAT10 (CURSCAT10)

PDMA_CURSCAT11 (CURSCAT11)

PDMA_CURSCAT12 (CURSCAT12)

PDMA_CURSCAT13 (CURSCAT13)

PDMA_CURSCAT14 (CURSCAT14)

PDMA_CURSCAT15 (CURSCAT15)

PDMA_DSCT1_SA (DSCT1_SA)

PDMA_DSCT1_DA (DSCT1_DA)

PDMA_DSCT1_NEXT (DSCT1_NEXT)

PDMA_DSCT2_CTL (DSCT2_CTL)

PDMA_DSCT2_SA (DSCT2_SA)

PDMA_DSCT2_DA (DSCT2_DA)

PDMA_DSCT2_NEXT (DSCT2_NEXT)

PDMA_DSCT3_CTL (DSCT3_CTL)

PDMA_DSCT3_SA (DSCT3_SA)

PDMA_DSCT3_DA (DSCT3_DA)

PDMA_DSCT3_NEXT (DSCT3_NEXT)

PDMA_DSCT0_SA (DSCT0_SA)

PDMA_DSCT4_CTL (DSCT4_CTL)

PDMA_CHCTL (CHCTL)

PDMA_STOP (STOP)

PDMA_SWREQ (SWREQ)

PDMA_TRGSTS (TRGSTS)

PDMA_PRISET (PRISET)

PDMA_PRICLR (PRICLR)

PDMA_INT0EN (INT0EN)

PDMA_INT0STS (INT0STS)

PDMA_ABTSTS (ABTSTS)

PDMA_TDSTS (TDSTS)

PDMA_ALIGN (ALIGN)

PDMA_TACTSTS (TACTSTS)

PDMA_TOUTPSC (TOUTPSC)

PDMA_TOUTEN (TOUTEN)

PDMA_TOUTI0EN (TOUTI0EN)

PDMA_DSCT4_SA (DSCT4_SA)

PDMA_TOC0_1 (TOC0_1)

PDMA_INT1EN (INT1EN)

PDMA_INT1STS (INT1STS)

PDMA_TOUTI1EN (TOUTI1EN)

PDMA_CHRST (CHRST)

PDMA_DSCT4_DA (DSCT4_DA)

PDMA_REQSEL0_3 (REQSEL0_3)

PDMA_REQSEL4_7 (REQSEL4_7)

PDMA_REQSEL8_11 (REQSEL8_11)

PDMA_REQSEL12_15 (REQSEL12_15)

PDMA_DSCT4_NEXT (DSCT4_NEXT)

PDMA_DSCT5_CTL (DSCT5_CTL)

PDMA_STCR0 (STCR0)

PDMA_ASOCR0 (ASOCR0)

PDMA_STCR1 (STCR1)

PDMA_ASOCR1 (ASOCR1)

PDMA_STCR2 (STCR2)

PDMA_ASOCR2 (ASOCR2)

PDMA_STCR3 (STCR3)

PDMA_ASOCR3 (ASOCR3)

PDMA_STCR4 (STCR4)

PDMA_ASOCR4 (ASOCR4)

PDMA_STCR5 (STCR5)

PDMA_ASOCR5 (ASOCR5)

PDMA_DSCT5_SA (DSCT5_SA)

PDMA_COMSCAT0 (COMSCAT0)

PDMA_COMSCAT1 (COMSCAT1)

PDMA_COMSCAT2 (COMSCAT2)

PDMA_COMSCAT3 (COMSCAT3)

PDMA_COMSCAT4 (COMSCAT4)

PDMA_COMSCAT5 (COMSCAT5)

PDMA_COMSCAT6 (COMSCAT6)

PDMA_COMSCAT7 (COMSCAT7)

PDMA_COMSCAT8 (COMSCAT8)

PDMA_COMSCAT9 (COMSCAT9)

PDMA_COMSCAT10 (COMSCAT10)

PDMA_COMSCAT11 (COMSCAT11)

PDMA_COMSCAT12 (COMSCAT12)

PDMA_COMSCAT13 (COMSCAT13)

PDMA_COMSCAT14 (COMSCAT14)

PDMA_COMSCAT15 (COMSCAT15)

PDMA_DSCT5_DA (DSCT5_DA)

PDMA_DSCT5_NEXT (DSCT5_NEXT)

PDMA_DSCT6_CTL (DSCT6_CTL)

PDMA_AICTL0 (AICTL0)

PDMA_RCNT0 (RCNT0)

PDMA_AICTL1 (AICTL1)

PDMA_RCNT1 (RCNT1)

PDMA_DSCT6_SA (DSCT6_SA)

PDMA_DSCT6_DA (DSCT6_DA)

PDMA_DSCT6_NEXT (DSCT6_NEXT)

PDMA_DSCT7_CTL (DSCT7_CTL)

PDMA_DSCT7_SA (DSCT7_SA)

PDMA_DSCT7_DA (DSCT7_DA)

PDMA_DSCT7_NEXT (DSCT7_NEXT)

PDMA_DSCT0_DA (DSCT0_DA)

PDMA_DSCT8_CTL (DSCT8_CTL)

PDMA_DSCT8_SA (DSCT8_SA)

PDMA_DSCT8_DA (DSCT8_DA)

PDMA_DSCT8_NEXT (DSCT8_NEXT)

PDMA_DSCT9_CTL (DSCT9_CTL)

PDMA_DSCT9_SA (DSCT9_SA)

PDMA_DSCT9_DA (DSCT9_DA)

PDMA_DSCT9_NEXT (DSCT9_NEXT)

PDMA_DSCT10_CTL (DSCT10_CTL)

PDMA_DSCT10_SA (DSCT10_SA)

PDMA_DSCT10_DA (DSCT10_DA)

PDMA_DSCT10_NEXT (DSCT10_NEXT)

PDMA_DSCT11_CTL (DSCT11_CTL)

PDMA_DSCT11_SA (DSCT11_SA)

PDMA_DSCT11_DA (DSCT11_DA)

PDMA_DSCT11_NEXT (DSCT11_NEXT)

PDMA_DSCT0_NEXT (DSCT0_NEXT)

PDMA_DSCT12_CTL (DSCT12_CTL)

PDMA_DSCT12_SA (DSCT12_SA)

PDMA_DSCT12_DA (DSCT12_DA)

PDMA_DSCT12_NEXT (DSCT12_NEXT)

PDMA_DSCT13_CTL (DSCT13_CTL)

PDMA_DSCT13_SA (DSCT13_SA)

PDMA_DSCT13_DA (DSCT13_DA)

PDMA_DSCT13_NEXT (DSCT13_NEXT)

PDMA_DSCT14_CTL (DSCT14_CTL)

PDMA_DSCT14_SA (DSCT14_SA)

PDMA_DSCT14_DA (DSCT14_DA)

PDMA_DSCT14_NEXT (DSCT14_NEXT)

PDMA_DSCT15_CTL (DSCT15_CTL)

PDMA_DSCT15_SA (DSCT15_SA)

PDMA_DSCT15_DA (DSCT15_DA)

PDMA_DSCT15_NEXT (DSCT15_NEXT)

OPMODE : PDMA Operation Mode Selection Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXTYPE : Transfer Type Note: When transfer to/from DRAM and IRAM, recommend that using 64-byte address alignment in burst mode to improve access efficiency.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BURSIZE : Burst Size This field is used for peripheral to determine the burst size or used for determine the re-arbitration size. Note: This field is only useful in burst transfer type.
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TBINTDIS : Table Interrupt Disable Bit This field can be used to decide whether to enable table interrupt or not. This bit is only used for scatter-gather mode. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SAINC : Source Address Increment This field is used to set the source address increment size.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DAINC : Destination Address Increment This field is used to set the destination address increment size.
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXWIDTH : Transfer Width Selection This field is used for transfer width. Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STRIDEEN : Stride Mode Enable Bit
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXCNT : Transfer Count The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1) The maximum transfer count is 16384, every transfer may be byte, half-word or word that is dependent on TXWIDTH field. Note: When PDMA finish each transfer data, this field will be decrease immediately.
bits : 16 - 31 (16 bit)
access : read-write

CURADDR : PDMA Current Description Address Register (Read Only) This field indicates a 32-bit current external description address of PDMA controller. Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address.
bits : 0 - 31 (32 bit)
access : read-only

SA : PDMA Transfer Source Address Register This field indicates a 32-bit source address of PDMA controller.
bits : 0 - 31 (32 bit)
access : read-write

CHEN0 : PDMA Channel 0 Enable Bit Set this bit to 1 to enable PDMA channel 0 operation. Channel 0 cannot be active if it is not set as enabled. Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN1 : PDMA Channel 1 Enable Bit Set this bit to 1 to enable PDMA channel 1 operation. Channel 1 cannot be active if it is not set as enabled. Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN2 : PDMA Channel 2 Enable Bit Set this bit to 1 to enable PDMA channel 2 operation. Channel 2 cannot be active if it is not set as enabled. Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN3 : PDMA Channel 3 Enable Bit Set this bit to 1 to enable PDMA channel 3 operation. Channel 3 cannot be active if it is not set as enabled. Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN4 : PDMA Channel 4 Enable Bit Set this bit to 1 to enable PDMA channel 4 operation. Channel 4 cannot be active if it is not set as enabled. Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN5 : PDMA Channel 5 Enable Bit Set this bit to 1 to enable PDMA channel 5 operation. Channel 5 cannot be active if it is not set as enabled. Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN6 : PDMA Channel 6 Enable Bit Set this bit to 1 to enable PDMA channel 6 operation. Channel 6 cannot be active if it is not set as enabled. Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN7 : PDMA Channel 7 Enable Bit Set this bit to 1 to enable PDMA channel 7 operation. Channel 7 cannot be active if it is not set as enabled. Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN8 : PDMA Channel 8 Enable Bit Set this bit to 1 to enable PDMA channel 8 operation. Channel 8 cannot be active if it is not set as enabled. Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN9 : PDMA Channel 9 Enable Bit Set this bit to 1 to enable PDMA channel 9 operation. Channel 9 cannot be active if it is not set as enabled. Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN10 : PDMA Channel 10 Enable Bit Set this bit to 1 to enable PDMA channel 10 operation. Channel 10 cannot be active if it is not set as enabled. Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN11 : PDMA Channel 11 Enable Bit Set this bit to 1 to enable PDMA channel 11 operation. Channel 11 cannot be active if it is not set as enabled. Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN12 : PDMA Channel 12 Enable Bit Set this bit to 1 to enable PDMA channel 12 operation. Channel 12 cannot be active if it is not set as enabled. Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN13 : PDMA Channel 13 Enable Bit Set this bit to 1 to enable PDMA channel 13 operation. Channel 13 cannot be active if it is not set as enabled. Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN14 : PDMA Channel 14 Enable Bit Set this bit to 1 to enable PDMA channel 14 operation. Channel 14 cannot be active if it is not set as enabled. Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN15 : PDMA Channel 15 Enable Bit Set this bit to 1 to enable PDMA channel 15 operation. Channel 15 cannot be active if it is not set as enabled. Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STOP0 : PDMA Channel 0 Transfer Stop Control Register (Write Only) User can set this bit to stop the PDMA channel 0 transfer. When user sets STOP0 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN0 (PDMA_CHCTL [0]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

STOP1 : PDMA Channel 1 Transfer Stop Control Register (Write Only) User can set this bit to stop the PDMA channel 1 transfer. When user sets STOP1 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN1 (PDMA_CHCTL [1]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

STOP2 : PDMA Channel 2 Transfer Stop Control Register (Write Only) User can set this bit to stop the PDMA channel 2 transfer. When user sets STOP2 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN2 (PDMA_CHCTL [2]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 2 - 2 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

STOP3 : PDMA Channel 3 Transfer Stop Control Register (Write Only) User can set this bit to stop the PDMA channel 3 transfer. When user sets STOP3 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN3 (PDMA_CHCTL [3]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 3 - 3 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

STOP4 : PDMA Channel 4 Transfer Stop Control Register (Write Only) User can set this bit to stop the PDMA channel 4 transfer. When user sets STOP4 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN4 (PDMA_CHCTL [4]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 4 - 4 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

STOP5 : PDMA Channel 5 Transfer Stop Control Register (Write Only) User can set this bit to stop the PDMA channel 5 transfer. When user sets STOP5 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN5 (PDMA_CHCTL [5]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 5 - 5 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

STOP6 : PDMA Channel 6 Transfer Stop Control Register (Write Only) User can set this bit to stop the PDMA channel 6 transfer. When user sets STOP6 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN6 (PDMA_CHCTL [6]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 6 - 6 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

STOP7 : PDMA Channel 7 Transfer Stop Control Register (Write Only) User can set this bit to stop the PDMA channel 7 transfer. When user sets STOP7 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN7 (PDMA_CHCTL [7]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 7 - 7 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

STOP8 : PDMA Channel 8 Transfer Stop Control Register (Write Only) User can set this bit to stop the PDMA channel 8 transfer. When user sets STOP8 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN8 (PDMA_CHCTL [8]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

STOP9 : PDMA Channel 9 Transfer Stop Control Register (Write Only) User can set this bit to stop the PDMA channel 9 transfer. When user sets STOP9 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN9 (PDMA_CHCTL [9]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

STOP10 : PDMA Channel 10 Transfer Stop Control Register (Write Only) User can set this bit to stop the PDMA channel 10 transfer. When user sets STOP10 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN10 (PDMA_CHCTL [10]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

STOP11 : PDMA Channel 11 Transfer Stop Control Register (Write Only) User can set this bit to stop the PDMA channel 11 transfer. When user sets STOP11 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN11 (PDMA_CHCTL [11]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

STOP12 : PDMA Channel 12 Transfer Stop Control Register (Write Only) User can set this bit to stop the PDMA channel 12 transfer. When user sets STOP12 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN12 (PDMA_CHCTL [12]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

STOP13 : PDMA Channel 13 Transfer Stop Control Register (Write Only) User can set this bit to stop the PDMA channel 13 transfer. When user sets STOP13 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN13 (PDMA_CHCTL [13]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

STOP14 : PDMA Channel 14 Transfer Stop Control Register (Write Only) User can set this bit to stop the PDMA channel 14 transfer. When user sets STOP14 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN14 (PDMA_CHCTL [14]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

STOP15 : PDMA Channel 15 Transfer Stop Control Register (Write Only) User can set this bit to stop the PDMA channel 15 transfer. When user sets STOP15 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN15 (PDMA_CHCTL [15]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
bits : 15 - 15 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ0 : PDMA Channel 0 Software Request Register (Write Only) Set this bit to 1 to generate a software request to PDMA Channel 0. Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ1 : PDMA Channel 1 Software Request Register (Write Only) Set this bit to 1 to generate a software request to PDMA Channel 1. Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ2 : PDMA Channel 2 Software Request Register (Write Only) Set this bit to 1 to generate a software request to PDMA Channel 2. Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 2 - 2 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ3 : PDMA Channel 3 Software Request Register (Write Only) Set this bit to 1 to generate a software request to PDMA Channel 3. Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 3 - 3 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ4 : PDMA Channel 4 Software Request Register (Write Only) Set this bit to 1 to generate a software request to PDMA Channel 4. Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 4 - 4 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ5 : PDMA Channel 5 Software Request Register (Write Only) Set this bit to 1 to generate a software request to PDMA Channel 5. Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 5 - 5 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ6 : PDMA Channel 6 Software Request Register (Write Only) Set this bit to 1 to generate a software request to PDMA Channel 6. Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 6 - 6 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ7 : PDMA Channel 7 Software Request Register (Write Only) Set this bit to 1 to generate a software request to PDMA Channel 7. Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 7 - 7 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ8 : PDMA Channel 8 Software Request Register (Write Only) Set this bit to 1 to generate a software request to PDMA Channel 8. Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ9 : PDMA Channel 9 Software Request Register (Write Only) Set this bit to 1 to generate a software request to PDMA Channel 9. Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ10 : PDMA Channel 10 Software Request Register (Write Only) Set this bit to 1 to generate a software request to PDMA Channel 10. Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ11 : PDMA Channel 11 Software Request Register (Write Only) Set this bit to 1 to generate a software request to PDMA Channel 11. Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ12 : PDMA Channel 12 Software Request Register (Write Only) Set this bit to 1 to generate a software request to PDMA Channel 12. Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ13 : PDMA Channel 13 Software Request Register (Write Only) Set this bit to 1 to generate a software request to PDMA Channel 13. Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ14 : PDMA Channel 14 Software Request Register (Write Only) Set this bit to 1 to generate a software request to PDMA Channel 14. Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ15 : PDMA Channel 15 Software Request Register (Write Only) Set this bit to 1 to generate a software request to PDMA Channel 15. Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request. Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 15 - 15 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

REQSTS0 : PDMA Channel 0 Request Status (Read Only) This flag indicates whether channel 0 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS1 : PDMA Channel 1 Request Status (Read Only) This flag indicates whether channel 1 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS2 : PDMA Channel 2 Request Status (Read Only) This flag indicates whether channel 2 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS3 : PDMA Channel 3 Request Status (Read Only) This flag indicates whether channel 3 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS4 : PDMA Channel 4 Request Status (Read Only) This flag indicates whether channel 4 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS5 : PDMA Channel 5 Request Status (Read Only) This flag indicates whether channel 5 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS6 : PDMA Channel 6 Request Status (Read Only) This flag indicates whether channel 6 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS7 : PDMA Channel 7 Request Status (Read Only) This flag indicates whether channel 7 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS8 : PDMA Channel 8 Request Status (Read Only) This flag indicates whether channel 8 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS9 : PDMA Channel 9 Request Status (Read Only) This flag indicates whether channel 9 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note1: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS10 : PDMA Channel 10 Request Status (Read Only) This flag indicates whether channel 10 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS11 : PDMA Channel 11 Request Status (Read Only) This flag indicates whether channel 11 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS12 : PDMA Channel 12 Request Status (Read Only) This flag indicates whether channel 12 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS13 : PDMA Channel 13 Request Status (Read Only) This flag indicates whether channel 13 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS14 : PDMA Channel 14 Request Status (Read Only) This flag indicates whether channel 14 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS15 : PDMA Channel 15 Request Status (Read Only) This flag indicates whether channel 15 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

FPRISET0 : PDMA Channel 0 Fixed Priority Setting Register Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET1 : PDMA Channel 1 Fixed Priority Setting Register Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET2 : PDMA Channel 2 Fixed Priority Setting Register Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET3 : PDMA Channel 3 Fixed Priority Setting Register Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET4 : PDMA Channel 4 Fixed Priority Setting Register Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET5 : PDMA Channel 5 Fixed Priority Setting Register Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET6 : PDMA Channel 6 Fixed Priority Setting Register Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET7 : PDMA Channel 7 Fixed Priority Setting Register Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET8 : PDMA Channel 8 Fixed Priority Setting Register Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET9 : PDMA Channel 9 Fixed Priority Setting Register Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET10 : PDMA Channel 10 Fixed Priority Setting Register Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET11 : PDMA Channel 10 Fixed Priority Setting Register Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET12 : PDMA Channel 12 Fixed Priority Setting Register Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET13 : PDMA Channel 13 Fixed Priority Setting Register Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET14 : PDMA Channel 14 Fixed Priority Setting Register Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET15 : PDMA Channel 15 Fixed Priority Setting Register Set this bit to 1 to enable fixed priority level. Write Operation: Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRICLR0 : PDMA Channel 0 Fixed Priority Clear Register (Write Only) Set this bit to 1 to clear fixed priority level. Note: User can read PDMA_PRISET register to know the channel priority.
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR1 : PDMA Channel 1 Fixed Priority Clear Register (Write Only) Set this bit to 1 to clear fixed priority level. Note: User can read PDMA_PRISET register to know the channel priority.
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR2 : PDMA Channel 2 Fixed Priority Clear Register (Write Only) Set this bit to 1 to clear fixed priority level. Note: User can read PDMA_PRISET register to know the channel priority.
bits : 2 - 2 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR3 : PDMA Channel 3 Fixed Priority Clear Register (Write Only) Set this bit to 1 to clear fixed priority level. Note: User can read PDMA_PRISET register to know the channel priority.
bits : 3 - 3 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR4 : PDMA Channel 4 Fixed Priority Clear Register (Write Only) Set this bit to 1 to clear fixed priority level. Note: User can read PDMA_PRISET register to know the channel priority.
bits : 4 - 4 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR5 : PDMA Channel 5 Fixed Priority Clear Register (Write Only) Set this bit to 1 to clear fixed priority level. Note: User can read PDMA_PRISET register to know the channel priority.
bits : 5 - 5 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR6 : PDMA Channel 6 Fixed Priority Clear Register (Write Only) Set this bit to 1 to clear fixed priority level. Note: User can read PDMA_PRISET register to know the channel priority.
bits : 6 - 6 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR7 : PDMA Channel 7 Fixed Priority Clear Register (Write Only) Set this bit to 1 to clear fixed priority level. Note: User can read PDMA_PRISET register to know the channel priority.
bits : 7 - 7 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR8 : PDMA Channel 8 Fixed Priority Clear Register (Write Only) Set this bit to 1 to clear fixed priority level. Note: User can read PDMA_PRISET register to know the channel priority.
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR9 : PDMA Channel 9 Fixed Priority Clear Register (Write Only) Set this bit to 1 to clear fixed priority level. Note: User can read PDMA_PRISET register to know the channel priority.
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR10 : PDMA Channel 10 Fixed Priority Clear Register (Write Only) Set this bit to 1 to clear fixed priority level. Note: User can read PDMA_PRISET register to know the channel priority.
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR11 : PDMA Channel 11 Fixed Priority Clear Register (Write Only) Set this bit to 1 to clear fixed priority level. Note: User can read PDMA_PRISET register to know the channel priority.
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR12 : PDMA Channel 12 Fixed Priority Clear Register (Write Only) Set this bit to 1 to clear fixed priority level. Note: User can read PDMA_PRISET register to know the channel priority.
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR13 : PDMA Channel 13 Fixed Priority Clear Register (Write Only) Set this bit to 1 to clear fixed priority level. Note: User can read PDMA_PRISET register to know the channel priority.
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR14 : PDMA Channel 14 Fixed Priority Clear Register (Write Only) Set this bit to 1 to clear fixed priority level. Note: User can read PDMA_PRISET register to know the channel priority.
bits : 14 - 14 (1 bit)
access : write-only

Enumeration: