TIMER2_CTL

TIMER2_CAP

TIMER3_CTL

TIMER3_CMP

TIMER3_INTSTS

TIMER3_CNT

TIMER3_CAP

TIMER3_EXTCTL

TIMER3_EINTSTS

TIMER3_TRGCTL

TIMER3_ALTCTL

TIMER2_EXTCTL

TIMER3_PWMCTL

TIMER3_PWMCLKSRC

TIMER3_PWMCLKPSC

TIMER3_PWMCNTCLR

TIMER3_PWMPERIOD

TIMER3_PWMCMPDAT

TIMER3_PWMDTCTL

TIMER3_PWMCNT

TIMER3_PWMMSKEN

TIMER3_PWMMSK

TIMER3_PWMPOLCTL

TIMER3_PWMPOEN

TIMER2_EINTSTS

TIMER3_PWMINTEN0

TIMER3_PWMINTSTS0

TIMER3_PWMSCTL

TIMER3_PWMSTATUS

TIMER3_PWMPBUF

TIMER3_PWMCMPBUF

TIMER2_TRGCTL

TIMER2_ALTCTL

TIMER2_CMP

TIMER2_PWMCTL

TIMER2_PWMCLKSRC

TIMER2_PWMCLKPSC

TIMER2_PWMCNTCLR

TIMER2_PWMPERIOD

TIMER2_PWMCMPDAT

TIMER2_PWMDTCTL

TIMER2_PWMCNT

TIMER2_PWMMSKEN

TIMER2_PWMMSK

TIMER2_PWMPOLCTL

TIMER2_PWMPOEN

TIMER2_INTSTS

TIMER2_PWMINTEN0

TIMER2_PWMINTSTS0

TIMER2_PWMSCTL

TIMER2_PWMSTRG

TIMER2_PWMSTATUS

TIMER2_PWMPBUF

TIMER2_PWMCMPBUF

TIMER2_CNT

PSC : Prescale Counter Note: Overwriting prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
bits : 0 - 7 (8 bit)
access : read-write

INTRGEN : Inter-timer Trigger Mode Enable Control Setting this bit will enable the inter-timer trigger capture function. The Timer0/2 will be in event counter mode and counting with external clock source or event.Also, Timer1/3 will be in trigger-counting mode of capture function. Note: For Timer1/3, this bit is ignored and the read back value is always 0.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PERIOSEL : Periodic Mode Behavior Selection Enable Bit If updated CMPDAT value CNT, CNT will be reset to default value.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TGLPINSEL : Toggle-output Pin Select
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKEN : Wake-up Function Enable Bit If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EXTCNTEN : Event Counter Mode Enable Bit This bit is for external counting pin function enabled. Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACTSTS : Timer Active Status Bit (Read Only) This bit indicates the 24-bit up counter status. Note: This bit may active when CNT 0 transition to CNT 1.
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

OPMODE : Timer Counting Mode Select
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN : Timer Interrupt Enable Bit Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN : Timer Counting Enable Bit Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ICEDEBUG : ICE Debug Mode Acknowledge Disable Control (Write Protected) TIMER counter will keep going no matter CPU is held by ICE or not. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPDAT : Timer Capture Data Register (Read Only) When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
bits : 0 - 23 (24 bit)
access : read-only

CNTPHASE : Timer External Count Phase
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPEN : Timer External Capture Pin Enable Bit This bit enables the TMx_EXT capture pin input function.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPFUNCS : Capture Function Selection
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIEN : Timer External Capture Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPDBEN : Timer External Capture Pin De-bounce Enable Bit Note: If this bit is enabled, the edge detection of TMx_EXT pin output is detected with de-bounce circuit.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTDBEN : Timer Counter Pin De-bounce Enable Bit Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPEDGE : Timer External Capture Pin Edge Detect When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ECNTSSEL : Event Counter Source Selection to Trigger Event Counter Function
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIF : Timer External Capture Interrupt Flag This bit indicates the timer external capture interrupt flag status. Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGSSEL : Trigger Source Select Bit This bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGPWM : Trigger PWM Enable Bit If this bit is set to 1, each timer time-out event or capture event can be as PWM counter clock source.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGPDMA : Trigger PDMA Enable Bit If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FUNCSEL : Function Selection Note: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDAT : Timer Comparator Value CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1. Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state. Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
bits : 0 - 23 (24 bit)
access : read-write

CNTEN : PWM Counter Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTTYPE : PWM Counter Behavior Type
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTMODE : PWM Counter Mode
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CTRLD : Center Re-load In up-down count type, PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period.
bits : 8 - 8 (1 bit)
access : read-write

IMMLDEN : Immediately Load Enable Bit Note: If IMMLDEN is enabled, CTRLD will be invalid.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OUTMODE : PWM Output Mode This bit controls the output mode of corresponding PWM channel.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBGHALT : ICE Debug Mode Counter Halt (Write Protected) If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode. Note: This register is write protected. Refer toSYS_REGLCTL register.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBGTRIOFF : ICE Debug Mode Acknowledge Disable Bit (Write Protected) PWM output pin will keep output no matter ICE debug mode acknowledged or not. Note: This register is write protected. Refer toSYS_REGLCTL register.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKSRC : PWM Counter Clock Source Select The PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event. Note: If TIMER0 PWM function is enabled, the PWM counter clock source can be selected from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt events.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKPSC : PWM Counter Clock Pre-scale The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0, then there is no scaling in PWM counter clock source.
bits : 0 - 11 (12 bit)
access : read-write

CNTCLR : Clear PWM Counter Control Bit It is automatically cleared by hardware.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PERIOD : PWM Period Register In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0. In down count type: PWM counter counts from PERIOD to 0, and restarts from PERIOD. In up-down count type: PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. In up and down count type: Note: User should take care DIRF (TIMERx_PWMCNT[16]) bit in up/down/up-down count type to monitor current counter direction in each count type.
bits : 0 - 15 (16 bit)
access : read-write

CMP : PWM Comparator Register PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events.
bits : 0 - 15 (16 bit)
access : read-write

DTCNT : Dead-time Counter (Write Protected) The dead-time can be calculated from the following two formulas: Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 0 - 11 (12 bit)
access : read-write

DTEN : Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protected) Dead-time insertion function is only active when PWM complementary mode is enabled. If dead- time insertion is inactive, the outputs of PWMx_CH0 and PWMx_CH1 are complementary without any delay. Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTCKSEL : Dead-time Clock Select (Write Protected) Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNT : PWM Counter Value Register (Read Only) User can monitor CNT to know the current counter value in 16-bit period counter.
bits : 0 - 15 (16 bit)
access : read-only

DIRF : PWM Counter Direction Indicator Flag (Read Only)
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

MSKEN0 : PWMx_CH0 Output Mask Enable Bit The PWMx_CH0 output signal will be masked when this bit is enabled. The PWMx_CH0 will output MSKDAT0 (TIMER_PWMMSK[0]) data.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN1 : PWMx_CH1 Output Mask Enable Bit The PWMx_CH1 output signal will be masked when this bit is enabled. The PWMx_CH1 will output MSKDAT1 (TIMER_PWMMSK[1]) data.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT0 : PWMx_CH0 Output Mask Data Control Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT1 : PWMx_CH1 Output Mask Data Control Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.