CRYPTO_INTEN (INTEN)

CRYPTO_PRNG_KEY0 (PRNG_KEY0)

CRYPTO_AES_CTL (AES_CTL)

CRYPTO_AES_STS (AES_STS)

CRYPTO_AES_DATIN (AES_DATIN)

CRYPTO_AES_DATOUT (AES_DATOUT)

CRYPTO_AES0_KEY0 (AES0_KEY0)

CRYPTO_AES0_KEY1 (AES0_KEY1)

CRYPTO_AES0_KEY2 (AES0_KEY2)

CRYPTO_AES0_KEY3 (AES0_KEY3)

CRYPTO_AES0_KEY4 (AES0_KEY4)

CRYPTO_AES0_KEY5 (AES0_KEY5)

CRYPTO_AES0_KEY6 (AES0_KEY6)

CRYPTO_AES0_KEY7 (AES0_KEY7)

CRYPTO_AES0_IV0 (AES0_IV0)

CRYPTO_AES0_IV1 (AES0_IV1)

CRYPTO_AES0_IV2 (AES0_IV2)

CRYPTO_AES0_IV3 (AES0_IV3)

CRYPTO_PRNG_KEY1 (PRNG_KEY1)

CRYPTO_AES0_SADDR (AES0_SADDR)

CRYPTO_AES0_DADDR (AES0_DADDR)

CRYPTO_AES0_CNT (AES0_CNT)

CRYPTO_PRNG_KEY2 (PRNG_KEY2)

CRYPTO_PRNG_KEY3 (PRNG_KEY3)

CRYPTO_PRNG_KEY4 (PRNG_KEY4)

CRYPTO_PRNG_KEY5 (PRNG_KEY5)

CRYPTO_PRNG_KEY6 (PRNG_KEY6)

CRYPTO_PRNG_KEY7 (PRNG_KEY7)

CRYPTO_SHA_CTL (SHA_CTL)

CRYPTO_SHA_STS (SHA_STS)

CRYPTO_SHA_DGST0 (SHA_DGST0)

CRYPTO_SHA_DGST1 (SHA_DGST1)

CRYPTO_SHA_DGST2 (SHA_DGST2)

CRYPTO_SHA_DGST3 (SHA_DGST3)

CRYPTO_SHA_DGST4 (SHA_DGST4)

CRYPTO_SHA_DGST5 (SHA_DGST5)

CRYPTO_SHA_DGST6 (SHA_DGST6)

CRYPTO_SHA_DGST7 (SHA_DGST7)

CRYPTO_SHA_KEYCNT (SHA_KEYCNT)

CRYPTO_SHA_SADDR (SHA_SADDR)

CRYPTO_SHA_DMACNT (SHA_DMACNT)

CRYPTO_SHA_DATIN (SHA_DATIN)

CRYPTO_INTSTS (INTSTS)

CRYPTO_AES_FDBCK0 (AES_FDBCK0)

CRYPTO_AES_FDBCK1 (AES_FDBCK1)

CRYPTO_AES_FDBCK2 (AES_FDBCK2)

CRYPTO_AES_FDBCK3 (AES_FDBCK3)

CRYPTO_PRNG_CTL (PRNG_CTL)

CRYPTO_PRNG_SEED (PRNG_SEED)

AESIEN : AES Interrupt Enable Bit Note: In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine. In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AESEIEN : AES Error Flag Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRNGIEN : PRNG Interrupt Enable Bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SHAIEN : SHA Interrupt Enable Bit Note: In DMA mode, an interrupt will be triggered when amount of data set in SHA _DMA_CNT is fed into the SHA engine. In Non-DMA mode, an interrupt will be triggered when the SHA engine finishes the operation.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SHAEIEN : SHA Error Interrupt Enable Bit
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

KEY : Store PRNG Generated Key (Read Only) The bits store the key that is generated by PRNG.
bits : 0 - 31 (32 bit)
access : read-only

START : AES Engine Start Note: This bit is always 0 when it's read back.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STOP : AES Engine Stop Note: This bit is always 0 when it's read back.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

KEYSZ : AES Key Size This bit defines three different key size for AES operation. If the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMALAST : AES Last Block In DMA mode, this bit must be set as beginning the last DMA cascade round. In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode. This bit is always 0 when it's read back. Must be written again once START is triggered.
bits : 5 - 5 (1 bit)
access : read-write

DMACSCAD : AES Engine DMA with Cascade Mode
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMAEN : AES Engine DMA Enable Bit The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE : AES Engine Operation Modes
bits : 8 - 15 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ENCRYPTO : AES Encryption/Decryption
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OUTSWAP : AES Engine Output Data Swap
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INSWAP : AES Engine Input Data Swap
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHANNEL : AES Engine Working Channel Keeps this field as 0x00.
bits : 24 - 25 (2 bit)
access : read-write

KEYUNPRT : Unprotect Key Writing 0 to CRYPTO_AES_CTL[31] and '10110' to CRYPTO_AES_CTL[30:26] is that AES key is unprotected. The KEYUNPRT can be read and written. When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
bits : 26 - 30 (5 bit)
access : read-write

KEYPRT : Protect Key Read as a flag to reflect KEYPRT.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSY : AES Engine Busy
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

INBUFEMPTY : AES Input Buffer Empty
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

INBUFFULL : AES Input Buffer Full Flag
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

INBUFERR : AES Input Buffer Error Flag
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CNTERR : CRYPTO_AES0_CNT Setting Error
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

OUTBUFEMPTY : AES Out Buffer Empty
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

OUTBUFFULL : AES Out Buffer Full Flag
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

OUTBUFERR : AES Out Buffer Error Flag
bits : 18 - 18 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BUSERR : AES DMA Access Bus Error Flag
bits : 20 - 20 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DATIN : AES Engine Input Port CPU feeds data to AES engine through this port by checking CRYPTO_AES_STS. Feed data when INBUFFULL is 0.
bits : 0 - 31 (32 bit)
access : read-write

DATOUT : AES Engine Output Port CPU gets results from the AES engine through this port by checking CRYPTO_AES_STS. Get data when OUTBUFEMPTY is 0.
bits : 0 - 31 (32 bit)
access : read-only

KEY : CRYPTO_AES0_KEYx The KEY keeps the security key for AES operation. {CRYPTO_AES0_KEY7, CRYPTO_AES0_KEY6, CRYPTO_AES0_KEY5, CRYPTO_AES0_KEY4, CRYPTO_AES0_KEY3, CRYPTO_AES0_KEY2, CRYPTO_AES0_KEY1, CRYPTO_AES0_KEY0} stores the 256-bit security key for AES operation.
bits : 0 - 31 (32 bit)
access : read-write

IV : AES Initial Vectors Four initial vectors (CRYPTO_AES0_IV0, CRYPTO_AES0_IV1, CRYPTO_AES0_IV2, and CRYPTO_AES0_IV3) are for AES operating in CBC, CFB, and OFB mode. Four registers (CRYPTO_AES0_IV0, CRYPTO_AES0_IV1, CRYPTO_AES0_IV2, and CRYPTO_AES0_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
bits : 0 - 31 (32 bit)
access : read-write

SADDR : AES DMA Source Address The AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO. The SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address, the AES accelerator can read the plain text (encryption) / cipher text (descryption) from SRAM memory space and do AES operation. The start of source address should be located at word boundary. In other words, bit 1 and 0 of SADDR are ignored. SADDR can be read and written. Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation. But the value of SADDR will be updated later on. Consequently, software can prepare the DMA source address for the next AES operation. In DMA mode, software can update the next CRYPTO_AES0_SADDR before triggering START. The value of CRYPTO_AES0_SADDR and CRYPTO_AES0_DADDR can be the same.
bits : 0 - 31 (32 bit)
access : read-write

DADDR : AES DMA Destination Address The AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO. The DADDR keeps the destination address of the data buffer where the engine output's text will be stored. Based on the destination address, the AES accelerator can write the cipher text (encryption) / plain text (decryption) back to SRAM memory space after the AES operation is finished. The start of destination address should be located at word boundary. In other words, bit 1 and 0 of DADDR are ignored. DADDR can be read and written. Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation. But the value of DADDR will be updated later on. Consequently, software can prepare the destination address for the next AES operation. In DMA mode, software can update the next CRYPTO_AES0_DADDR before triggering START. The value of CRYPTO_AES0_SADDR and CRYPTO_AES0_DADDR can be the same.
bits : 0 - 31 (32 bit)
access : read-write

CNT : AES Byte Count The CRYPTO_AES0_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode. The CRYPTO_AES0_CNT is 32-bit and the maximum of byte count is 4G bytes. CRYPTO_AES0_CNT can be read and written. Writing to CRYPTO_AES0_CNT while the AES accelerator is operating doesn't affect the current AES operation. But the value of CRYPTO_AES0_CNT will be updated later on. Consequently, software can prepare the byte count of data for the next AES operation. According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be more than 16 bytes. Operations that are qual or less than one block will output unexpected result. In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRYPTO_AES0_CNT must be set as byte count for the last block of data before feeding in the last block of data. In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRYPTO_AES0_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
bits : 0 - 31 (32 bit)
access : read-write

START : SHA Engine Start Note: This bit is always 0 when it's read back.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STOP : SHA Engine Stop Note: This bit is always 0 when it's read back.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMAFIRST : SHA First Block in cascadefunction This bit must be set as feeding in first byte of data.
bits : 4 - 4 (1 bit)
access : read-write

DMALAST : SHA Last Block This bit must be set as feeding in last byte of data.
bits : 5 - 5 (1 bit)
access : read-write

DMACSCAD : SHA Engine DMA with Cascade Mode
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMAEN : SHA Engine DMA Enable Bit SHA engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE : SHA Engine Operation Modes 0x100: SHA256 Note: These bits can be read and written. But writing to them wouldn't take effect as BUSY is 1.
bits : 8 - 10 (3 bit)
access : read-write

SHAEN : SHA Engine Operating Mode
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OUTSWAP : SHA Engine Output Data Swap
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INSWAP : SHA Engine Input Data Swap
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSY : SHA Engine Busy
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DMABUSY : SHA Engine DMA Busy Flag
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DMAERR : SHA Engine DMA Error Flag
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DATINREQ : SHA Non-DMA Mode Data Input Request
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DGST : SHA Digest Message Output Register For SHA-256, the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST7.
bits : 0 - 31 (32 bit)
access : read-only

KEYCNT : SHA Key Byte Count The CRYPTO_SHA_KEYCNT keeps the byte count of key that SHA engine operates. The register is 32-bit and the maximum byte count is 4G bytes. It can be read and written. Writing to the register CRYPTO_SHA_KEYCNT as the SHA accelerator operating doesn't affect the current SHA operation. But the value of CRYPTO_SHA _KEYCNT will be updated later on. Consequently, software can prepare the key count for the next SHA operation.
bits : 0 - 31 (32 bit)
access : read-write

SADDR : SHA DMA Source Address The SHA accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO. The CRYPTO_SHA_SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address, the SHA accelerator can read the plain text from SRAM memory space and do SHA operation. The start of source address should be located at word boundary. In other words, bit 1 and 0 of CRYPTO_SHA_SADDR are ignored. CRYPTO_SHA_SADDR can be read and written. Writing to CRYPTO_SHA_SADDR while the SHA accelerator is operating doesn't affect the current SHA operation. But the value of CRYPTOSHA_SHA_SADDR will be updated later on. Consequently, software can prepare the DMA source address for the next SHA operation. In DMA mode, software can update the next CRYPTO_SHA_SADDR before triggering START. CRYPTO_SHA_SADDR and CRYPTO_SHA_DADDR can be the same in the value.
bits : 0 - 31 (32 bit)
access : read-write

DMACNT : SHA Operation Byte Count The CRYPTO_SHA_DMACNT keeps the byte count of source text that is for the SHA engine operating in DMA mode. The CRYPTO_SHA_DMACNT is 32-bit and the maximum of byte count is 4G bytes. CRYPTO_SHA_DMACNT can be read and written. Writing to CRYPTO_SHA_DMACNT while the SHA accelerator is operating doesn't affect the current SHA operation. But the value of CRYPTO_SHA_DMACNT will be updated later on. Consequently, software can prepare the byte count of data for the next SHA operation. In Non-DMA mode, CRYPTO_SHA_DMACNT must be set as the byte count of the last block before feeding in the last block of data.
bits : 0 - 31 (32 bit)
access : read-write

DATIN : SHA Engine Input Port CPU feeds data to SHA engine through this port by checking CRYPTO_SHA_STS. Feed data when DATINREQ is 1.
bits : 0 - 31 (32 bit)
access : read-write

AESIF : AES Finish Interrupt Flag This bit is cleared by writing 1, and it has no effect by writing 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AESEIF : AES Error Flag This bit is cleared by writing 1, and it has no effect by writing 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRNGIF : PRNG Finish Interrupt Flag This bit is cleared by writing 1, and it has no effect by writing 0.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SHAIF : SHASHA Finish Interrupt Flag This bit is cleared by writing 1, and it has no effect by writing 0.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SHAEIF : SHA Error Flag This register includes operating and setting error. The detail flag is shown in CRYPTO_SHA_STS register. This bit is cleared by writing 1, and it has no effect by writing 0.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FDBCK : AES Feedback Information The feedback value is 128 bits in size. The AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AES0_IVx for the next block in DMA cascade mode. The AES engine outputs feedback information for IV in the next block's operation. Software can use this feedback information to implement more than four DMA channels. Software can store that feedback value temporarily. After switching back, fill the stored feedback value to CRYPTO_AES0_IVx in the same channel operation, and then continue the operation with the original setting.
bits : 0 - 31 (32 bit)
access : read-only