DMIC_CTL (CTL)

DMIC_FIFO (FIFO)

DMIC_GAIN0_1 (GAIN0_1)

DMIC_GAIN2_3 (GAIN2_3)

DMIC_RAMCFG (RAMCFG)

DMIC_ZCTH (ZCTH)

DMIC_DIV (DIV)

DMIC_STATUS (STATUS)

DMIC_PDMACTL (PDMACTL)

CHEN0 : DMIC Channel 0 Enable Bit Set this bit to 1 to enable DMIC channel 0 operation.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN1 : DMIC Channel 1 Enable Bit Set this bit to 1 to enable DMIC channel 1 operation.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN2 : DMIC Channel 2 Enable Bit Set this bit to 1 to enable DMIC channel 2 operation.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN3 : DMIC Channel 3 Enable Bit Set this bit to 1 to enable DMIC channel 3 operation.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LEDGE01 : DMIC Channel 01 Data Latch Edge The data of DMIC channel 0 and channel 1 is latched on DMIC_DATA0 pin. This bit is used to select the data of DMIC channel 0 and channel 1 is latched on rising or falling edge of DMIC_CLK (DMIC bus clock).
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LEDGE23 : DMIC Channel 23 Data Latch Edge The data of DMIC channel 2 and channel 3 is latched on DMIC_DATA0 pin. This bit is used to select the data of DMIC channel 2 and channel 3 is latched on rising or falling edge of DMIC_CLK (DMIC bus clock).
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0MUTE : DMIC Channel 0 Mute Enable Bit Set this bit to 1 to mute DMIC channel 0.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1MUTE : DMIC Channel 1 Mute Enable Bit Set this bit to 1 to mute DMIC channel 1.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

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CH2MUTE : DMIC Channel 2 Mute Enable Bit Set this bit to 1 to mute DMIC channel 2.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH3MUTE : DMIC Channel 3 Mute Enable Bit Set this bit to 1 to mute DMIC channel 3.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH01HPF : DMIC Channel 01 High Pass Filter Enable Bit Set this bit to 1 to Enable DMIC channel 0 and channel 1 HPF filter for remove DC component.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH23HPF : DMIC Channel 23 High Pass Filter Enable Bit Set this bit to 1 to Enable DMIC channel 2 and channel 3 HPF filter for remove DC component.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

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SWRST : Internal State Software Reset. Set this bit to 1 to Reset DMIC state machine, but all DMIC registers are kept unchanged.
bits : 24 - 24 (1 bit)
access : read-write

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GAINSTEP : Volume Control Gain Adjust Step for Decimal Point.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

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DATWIDTH : Data Effective Bit in FIFO
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIFO : FIFO Data Output Register DMIC contains 32 level (32x24 bit) data buffer for data receive. A read to this register pushes data out from FIFO data buffer and decrements the read pointer. This is the address that PDMA reads audio data from. The remaining data word number is indicated by FIFOPTR (DMIC_STATUS[8:4]).
bits : 0 - 23 (24 bit)
access : write-only

CH0GAIN : Channel 0 Gain Control A 16-bit signed 2's complement number, content is as following Bit15: Sign bit Bit14~Bit7: Integer Part Bit6: Decimal Part,0.5dB Bit5: Decimal Part, 0.25dB Bit4: Decimal Part,0.125dB Bit3~Bit0: Reserved The mapping between real gain and programmed number is For example, if the desired gain is 0dB, the programmed value will be -128 (0xC000) if the desired gain is -20.5dB, the programmed value will be -107.5(0xCA40)
bits : 0 - 15 (16 bit)
access : read-write

CH1GAIN : Channel 1 Gain Control A 16-bit signed 2's complement number, content is as following Bit15: Sign bit Bit14~Bit7: Integer Part Bit6: Decimal Part,0.5dB Bit5: Decimal Part, 0.25dB Bit4: Decimal Part,0.125dB Bit3~Bit0: Reserved The mapping between real gain and programmed number is For example, if the desired gain is 0dB, the programmed value will be -128 (0xC000) if the desired gain is -20.5dB, the programmed value will be -107.5(0xCA40)
bits : 16 - 31 (16 bit)
access : read-write

CH2GAIN : Channel 2 Gain Control A 16-bit signed 2's complement number, content is as following Bit15: Sign bit Bit14~Bit7: Integer Part Bit6: Decimal Part,0.5dB Bit5: Decimal Part, 0.25dB Bit4: Decimal Part,0.125dB Bit3~Bit0: Reserved The mapping between real gain and programmed number is For example, if the desired gain is 0dB, the programmed value will be -128 (0xC000) if the desired gain is -20.5dB, the programmed value will be -107.5(0xCA40)
bits : 0 - 15 (16 bit)
access : read-write

CH3GAIN : Channel 3 Gain Control A 16-bit signed 2's complement number, content is as following Bit15: Sign bit Bit14~Bit7: Integer Part Bit6: Decimal Part,0.5dB Bit5: Decimal Part, 0.25dB Bit4: Decimal Part,0.125dB Bit3~Bit0: Reserved The mapping between real gain and programmed number is For example, if the desired gain is 0dB, the programmed value will be -128 (0xC000) if the desired gain is -20.5dB, the programmed value will be -107.5(0xCA40)
bits : 16 - 31 (16 bit)
access : read-write

D0RAMCLR : DSP0 RAM Data Clear Note: This field is auto cleared by hardware.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

D1RAMCLR : DSP1 RAM Data Clear Note: This field is auto cleared by hardware.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZCTH : Zero Crossing Threshold for PCM Sample Amplitude Gain Adjustment. DMIC_ZCTH[23] is sign bit, the range [-8388688~8388607]
bits : 0 - 23 (24 bit)
access : read-write

MCLKDIV : Divider to Generate the DMIC Working Main Clock The value in this field is the frequency divider for generating the DMIC working main clock. The frequency is obtained according to the following equation. where F_DMIC_CLK_SRC is the frequency of DMIC module clock source, which is defined in the clock control register DMICSEL (CLK_CLKSEL2[11:9]) and F_DMIC_MCLK depends on the cycle of DMIC DSP processor needed, it is 49.152MHz in general.
bits : 0 - 7 (8 bit)
access : read-write

CLKDIV : Divider to Generate the DMIC Bus Clock The value in this field is the frequency divider for generating the DMIC bus clock. The frequency is obtained according to the following equation. where F_DMIC_MCLK is the frequency of DMIC working main clock (DMIC_MCLK) and F_DMIC_CLK is the frequency of DMIC bus clock (DMIC_CLK).
bits : 8 - 15 (8 bit)
access : read-write

DMTH : FIFO Threshold Level If the valid data count of the FIFO data buffer is more than or equal to DMTH (DMIC_DIV[20:16]) setting, the DMTHIF (DMIC_STATUS[2]) bit will set to 1, else the DMTHIF (DMIC_STATUS[2]) bit will be cleared to 0.
bits : 16 - 20 (5 bit)
access : read-write

DMTHIE : FIFO Threshold Interrupt
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

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FCLR : FIFO Clear Note 1: To clear the FIFO, need to write FCLR (DMIC_DIV[23:22]) to 11b, and can read the EMPTY (DMIC_STATUS[1]) bit to make sure that the FIFO has been cleared. Note 2: This field is auto cleared by hardware.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSR : DMIC OSR Setting
bits : 24 - 26 (3 bit)
access : read-write

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HPFCUTF : High Pass Filter Cut Off Frequency Selection
bits : 28 - 30 (3 bit)
access : read-write

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FULL : FIFO Full Indicator (Read Only)
bits : 0 - 0 (1 bit)
access : read-only

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EMPTY : FIFO Empty Indicator (Read Only)
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DMTHIF : FIFO Threshold Interrupt Status (Read Only)
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

FIFOPTR : FIFO Pointer (Read Only) The FULL (DMIC_STATUS[0]) and FIFOPTR (DMIC_STATUS[8:4]) indicates the field that the valid data count within the DMIC FIFO buffer. The maximum value shown in FIFOPTR (DMIC_STATUS[8:4]) is 31. When the using level of DMIC FIFO buffer equal to 32, The FULL (DMIC_STATUS[0]) is set to 1.
bits : 4 - 8 (5 bit)
access : read-only

PDMAEN : PDMA Transfer Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.