DPWM_CTL (CTL)

DPWM_ZOHDIV (ZOHDIV)

DPWM_FREQ (FREQ)

DPWM_STATUS (STATUS)

DPWM_PDMACTL (PDMACTL)

DPWM_FIFO (FIFO)

FIFOWIDTH : FIFO Data Width This bit field is used to define the bit-width of data word and valid bits in register DPWM_FIFO. Note: When FLTEN is '0', FIFOWIDTH is for fixed point setting.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DEADTIME : Driver Dead Time Control. Enabling this bit will insert an additional clock cycle deadtime into the switching of PMOS and NMOS driver transistors.
bits : 3 - 3 (1 bit)
access : read-write

MODESEL : Data Control in FIFO
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DPWMEN : Audio DPWM Modulator Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DRVEN : Driver Enable Bit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

THIE : FIFO Threshold Interrupt
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TH : FIFO Threshold Level If the valid data count of the FIFO data buffer is less than or equal to TH (DPWM_CTL[16:12]) setting, the THIF (DPWM_STATUS[2]) will set to 1, else the THIF (DPWM_STATUS[2]) will be cleared to 0.
bits : 12 - 16 (5 bit)
access : read-write

FCLR : FIFO Clear Note 1: To clear the FIFO, need to write FCLR (DPWM_CTL[29:28]) to 11b, and can read the EMPTY (DPWM_STATUS[1]) bit to make sure that the FIFO has been cleared. Note 2: This field is auto cleared by hardware.
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SWRST : State Machine Software Reset
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKSET : Working Clock Selection
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ZOHDIV : Zero Order Hold, Down-sampling Divisor The input sample rate of the DPWM is set by DPWM_CLK frequency and the divisor set in this register by the following formula:
bits : 0 - 7 (8 bit)
access : read-write

CLKDIV : Clock Divider Divider to generate the DPWM_CLK where F_ DPWM _CLK_SRC is the frequency of DPWM module clock source, which is defined in the clock control register DPWMSEL (CLK_CLKSEL2[13:12]) and F_DPWM_CLK is the frequency of DPWM module working clock (DPWM_CLK). Note 1: If fs is 48 kHz, the frequency of DPWM_CLK must be 24.576 MHz or 24 MHz according to the value of CLKSET (DPWM_CTL[31]). Note 2: If fs is 96 kHz, the frequency of DPWM_CLK must be 49.152 MHz or 48 MHz according to the value of CLKSET (DPWM_CTL[31]).
bits : 8 - 18 (11 bit)
access : read-write

FREQSEL : Output Signal FrequencySelection
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STEPSEL : Output Signal Frequency
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FULL : FIFO Full (Read Only)
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

EMPTY : FIFO Empty (Read Only)
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

THIF : FIFO Threshold Interrupt Status (Read Only)
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

FIFOPTR : FIFO Pointer (Read Only) The FULL (DPWM_STATUS[0]) and FIFOPTR (DPWM_STATUS[9:4]) indicates the field that the valid data count within the DPWM FIFO buffer. The maximum value shown in FIFOPTR is 32. When the using level of DPWM FIFO buffer equal to 32, The FULL (DPWM_STATUS[0]) is set to 1.
bits : 4 - 9 (6 bit)
access : read-only

PDMAEN : PDMA Transfer Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIFO : FIFO Data Input Register DPWM contains 32 words (32x32 bit) data buffer for data transmit. A write to this register pushes data onto the FIFO data buffer and increments the write pointer. This is the address that PDMA writes audio data to. The remaining word number is indicated by FIFOPTR (DPWM_STATUS[8:4]).
bits : 0 - 31 (32 bit)
access : write-only