\n
address_offset : 0x0 Bytes (0x0)
size : 0x88 byte (0x0)
mem_usage : registers
protection :
IRQ0 (BOD) Interrupt Source Identity Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: BOD_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ4 (GPA/B) Interrupt Source Identity Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: GPB_INT
Bit0: GPA_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ5 (ALC) Interrupt Source Identity Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: ALC_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ6 (PWMA) Interrupt Source Identity Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: PWM_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ7 (Reserved) Interrupt Source Identity Register
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ8 (TMR0) Interrupt Source Identity Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: TMR0_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ9 (TMR1) Interrupt Source Identity Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: TMR1_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ10 (Reserved) Interrupt Source Identity Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ11 (Reserved) Interrupt Source Identity Register
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ12 (UART0) Interrupt Source Identity Register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: UART0_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ13 (Reserved) Interrupt Source Identity Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ14 (SPI0) Interrupt Source Identity Register
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: SPI0_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ15 (Reserved) Interrupt Source Identity Register
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ1 (WDT) Interrupt Source Identity Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: WDT_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ16 (Reserved) Interrupt Source Identity Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ17 (Reserved) Interrupt Source Identity Register
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ18 (I2C0) Interrupt Source Identity Register
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: I2C0_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ19 (Reserved) Interrupt Source Identity Register
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ20 (Reserved) Interrupt Source Identity Register
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ21 (TALARM) Interrupt Source Identity Register
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: TALARM_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ22 (Reserved ) Interrupt Source Identity Register
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ23 (Reserved) Interrupt Source Identity Register
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ24 (Reserved) Interrupt Source Identity Register
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ25 (ACMP) Interrupt Source Identity Register
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: TALARM_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ26 (PDMA) Interrupt Source Identity Register
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: PDMA_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ27 (I2S) Interrupt Source Identity Register
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: I2S_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ28 (CAPS) Interrupt Source Identity Register
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: CAPS_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ29 (ADC) Interrupt Source Identity Register
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: ADC_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ30 (Reserved) Interrupt Source Identity Register
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ31 (RTC) Interrupt Source Identity Register
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: RTC_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ2 (EINT0) Interrupt Source Identity Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: INT0_INT
bits : 0 - 2 (3 bit)
access : read-only
NMI Source Interrupt Select Control Register
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NMI_SEL : NMI Source Interrupt Select
The NMI interrupt to Cortex-M0 can be selected from one of the interrupt[31:0]
The NMI_SEL bit[4:0] used to select the NMI interrupt source
bits : 0 - 4 (5 bit)
access : read-write
IRQ_TM : IRQ Test Mode
If set to 1 then peripheral IRQ signals (0-31) are replaced by the value in the MCU_IRQ register. This is a protected register to program first issue the unlock sequence (see Protected Register Lock Key Register (SYS_REGLCTL))
bits : 7 - 7 (1 bit)
access : read-write
MCU IRQ Number Identify Register
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_IRQ : MCU IRQ Source Test Mode
In Normal mode (NMI_SEL register bit [7] aaa 0) The device collects interrupts from each peripheral and synchronizes them to interrupt the Cortex-M0.
In Test mode (NMI_SEL register bit [7] aaa 1), the interrupts from peripherals are blocked, and the interrupts are replaces by MCU_IRQ[31:0].
When MCU_IRQ[n] is 0 : Writing MCU_IRQ[n] 1 will generate an interrupt to Cortex_M0 NVIC[n].
When MCU_IRQ[n] is 1 (meaning an interrupt is asserted) writing MCU_bit[n] '1' will clear the interrupt
Writing MCU_IRQ[n] 0 : has no effect.
bits : 0 - 31 (32 bit)
access : read-write
IRQ3 (EINT1) Interrupt Source Identity Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: INT0_INT
bits : 0 - 2 (3 bit)
access : read-only
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