CLK_PWRCTL (PWRCTL)

CLK_CLKSEL0 (CLKSEL0)

CLK_CLKSEL1 (CLKSEL1)

CLK_CLKDIV0 (CLKDIV0)

CLK_CLKSEL2 (CLKSEL2)

CLK_SLEEPCTL (SLEEPCTL)

CLK_PWRSTSF (PWRSTSF)

CLK_DBGPD (DBGPD)

CLK_AHBCLK (AHBCLK)

CLK_APBCLK0 (APBCLK0)

CLK_DPDSTATE (DPDSTATE)

LXTEN : External 32.768 kHz Crystal Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HIRCEN : OSC49M Oscillator Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIRCEN : OSC16K Oscillator Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STOP : Stop Reserved - do not set to '1'
bits : 9 - 9 (1 bit)
access : read-write

SPDEN : Standby Power Down (SPD) Bit Set to '1' and issue WFI/WFE instruction to enter SPD mode.
bits : 10 - 10 (1 bit)
access : read-write

DPDEN : Deep Power Down (DPD) Bit Set to '1' and issue WFI/WFE instruction to enter DPD mode.
bits : 11 - 11 (1 bit)
access : read-write

WKPINEN : Wakeup Pin Enabled Control Determines whether WAKEUP pin is enabled in DPD mode.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIRCDPDEN : OSC16K Enabled Control Determines whether OSC16K is enabled in DPD mode. If OSC16K is disabled, device cannot wake from DPD with SELWKTMR delay.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SELWKTMR : Select Wakeup Timer SELWKTMR[0] aaa 1: WAKEUP after 128 OSC16K clocks (12.8 ms) SELWKTMR[1] aaa 1: WAKEUP after 256 OSC16K clocks (25.6 ms) SELWKTMR[2] aaa 1: WAKEUP after 512 OSC16K clocks (51.2 ms) SELWKTMR[3] aaa 1: WAKEUP after 1024 OSC16K clocks (102.4ms)
bits : 20 - 23 (4 bit)
access : read-write

WKPINWKF : Pin Wakeup Flag Read Only. This flag indicates that wakeup of device was requested with a high to low transition of the WAKEUP pin. Flag is cleared when DPD mode is entered.
bits : 24 - 24 (1 bit)
access : read-write

TMRWKF : Timer Wakeup Flag Read Only. This flag indicates that wakeup of device was requested with TIMER count of the 16Khz oscillator. Flag is cleared when DPD mode is entered.
bits : 25 - 25 (1 bit)
access : read-write

PORWKF : POI Wakeup Flag Read Only. This flag indicates that wakeup of device was requested with a power-on reset. Flag is cleared when DPD mode is entered.
bits : 26 - 26 (1 bit)
access : read-write

WKTMRSTS : Current Wakeup Timer Setting Read-Only. Read back of the current WAKEUP timer setting. This value is updated with SELWKTMR upon entering DPD mode.
bits : 28 - 31 (4 bit)
access : read-write

HCLKSEL : HCLK Clock Source Select Ensure that related clock sources (pre-select and new-select) are enabled before updating register. These bits are protected, to write to bits first perform the unlock sequence (see Protected Register Lock Key Register (SYS_REGLCTL)) 000 aaa clock source from internal OSC48M oscillator. 001 aaa clock source from external 32kHz crystal clock 010 aaa clock source from internal 16 kHz oscillator clock Others aaa reserved
bits : 0 - 2 (3 bit)
access : read-write

STCLKSEL : MCU Cortex_M0 SysTick Clock Source Select These bits are protected, to write to bits first perform the unlock sequence (see Protected Register Lock Key Register (SYS_REGLCTL)) 000 aaa clock source from 16 kHz internal clock 001 aaa clock source from external 32kHz crystal clock 010 aaa clock source from 16 kHz internal oscillator divided by 2 011 aaa clock source from OSC49M internal oscillator divided by 2 1xx aaa clock source from HCLK / 2 (Default) Note that to use STCLKSEL as source of SysTic timer the CLKSRC bit of SYST_CSR must be set to 0.
bits : 3 - 5 (3 bit)
access : read-write

HIRCFSEL : OSC48M Frequency Select Determines which trim setting to use for OSC48M internal oscillator. Oscillator is factory trimmed within 1% to:
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTSEL : WDT CLK Clock Source Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DPWMCKSEL : Differential Speaker Driver PWM Clock Source Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0SEL : TIMER0 Clock Source Select 000 aaa clock source from internal 16 kHz oscillator 001 aaa clock source from external 32kHz crystal clock 010 aaa clock source from HCLK 011 aaa clock source from external pin (GPIOA[14]) 1xx aaa clock source from internal OSC48M oscillator clock
bits : 8 - 10 (3 bit)
access : read-write

TMR1SEL : TIMER1 Clock Source Select 000 aaa clock source from internal 16 kHz oscillator 001 aaa clock source from external 32kHz crystal clock 010 aaa clock source from HCLK 011 aaa clock source from external pin (GPIOA[15]) 1xx aaa clock source from internal OSC48M oscillator clock
bits : 12 - 14 (3 bit)
access : read-write

PWM0CH01CKSEL : PWM0 And PWM1 Clock Source Select PWM0 and PWM1 uses the same clock source, and prescaler
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HCLKDIV : HCLK Clock Divide Number From HCLK Clock Source The HCLK clock frequency aaa (HCLK clock source frequency) / (HCLKDIV + 1)
bits : 0 - 3 (4 bit)
access : read-write

UARTDIV : UART Clock Divide Number From UART Clock Source The UART clock frequency aaa (UART clock source frequency ) / (UARTDIV + 1)
bits : 8 - 11 (4 bit)
access : read-write

ADCDIV : ADC Clock Divide Number From ADC Clock Source The ADC clock frequency aaa (ADC clock source frequency ) / (ADCDIV + 1)
bits : 16 - 23 (8 bit)
access : read-write

I2S0SEL : I2S Clock Source Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HCLKEN : CPU Clock Sleep Enable (HCLK) Must be left as '1' for normal operation.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMACKEN : PDMA Controller Sleep Clock Enable Control
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPCKEN : Flash ISP Controller Sleep Clock Enable Control
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTCKEN : Watchdog Sleep Clock Enable Control
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTCCKEN : Real-Time- Sleep Clock APB Interface Clock Control
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0CKEN : Timer0 Sleep Clock Enable Control
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1CKEN : Timer1 Sleep Clock Enable Control
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C0CKEN : I2C0 Sleep Clock Enable Control
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI0CKEN : SPI0 Sleep Clock Enable Control
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DPWMCKEN : Differential PWM Speaker Driver Sleep Clock Enable Control
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UARTCKEN : UART0 Sleep Clock Enable Control
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BFALCKEN : Biquad filter/ALC block Sleep Clock Enable Control
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRCCKEN : Cyclic Redundancy Check Sleep Block Clock Enable Control
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0CH01CKEN : PWM Block Sleep Clock Enable Control
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMPCKEN : Analog Comparator Sleep Clock Enable Control
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SBRAMCKEN : Standby RAM Sleep Clock Enable Control
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCCKEN : Audio Analog-Digital-Converter (ADC) Sleep Clock Enable Control
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2S0CKEN : I2S Sleep Clock Enable Control
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ANACKEN : Analog Block Sleep Clock Enable Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DSF : Deep Sleep Flag This flag is set if core logic was placed in Deep Sleep mode. Write '1' to clear flag.
bits : 0 - 0 (1 bit)
access : read-write

STOPF : Stop Flag This flag is set if core logic was stopped but not powered down. Write '1' to clear flag.
bits : 1 - 1 (1 bit)
access : read-write

SPDF : Powered Down Flag This flag is set if core logic was powered down to Standby (SPD). Write '1' to clear flag.
bits : 2 - 2 (1 bit)
access : read-write

DISPDREQ : Disable Power Down
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ICECLKST : ICE_CLK Pin State Read Only. Current state of ICE_CLK pin.
bits : 6 - 6 (1 bit)
access : read-write

ICEDATST : ICE_DAT Pin State Read Only. Current state of ICE_DAT pin.
bits : 7 - 7 (1 bit)
access : read-write

HCLKEN : CPU Clock Enable (HCLK) Must be left as '1' for normal operation.
bits : 0 - 0 (1 bit)
access : read-write

PDMACKEN : PDMA Controller Clock Enable Control
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPCKEN : Flash ISP Controller Clock Enable Control
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTCKEN : Watchdog Clock Enable Control
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTCCKEN : Real-Time-Clock APB Interface Clock Control
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0CKEN : Timer0 Clock Enable Control
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1CKEN : Timer1 Clock Enable Control
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C0CKEN : I2C0 Clock Enable Control
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI0CKEN : SPI0 Clock Enable Control
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DPWMCKEN : Differential PWM Speaker Driver Clock Enable Control
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UARTCKEN : UART0 Clock Enable Control
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BFALCKEN : Biquad Filter And Automatic Level Control Block Clock Enable Control
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRCCKEN : Cyclic Redundancy Check Block Clock Enable Control
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0CH01CKEN : PWM Block Clock Enable Control
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMPCKEN : Analog Comparator Clock Enable Control
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SBRAMCKEN : Standby RAM Clock Enable Control
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCCKEN : Audio Analog-Digital-Converter (ADC) Clock Enable Control
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2S0CKEN : I2S Clock Enable Control
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ANACKEN : Analog Block Clock Enable Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DPDSTSWR : DPD State Write To set the CLK_DPDSTATE register, write value to this register. Data is latched on next DPD event.
bits : 0 - 7 (8 bit)
access : read-write

DPDSTSRD : DPD State Read Back Read back of CLK_DPDSTATE register. This register was preserved from last DPD event .
bits : 8 - 15 (8 bit)
access : read-write