PA_MODE

PA_PIN

PA_DBEN

PA_INTTYPE

GPIO_DBCTL (DBCTL)

PA_INTEN

PA_INTSRC

PA_DINOFF

PB_MODE

PB_DINOFF

PB_DOUT

PB_DATMSK

PB_PIN

PB_DBEN

PB_INTTYPE

PB_INTEN

PB_INTSRC

PA_DOUT

PA_DATMSK

MODE0 : GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE1 : GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE2 : GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE3 : GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE4 : GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE5 : GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins.
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE6 : GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins.
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE7 : GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins.
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE8 : GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins.
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE9 : GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins.
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE10 : GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins.
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE11 : GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE12 : GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins.
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE13 : GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins.
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE14 : GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins.
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE15 : GPIOx I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins.
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIN0 : Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin
bits : 0 - 0 (1 bit)
access : read-only

PIN1 : Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin
bits : 1 - 1 (1 bit)
access : read-only

PIN2 : Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin
bits : 2 - 2 (1 bit)
access : read-only

PIN3 : Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin
bits : 3 - 3 (1 bit)
access : read-only

PIN4 : Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin
bits : 4 - 4 (1 bit)
access : read-only

PIN5 : Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin
bits : 5 - 5 (1 bit)
access : read-only

PIN6 : Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin
bits : 6 - 6 (1 bit)
access : read-only

PIN7 : Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin
bits : 7 - 7 (1 bit)
access : read-only

PIN8 : Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin
bits : 8 - 8 (1 bit)
access : read-only

PIN9 : Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin
bits : 9 - 9 (1 bit)
access : read-only

PIN10 : Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin
bits : 10 - 10 (1 bit)
access : read-only

PIN11 : Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin
bits : 11 - 11 (1 bit)
access : read-only

PIN12 : Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin
bits : 12 - 12 (1 bit)
access : read-only

PIN13 : Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin
bits : 13 - 13 (1 bit)
access : read-only

PIN14 : Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin
bits : 14 - 14 (1 bit)
access : read-only

PIN15 : Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin
bits : 15 - 15 (1 bit)
access : read-only

DBEN0 : Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the GPIO_DBCTL register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN1 : Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the GPIO_DBCTL register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN2 : Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the GPIO_DBCTL register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN3 : Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the GPIO_DBCTL register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN4 : Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the GPIO_DBCTL register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN5 : Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the GPIO_DBCTL register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN6 : Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the GPIO_DBCTL register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN7 : Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the GPIO_DBCTL register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN8 : Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the GPIO_DBCTL register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN9 : Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the GPIO_DBCTL register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN10 : Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the GPIO_DBCTL register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN11 : Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the GPIO_DBCTL register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN12 : Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the GPIO_DBCTL register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN13 : Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the GPIO_DBCTL register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN14 : Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the GPIO_DBCTL register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN15 : Port [A/B] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the GPIO_DBCTL register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE0 : Port [A/B] Edge Or Level Detection Interrupt Control TYPE[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register. If both levels are set no interrupt will occur.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE1 : Port [A/B] Edge Or Level Detection Interrupt Control TYPE[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register. If both levels are set no interrupt will occur.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE2 : Port [A/B] Edge Or Level Detection Interrupt Control TYPE[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register. If both levels are set no interrupt will occur.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE3 : Port [A/B] Edge Or Level Detection Interrupt Control TYPE[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register. If both levels are set no interrupt will occur.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE4 : Port [A/B] Edge Or Level Detection Interrupt Control TYPE[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register. If both levels are set no interrupt will occur.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE5 : Port [A/B] Edge Or Level Detection Interrupt Control TYPE[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register. If both levels are set no interrupt will occur.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE6 : Port [A/B] Edge Or Level Detection Interrupt Control TYPE[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register. If both levels are set no interrupt will occur.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE7 : Port [A/B] Edge Or Level Detection Interrupt Control TYPE[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register. If both levels are set no interrupt will occur.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE8 : Port [A/B] Edge Or Level Detection Interrupt Control TYPE[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register. If both levels are set no interrupt will occur.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE9 : Port [A/B] Edge Or Level Detection Interrupt Control TYPE[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register. If both levels are set no interrupt will occur.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE10 : Port [A/B] Edge Or Level Detection Interrupt Control TYPE[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register. If both levels are set no interrupt will occur.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE11 : Port [A/B] Edge Or Level Detection Interrupt Control TYPE[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register. If both levels are set no interrupt will occur.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE12 : Port [A/B] Edge Or Level Detection Interrupt Control TYPE[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register. If both levels are set no interrupt will occur.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE13 : Port [A/B] Edge Or Level Detection Interrupt Control TYPE[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register. If both levels are set no interrupt will occur.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE14 : Port [A/B] Edge Or Level Detection Interrupt Control TYPE[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register. If both levels are set no interrupt will occur.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE15 : Port [A/B] Edge Or Level Detection Interrupt Control TYPE[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt. If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register. If both levels are set no interrupt will occur.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBCLKSEL : De-bounce Sampling Cycle Selection. For edge level interrupt GPIO state is sampled every 2^(DBCLKSEL) de-bounce clocks. For example if DBCLKSRC aaa 6, then interrupt is sampled every 2^6 aaa 64 de-bounce clocks. If DBCLKSRC is 16KHz oscillator this would be a 64ms de-bounce.
bits : 0 - 3 (4 bit)
access : read-write

DBCLKSRC : De-bounce Counter Clock Source Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ICLKON : Interrupt Clock On Mode Set this bit 0 will gate the clock to the interrupt generation circuit if the GPIOx[n] interrupt is disabled.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN0 : Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low FLIEN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN1 : Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low FLIEN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN2 : Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low FLIEN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN3 : Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low FLIEN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN4 : Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low FLIEN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN5 : Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low FLIEN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN6 : Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low FLIEN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN7 : Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low FLIEN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN8 : Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low FLIEN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN9 : Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low FLIEN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN10 : Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low FLIEN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN11 : Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low FLIEN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN12 : Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low FLIEN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN13 : Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low FLIEN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN14 : Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low FLIEN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN15 : Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low FLIEN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN0 : Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High RHIEN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN1 : Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High RHIEN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN2 : Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High RHIEN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN3 : Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High RHIEN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN4 : Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High RHIEN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN5 : Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High RHIEN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN6 : Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High RHIEN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN7 : Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High RHIEN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN8 : Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High RHIEN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN9 : Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High RHIEN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN10 : Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High RHIEN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN11 : Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High RHIEN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN12 : Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High RHIEN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN13 : Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High RHIEN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN14 : Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High RHIEN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN15 : Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High RHIEN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC0 : Port [A/B] Interrupt Trigger Source Indicator Read : 1 aaa Indicates GPIOx[n] generated an interrupt 0 aaa No interrupt from GPIOx[n] Write : 1 aaa Clear the corresponding pending interrupt. 0 aaa No action
bits : 0 - 0 (1 bit)
access : read-write

INTSRC1 : Port [A/B] Interrupt Trigger Source Indicator Read : 1 aaa Indicates GPIOx[n] generated an interrupt 0 aaa No interrupt from GPIOx[n] Write : 1 aaa Clear the corresponding pending interrupt. 0 aaa No action
bits : 1 - 1 (1 bit)
access : read-write

INTSRC2 : Port [A/B] Interrupt Trigger Source Indicator Read : 1 aaa Indicates GPIOx[n] generated an interrupt 0 aaa No interrupt from GPIOx[n] Write : 1 aaa Clear the corresponding pending interrupt. 0 aaa No action
bits : 2 - 2 (1 bit)
access : read-write

INTSRC3 : Port [A/B] Interrupt Trigger Source Indicator Read : 1 aaa Indicates GPIOx[n] generated an interrupt 0 aaa No interrupt from GPIOx[n] Write : 1 aaa Clear the corresponding pending interrupt. 0 aaa No action
bits : 3 - 3 (1 bit)
access : read-write

INTSRC4 : Port [A/B] Interrupt Trigger Source Indicator Read : 1 aaa Indicates GPIOx[n] generated an interrupt 0 aaa No interrupt from GPIOx[n] Write : 1 aaa Clear the corresponding pending interrupt. 0 aaa No action
bits : 4 - 4 (1 bit)
access : read-write

INTSRC5 : Port [A/B] Interrupt Trigger Source Indicator Read : 1 aaa Indicates GPIOx[n] generated an interrupt 0 aaa No interrupt from GPIOx[n] Write : 1 aaa Clear the corresponding pending interrupt. 0 aaa No action
bits : 5 - 5 (1 bit)
access : read-write

INTSRC6 : Port [A/B] Interrupt Trigger Source Indicator Read : 1 aaa Indicates GPIOx[n] generated an interrupt 0 aaa No interrupt from GPIOx[n] Write : 1 aaa Clear the corresponding pending interrupt. 0 aaa No action
bits : 6 - 6 (1 bit)
access : read-write

INTSRC7 : Port [A/B] Interrupt Trigger Source Indicator Read : 1 aaa Indicates GPIOx[n] generated an interrupt 0 aaa No interrupt from GPIOx[n] Write : 1 aaa Clear the corresponding pending interrupt. 0 aaa No action
bits : 7 - 7 (1 bit)
access : read-write

INTSRC8 : Port [A/B] Interrupt Trigger Source Indicator Read : 1 aaa Indicates GPIOx[n] generated an interrupt 0 aaa No interrupt from GPIOx[n] Write : 1 aaa Clear the corresponding pending interrupt. 0 aaa No action
bits : 8 - 8 (1 bit)
access : read-write

INTSRC9 : Port [A/B] Interrupt Trigger Source Indicator Read : 1 aaa Indicates GPIOx[n] generated an interrupt 0 aaa No interrupt from GPIOx[n] Write : 1 aaa Clear the corresponding pending interrupt. 0 aaa No action
bits : 9 - 9 (1 bit)
access : read-write

INTSRC10 : Port [A/B] Interrupt Trigger Source Indicator Read : 1 aaa Indicates GPIOx[n] generated an interrupt 0 aaa No interrupt from GPIOx[n] Write : 1 aaa Clear the corresponding pending interrupt. 0 aaa No action
bits : 10 - 10 (1 bit)
access : read-write

INTSRC11 : Port [A/B] Interrupt Trigger Source Indicator Read : 1 aaa Indicates GPIOx[n] generated an interrupt 0 aaa No interrupt from GPIOx[n] Write : 1 aaa Clear the corresponding pending interrupt. 0 aaa No action
bits : 11 - 11 (1 bit)
access : read-write

INTSRC12 : Port [A/B] Interrupt Trigger Source Indicator Read : 1 aaa Indicates GPIOx[n] generated an interrupt 0 aaa No interrupt from GPIOx[n] Write : 1 aaa Clear the corresponding pending interrupt. 0 aaa No action
bits : 12 - 12 (1 bit)
access : read-write

INTSRC13 : Port [A/B] Interrupt Trigger Source Indicator Read : 1 aaa Indicates GPIOx[n] generated an interrupt 0 aaa No interrupt from GPIOx[n] Write : 1 aaa Clear the corresponding pending interrupt. 0 aaa No action
bits : 13 - 13 (1 bit)
access : read-write

INTSRC14 : Port [A/B] Interrupt Trigger Source Indicator Read : 1 aaa Indicates GPIOx[n] generated an interrupt 0 aaa No interrupt from GPIOx[n] Write : 1 aaa Clear the corresponding pending interrupt. 0 aaa No action
bits : 14 - 14 (1 bit)
access : read-write

INTSRC15 : Port [A/B] Interrupt Trigger Source Indicator Read : 1 aaa Indicates GPIOx[n] generated an interrupt 0 aaa No interrupt from GPIOx[n] Write : 1 aaa Clear the corresponding pending interrupt. 0 aaa No action
bits : 15 - 15 (1 bit)
access : read-write

DINOFF16 : GPIOx Pin[n] OFF Digital Input Path Enable
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF17 : GPIOx Pin[n] OFF Digital Input Path Enable
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF18 : GPIOx Pin[n] OFF Digital Input Path Enable
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF19 : GPIOx Pin[n] OFF Digital Input Path Enable
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF20 : GPIOx Pin[n] OFF Digital Input Path Enable
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF21 : GPIOx Pin[n] OFF Digital Input Path Enable
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF22 : GPIOx Pin[n] OFF Digital Input Path Enable
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF23 : GPIOx Pin[n] OFF Digital Input Path Enable
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF24 : GPIOx Pin[n] OFF Digital Input Path Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF25 : GPIOx Pin[n] OFF Digital Input Path Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF26 : GPIOx Pin[n] OFF Digital Input Path Enable
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF27 : GPIOx Pin[n] OFF Digital Input Path Enable
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF28 : GPIOx Pin[n] OFF Digital Input Path Enable
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF29 : GPIOx Pin[n] OFF Digital Input Path Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF30 : GPIOx Pin[n] OFF Digital Input Path Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF31 : GPIOx Pin[n] OFF Digital Input Path Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT0 : GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT1 : GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT2 : GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT3 : GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT4 : GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT5 : GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT6 : GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT7 : GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT8 : GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT9 : GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT10 : GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT11 : GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT12 : GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT13 : GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT14 : GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT15 : GPIOx Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATMSK0 : Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DATMSK bit[n] to 1 , the corresponding DOUTn bit is write-protected.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATMSK1 : Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DATMSK bit[n] to 1 , the corresponding DOUTn bit is write-protected.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATMSK2 : Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DATMSK bit[n] to 1 , the corresponding DOUTn bit is write-protected.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATMSK3 : Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DATMSK bit[n] to 1 , the corresponding DOUTn bit is write-protected.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATMSK4 : Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DATMSK bit[n] to 1 , the corresponding DOUTn bit is write-protected.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATMSK5 : Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DATMSK bit[n] to 1 , the corresponding DOUTn bit is write-protected.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATMSK6 : Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DATMSK bit[n] to 1 , the corresponding DOUTn bit is write-protected.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATMSK7 : Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DATMSK bit[n] to 1 , the corresponding DOUTn bit is write-protected.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATMSK8 : Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DATMSK bit[n] to 1 , the corresponding DOUTn bit is write-protected.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATMSK9 : Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DATMSK bit[n] to 1 , the corresponding DOUTn bit is write-protected.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATMSK10 : Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DATMSK bit[n] to 1 , the corresponding DOUTn bit is write-protected.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATMSK11 : Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DATMSK bit[n] to 1 , the corresponding DOUTn bit is write-protected.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATMSK12 : Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DATMSK bit[n] to 1 , the corresponding DOUTn bit is write-protected.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATMSK13 : Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DATMSK bit[n] to 1 , the corresponding DOUTn bit is write-protected.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATMSK14 : Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DATMSK bit[n] to 1 , the corresponding DOUTn bit is write-protected.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATMSK15 : Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DATMSK bit[n] to 1 , the corresponding DOUTn bit is write-protected.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.